PIC24FJ32GB004 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x0057F8), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
CONFIG4 · 0x57F8 0xFFFF default 0xFFFF DSWDTEN Deep Sleep Watchdog Timer DSWDT disabled DSWDT enabled DSBOREN Deep Sleep BOR Enable bit BOR disabled in Deep Sleep BOR enabled in Deep Sleep RTCCKSEL RTCC Reference Oscillator Select RTCC uses Low Power RC Oscillator (LPRC) RTCC uses Secondary Oscillator (SOSC) DSWCKSEL Deep Sleep Watchdog Timer Oscillator Select DSWDT uses Secondary Oscillator (SOSC) DSWDT uses Low Power RC Oscillator (LPRC) DSWDTPS DSWDT Postscale Select 1:2 (2.1 ms) 1:8 (8.3 ms) 1:32 (33 ms) 1:128 (132 ms) 1:512 (528 ms) 1:2,048 (2.1 seconds) 1:8,192 (8.5 seconds) 1:32,768 (34 seconds) 1:131,072 (135 seconds) 1:524,288 (9 minutes) 1:2,097,152 (36 minutes) 1:8,388,608 (2.4 hours) 1:33,554,432 (9.6 hours) 1:134,217,728 (38.5 hours) 1:536,870,912 (6.4 days) 1:2,147,483,648 (25.7 days) CONFIG3 · 0x57FA 0xFFFF default 0xFFFF WPEND Segment Write Protection End Page Select Write Protect from page 0 to WPFP Write Protect from WPFP to the last page of memory WPCFG Write Protect Configuration Page Select Last page and Flash Configuration words are code-protected Last page and Flash Configuration words are unprotected WPDIS Segment Write Protection Disable Segmented code protection enabled Segmented code protection disabled WUTSEL Voltage Regulator Wake-up Time Select Fast regulator start-up time used Default regulator start-up time used SOSCSEL Secondary Oscillator Pin Mode Select SOSC pins have digital I/O functions (RA4, RB4) SOSC pins in Low-Power (low drive-strength) Oscillator Mode SOSC pins in Default (high drive-strength) Oscillator Mode WPFP Write Protection Flash Page Segment Boundary Page 0 (0x0) Page 1 (0x400) Page 2 (0x800) Page 3 (0xC00) Page 4 (0x1000) Page 5 (0x1400) Page 6 (0x1800) Page 7 (0x1C00) Page 8 (0x2000) Page 9 (0x2400) Page 10 (0x2800) Page 11 (0x2C00) Page 12 (0x3000) Page 13 (0x3400) Page 14 (0x3800) Page 15 (0x3C00) Page 16 (0x4000) Page 17 (0x4400) Page 18 (0x4800) Page 19 (0x4C00) Page 20 (0x5000) Page 21 (0x5400) Highest Page (same as page 21) CONFIG2 · 0x57FC 0xFFFF default 0xFFFF IESO Internal External Switchover IESO mode (Two-Speed Start-up) disabled IESO mode (Two-Speed Start-up) enabled PLLDIV USB 96 MHz PLL Prescaler Select Oscillator input used directly (4 MHz input) Oscillator input divided by 2 (8 MHz input) Oscillator input divided by 3 (12 MHz input) Oscillator input divided by 4 (16 MHz input) Oscillator input divided by 5 (20 MHz input) Oscillator input divided by 6 (24 MHz input) Oscillator input divided by 8 (32 MHz input) Oscillator input divided by 12 (48 MHz input) PLL96MHZ 96MHz PLL Startup Select 96 MHz PLL Startup is enabled by user in software( controlled with the PLLEN bit) 96 MHz PLL Startup is enabled automatically on start-up FNOSC Initial Oscillator Select Fast RC Oscillator (FRC) Fast RC Oscillator with Postscaler and PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Fast RC Oscillator with Postscaler (FRCDIV) FCKSM Clock Switching and Fail-Safe Clock Monitor Sw Enabled, Mon Enabled Sw Enabled, Mon Disabled Sw Disabled, Mon Disabled 3 (not named) OSCIOFNC OSCO Pin Configuration OSCO pin functions as port I/O (RA3) OSCO pin functions as clock output (CLKO) IOL1WAY IOLOCK One-Way Set Enable The IOLOCK bit can be set and cleared using the unlock sequence Once set, the IOLOCK bit cannot be cleared I2C1SEL I2C1 Pin Select bit Use alternate SCL1/SDA1 pins for I2C1 Use default SCL1/SDA1 pins for I2C1 POSCMOD Primary Oscillator Select EC Oscillator mode selected XT Oscillator mode selected HS Oscillator mode selected Primary Oscillator disabled CONFIG1 · 0x57FE 0x7FFF default 0x7FFF JTAGEN JTAG Port Enable JTAG port is disabled JTAG port is enabled GCP General Segment Code Protect Code protection is enabled for the entire program memory space Code protection is disabled GWRP General Segment Write Protect Writes to program memory are disabled Writes to program memory are allowed ICS Emulator Pin Placement Select bits Emulator functions are shared with PGEC3/PGED3 Emulator functions are shared with PGEC2/PGED2 Emulator functions are shared with PGEC1/PGED1 FWDTEN Watchdog Timer Watchdog Timer is disabled Watchdog Timer is enabled WINDIS Windowed WDT Windowed Watchdog Timer enabled; FWDTEN must be 1 Standard Watchdog Timer enabled,(Windowed-mode is disabled) FWPSA WDT Prescaler Prescaler ratio of 1:32 Prescaler ratio of 1:128 WDTPS Watchdog Timer Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 
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