PIC24FJ64GU202 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they are the last words of flash (from 0x00AF00), programmed with the code. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FSEC · 0xAF00 0xFFFFFF default 0xFFFFFF AIVTDIS Alternate Interrupt Vector Table bit Enabled AIVT Disabled AIVT CSS Configuration Segment Code-Protect Level bits High Security Enhanced Security Standard Security No Protection (other than CWRP) CWRP Configuration Segment Write-Protect bit Configuration Segment is write protected Configuration Segment may be written GSS General Segment Code-Protect Level bits High Security Standard Security No Protection (other than GWRP) GWRP General Segment Write-Protect bit General Segment is write protected General Segment may be written BSEN Boot Segment Control bit Boot Segment size determined by FBSLIM No Boot Segment BSS Boot Segment Code-Protect Level bits High Security Standard Security No Protection (other than BWRP) BWRP Boot Segment Write-Protect bit Boot Segment is write protected Boot Segment may be written FBSLIM · 0xAF10 0xFFFFFF default 0xFFFFFF BSLIM Boot Segment Flash Page Address Limit bits FSIGN · 0xAF14 0xFF7FFF default 0xFF7FFF SIGN Signature Bit FOSCSEL · 0xAF18 0xFFFFFF default 0xFFFFFF IESO Two-speed Oscillator Start-up Enable bit Start up with user-selected oscillator source Start up device with FRC, then switch to user-selected oscillator source PLLMODE PLL Mode Selection 96 MHz PLL. Oscillator input is divided by 1 (4 MHz input) 96 MHz PLL. Oscillator input is divided by 2 (8 MHz input) 96 MHz PLL. Oscillator input is divided by 3 (12 MHz input) 96 MHz PLL. Oscillator input is divided by 4 (16 MHz input) 96 MHz PLL. Oscillator input is divided by 5 (20 MHz input) 96 MHz PLL. Oscillator input is divided by 6 (24 MHz input) 96 MHz PLL. Oscillator input is divided by 8 (32 MHz input) 96 MHz PLL. Oscillator input is divided by 12 (48 MHz input) 4x PLL selected 6x PLL selected 8x PLL selected No PLL used; PLLEN bit is not available FNOSC Oscillator Source Selection Internal Fast RC (FRC) Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) Primary Oscillator (XT, HS, EC) Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) Secondary Oscillator (SOSC) Low-Power RC Oscillator (LPRC) Oscillator with Divider FOSC · 0xAF1C 0xFFFFFF default 0xFFFFFF FCKSM Clock Switching Mode bits Both Clock switching and Fail-safe Clock Monitor are enabled Clock switching is enabled,Fail-safe Clock Monitor is disabled Both Clock switching and Fail-safe Clock Monitor are disabled 3 (not named) IOL1WAY Peripheral pin select configuration bit Allow multiple reconfigurations Allow only one reconfiguration PLLSS PLL Secondary Selection Configuration bit PLL is fed by the on-chip Fast RC (FRC) oscillator PLL is fed by the Primary oscillator SOSCSEL SOSC Selection Configuration bits Digital (SCLKI) mode SOSC is used in crystal (SOSCI/SOSCO) mode OSCIOFCN OSC2 Pin Function bit OSC2 is general purpose digital I/O pin OSC2 is clock output POSCMD Primary Oscillator Mode Select bits EC (External Clock) Mode XT Crystal Oscillator Mode HS Crystal Oscillator Mode Primary Oscillator disabled FWDT · 0xAF20 0xFFFFFF default 0xFFFFFF WDTCLK WDT Clock Source Select bits WDT uses system clock when active, LPRC while in Sleep mode WDT uses SOSC input WDT uses 31 kHz source from FRC when active in Windowed WDT WDT uses LPRC WDTCMX WDT MUX Source Select bits WDT always uses LPRC as its clock source WDT clock source is determined by the WDTCLK Configuration bits WDTWIN Watchdog Timer Window Select bits WDT Windo is 75% of WDT period WDT Window is 50% of WDT period WDT Window is 37.5% of WDT period WDT Window is 25% of WDT period WINDIS Watchdog Timer Window Enable bit Watchdog Timer in Window mode Watchdog Timer in Non-Window mode FWDTEN Watchdog Timer Enable bits WDT and SWDTEN disabled WDT Enabled only while device is active (disabled in sleep, SWDTEN disabled) WDT Enabled/Disabled (controlled using SWDTEN bit) WDT Enabled FWPSA Watchdog Timer Prescaler bit 1:32 1:128 WDTPS Watchdog Timer Postscaler bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xAF24 0xFFFFFF default 0xFFFFFF LPBOREN Downside Voltage Protection Enable bit Low Power BOR is disabled Low Power BOR is enabled and active when main BOR is inactive LPREGEN Low power regulator control Low Voltage and Low Power Regulator are available and controlled by the RETEN bit during Sleep mode Low Voltage and Low Power Regulator are not available BOREN Brown Out Enable bit Brown-out Reset is Disabled Brown-out Reset is controlled with the SBOREN bit Brown-out Reset is enabled only while device is active and is disabled in Sleep Brown-out Reset is Enabled FICD · 0xAF28 0xFFFFDF default 0xFFFFDF JTAGEN JTAG Enable bit JTAG is disabled JTAG is enabled ICS ICD Communication Channel Select bits Reserved, do not use Communicate on PGEC3 and PGED3 Communicate on PGEC2 and PGED2 Communicate on PGEC1 and PGED1 FDMTIVTL · 0xAF2C 0xFFFFFF default 0xFFFFFF DMTIVTL Deadman Timer Interval Low Word FDMTIVTH · 0xAF30 0xFFFFFF default 0xFFFFFF DMTIVTH Deadman Timer Interval High Word FDMTCNTL · 0xAF34 0xFFFFFF default 0xFFFFFF DMTCNTL Deadman Timer Instruction Count Low Word FDMTCNTH · 0xAF38 0xFFFFFF default 0xFFFFFF DMTCNTH Deadman Timer Instruction Count High Word FMDT · 0xAF3C 0xFFFFFF default 0xFFFFFF DMTDIS Deadman Timer Enable Bit Dead Man Timer is Enabled and cannot be disabled by software Dead Man Timer is Disabled and can be enabled by software FDEVOPT1 · 0xAF40 0xFFFFFF default 0xFFFFFF SMB3EN SM Bus Enable Normal SMBus input levels SMBus 3.0 input levels ALTCMP2 Alternate Comparator 2 Input Enable bit AC2INC is on RB9 and AC2IND is on RA3 C2INC is on RA4 and C2IND is on RB4 ALTI2C1 Alternate I2C pin Location I2C1 Pin mapped to ASCL1/ASDA1 pins I2C1 Pin mapped to SDA1/SCL1 pins SOSCHP SOSC High Power Enable bit (valid only when SOSCSEL = 1 Enable SOSC low power mode Enable SOSC high power mode (default) TMPRPIN Tamper Pin Enable bit TMPRN pin function is enabled TMPRN pin function is disabled ALTCMP1 Alternate Comparator 1 Input Enable bit AC1INC and AC3INC are on RB9 C1INC is on RB13 and C3INC is on RA0 
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