PIC24HJ256GP206 configuration bits The configuration words set the oscillator and PLL, the watchdog, the debugger pins, brown-out reset and code protection: they sit in their own configuration memory at 0xF80000. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC16 each setting is a #pragma config FNOSC = FRC line.
FBS · 0xF80000 0x00CF default 0x00CF RBS Boot Segment RAM Protection Large-sized Boot RAM Large-sized Boot RAM Medium-sized Boot RAM Medium-sized Boot RAM Small-sized Boot RAM Small-sized Boot RAM No Boot RAM No Boot RAM BSS Boot Segment Program Flash Code Protection High Security, Large-sized Boot Flash High Security, Large-sized Boot Flash High Security, Medium-sized Boot Flash High Security, Medium-sized Boot Flash High Security, Small-sized Boot Flash High Security, Small-sized Boot Flash Standard Security, Large-sized Boot Flash Standard Security, Large-sized Boot Flash Standard Security, Medium-sized Boot Flash Standard Security, Medium-sized Boot Flash Standard Security, Small-sized Boot Flash Standard Security, Small-sized Boot Flash No Boot program Flash segment No Boot program Flash segment BWRP Boot Segment Write Protect Boot segment is write-protected Boot Segment may be written FSS · 0xF80002 0x00CF default 0x00CF RES Reserved RSS Secure Segment Data RAM Protection Large-sized Secure RAM Large-sized Secure RAM Medium-sized Secure RAM Medium-sized Secure RAM Small-sized Secure RAM Small-sized Secure RAM No Secure RAM No Secure RAM SSS Secure Segment Program Flash Code Protection High Security, Large-sized Secure Flash High Security, Large-sized Secure Flash High Security, Medium-sized Secure Flash High Security, Medium-sized Secure Flash High Security, Small-sized Secure Flash High Security, Small-sized Secure Flash Standard Security, Large-sized Secure Flash Standard Security, Large-sized Secure Flash Standard Security, Medium-sized Secure Flash Standard Security, Medium-sized Secure Flash Standard Security, Small-sized Secure Flash Standard Security, Small-sized Secure Flash No Secure Segment No Secure Segment SWRP Secure Segment Program Write Protect Secure segment is write-protected Secure segment may be written FGS · 0xF80004 0x0007 default 0x0007 GSS General Segment Code Protection High Security Code Protection is Enabled Standard Security Code Protection is Enabled User program memory is not code-protected GWRP General Code Segment Write Protect User program memory is write-protected User program memory is not write-protected FOSCSEL · 0xF80006 0xFFFF default 0xFFFF IESO Two-speed Oscillator Start-Up Enable Start up with user-selected oscillator Start up with FRC, then switch TEMP Temperature Protection Enable Temperature protection enabled Temperature protection disabled FNOSC Oscillator Mode Internal Fast RC (FRC) Internal Fast RC (FRC) w/ PLL Primary Oscillator (XT, HS, EC) Primary Oscillator (XT, HS, EC) w/ PLL Secondary Oscillator (SOSC) Low Power RC Oscillator (LPRC) Internal Fast RC (FRC) divide by 16 Internal Fast RC (FRC) with divide by N FOSC · 0xF80008 0xFFFF default 0xFFFF FCKSM Clock Switching and Monitor Both Clock Switching and Fail-Safe Clock Monitor are enabled Clock switching is enabled, Fail-Safe Clock Monitor is disabled Both Clock Switching and Fail-Safe Clock Monitor are disabled 3 (not named) OSCIOFNC OSC2 Pin Function OSC2 pin has digital I/O function OSC2 pin has clock out function POSCMD Primary Oscillator Source EC Oscillator Mode XT Oscillator Mode HS Oscillator Mode Primary Oscillator Disabled FWDT · 0xF8000A 0xFFFF default 0xFFFF FWDTEN Watchdog Timer Enable Watchdog timer enabled/disabled by user software Watchdog timer always enabled WINDIS Watchdog Timer Window Watchdog Timer in Window mode Watchdog Timer in Non-Window mode WDTPRE WDT Prescaler 1:32 1:128 WDTPOST Watchdog Timer Postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1,024 1:2,048 1:4,096 1:8,192 1:16,384 1:32,768 FPOR · 0xF8000C 0xFFFF default 0xFFFF RES Reserved FPWRT POR Timer Value Disabled 2ms 4ms 8ms 16ms 32ms 64ms 128ms FICD · 0xF8000E 0xFFDF default 0xFFDF BACKBUG Background Debug Enabled Disabled COE Set Clip On Emulation Mode Reset Into Clip On Emulation Mode Reset Into Operational Mode JTAGEN JTAG Port Enable JTAG is Disabled JTAG is Enabled ICS Comm Channel Select Communicate on PGC3/EMUC3 and PGD3/EMUD3 Communicate on PGC2/EMUC2 and PGD2/EMUD2 Communicate on PGC1/EMUC1 and PGD1/EMUD1 
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