The 56 registers of DSU (Device Service Unit), from 0x41002000, with their reset value and every field. The PIC32CM1216LE00032 has 1252 registers in 40 peripherals, one page each.
DSU Device Service Unit
CTRLControl
Address
0x41002000
Reset
0x00
Access
write only
7–
6–
5–
4–
3MBIST
2CRC
1–
0SWRST
3 fields
Field
Bits
What it does
MBIST
3
Memory built-in self-test
CRC
2
32-bit Cyclic Redundancy Code
SWRST
0
Software Reset
STATUSAStatus A
Address
0x41002001
Reset
0x00
Access
read/write
7–
6–
5BREXT
4PERR
3FAIL
2BERR
1CRSTEXT
0DONE
6 fields
Field
Bits
What it does
BREXT
5
BootRom Phase Extension
PERR
4
Protection Error
FAIL
3
Failure
BERR
2
Bus Error
CRSTEXT
1
CPU Reset Phase Extension
DONE
0
Done
STATUSBStatus B
Address
0x41002002
Reset
0x00
Access
read only
7BCCD1
6BCCD0
5DCCD1
4DCCD0
3HPE
2DBGPRES
1DAL1
0DAL0
7 fields
Field
Bits
What it does
BCCD1
7
Boot ROM Communication Channel 1 Dirty
BCCD0
6
Boot ROM Communication Channel 0 Dirty
DCCD1
5
Debug Communication Channel 1 Dirty
DCCD0
4
Debug Communication Channel 0 Dirty
HPE
3
Hot-Plugging Enable
DBGPRES
2
Debugger Present
DAL
1:0
Debugger Access Level
0 Debugger can only access the DSU external address space.
2 Debugger can access any regions.
ADDRAddress
Address
0x41002004
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
AMOD
1:0
Access Mode
ADDR
31:2
Address
LENGTHLength
Address
0x41002008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LENGTH
31:2
Length
DATAData
Address
0x4100200C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC0Debug Communication Channel n
Address
0x41002010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC1Debug Communication Channel n
Address
0x41002014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DIDDevice Identification
Address
0x41002018
Reset
0x2085200B
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
FAMILY
27:23
Family
1 PIC32CM Ultra-Low Power Entry Level Families
SERIES
21:16
Series
5 Low Power
6 Low Power and Security
7 Low Power and Security with CryptoAuthentication Device
DIE
15:12
Die Number
REVISION
11:8
Revision Number
DEVSEL
7:0
Device Select
0 512 KB Flash / 64 KB SRAM / 100-pin
1 512 KB Flash / 64 KB SRAM / 64-pin
2 512 KB Flash / 64 KB SRAM / 48-pin
4 256 KB Flash / 32 KB SRAM / 100-pin
5 256 KB Flash / 32 KB SRAM / 64-pin
6 256 KB Flash / 32 KB SRAM / 48-pin
10 128 KB Flash / 16 KB SRAM / 48-pin
11 128 KB Flash / 16 KB SRAM / 32-pin
PROCESSOR
31:28
Processor
2 Cortex-M23
CFGConfiguration
Address
0x4100201C
Reset
0x00000002
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
DCCDMALEVEL1
3
DMA Trigger Level 1
0 Signals to the DMA that a data is available for read
1 Signals to the DMA that a data is available for write
DCCDMALEVEL0
2
DMA Trigger Level 0
0 Signals to the DMA that a data is available for read
1 Signals to the DMA that a data is available for write
LQOS
1:0
Latency Quality Of Service
BCC0Boot ROM Communication Channel n
Address
0x41002020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
BCC1Boot ROM Communication Channel n
Address
0x41002024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
CTRLControl
Address
0x41002100
Reset
0x00
Access
write only
7–
6–
5–
4–
3MBIST
2CRC
1–
0SWRST
3 fields
Field
Bits
What it does
MBIST
3
Memory built-in self-test
CRC
2
32-bit Cyclic Redundancy Code
SWRST
0
Software Reset
STATUSAStatus A
Address
0x41002101
Reset
0x00
Access
read/write
7–
6–
5BREXT
4PERR
3FAIL
2BERR
1CRSTEXT
0DONE
6 fields
Field
Bits
What it does
BREXT
5
BootRom Phase Extension
PERR
4
Protection Error
FAIL
3
Failure
BERR
2
Bus Error
CRSTEXT
1
CPU Reset Phase Extension
DONE
0
Done
STATUSBStatus B
Address
0x41002102
Reset
0x00
Access
read only
7BCCD1
6BCCD0
5DCCD1
4DCCD0
3HPE
2DBGPRES
1DAL1
0DAL0
7 fields
Field
Bits
What it does
BCCD1
7
Boot ROM Communication Channel 1 Dirty
BCCD0
6
Boot ROM Communication Channel 0 Dirty
DCCD1
5
Debug Communication Channel 1 Dirty
DCCD0
4
Debug Communication Channel 0 Dirty
HPE
3
Hot-Plugging Enable
DBGPRES
2
Debugger Present
DAL
1:0
Debugger Access Level
0 Debugger can only access the DSU external address space.
2 Debugger can access any regions.
ADDRAddress
Address
0x41002104
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
AMOD
1:0
Access Mode
ADDR
31:2
Address
LENGTHLength
Address
0x41002108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LENGTH
31:2
Length
DATAData
Address
0x4100210C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC0Debug Communication Channel n
Address
0x41002110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC1Debug Communication Channel n
Address
0x41002114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DIDDevice Identification
Address
0x41002118
Reset
0x2085200B
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
FAMILY
27:23
Family
1 PIC32CM Ultra-Low Power Entry Level Families
SERIES
21:16
Series
5 Low Power
6 Low Power and Security
7 Low Power and Security with CryptoAuthentication Device
DIE
15:12
Die Number
REVISION
11:8
Revision Number
DEVSEL
7:0
Device Select
0 512 KB Flash / 64 KB SRAM / 100-pin
1 512 KB Flash / 64 KB SRAM / 64-pin
2 512 KB Flash / 64 KB SRAM / 48-pin
4 256 KB Flash / 32 KB SRAM / 100-pin
5 256 KB Flash / 32 KB SRAM / 64-pin
6 256 KB Flash / 32 KB SRAM / 48-pin
10 128 KB Flash / 16 KB SRAM / 48-pin
11 128 KB Flash / 16 KB SRAM / 32-pin
PROCESSOR
31:28
Processor
2 Cortex-M23
CFGConfiguration
Address
0x4100211C
Reset
0x00000002
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
DCCDMALEVEL1
3
DMA Trigger Level 1
0 Signals to the DMA that a data is available for read
1 Signals to the DMA that a data is available for write
DCCDMALEVEL0
2
DMA Trigger Level 0
0 Signals to the DMA that a data is available for read
1 Signals to the DMA that a data is available for write