BETACTRLAControl A
- Address
0x4100A000- Reset
0x00- Access
- read/write
- 7MODE
- 6–
- 5–
- 4–
- 3–
- 2RUNSTDBY
- 1ENABLE
- 0SWRST
4 fields
| Field | Bits | What it does |
|---|---|---|
| MODE | 7 | Operating Mode
|
| RUNSTDBY | 2 | Run in Standby Mode |
| ENABLE | 1 | Enable |
| SWRST | 0 | Software Reset |
PIC32CM1216LE00032 USB registers
The 143 registers of USB (Universal Serial Bus), from 0x4100A000, with their reset value and every field. The PIC32CM1216LE00032 has 1252 registers in 40 peripherals, one page each.
USB Universal Serial Bus
SYNCBUSYSynchronization Busy
- Address
0x4100A002- Reset
0x00- Access
- read only
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1ENABLE
- 0SWRST
2 fields
| Field | Bits | What it does |
|---|---|---|
| ENABLE | 1 | Enable Synchronization Busy |
| SWRST | 0 | Software Reset Synchronization Busy |
QOSCTRLUSB Quality Of Service
- Address
0x4100A003- Reset
0x0F- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3DQOS1
- 2DQOS0
- 1CQOS1
- 0CQOS0
2 fields
| Field | Bits | What it does |
|---|---|---|
| DQOS | 3:2 | Data Quality of Service |
| CQOS | 1:0 | Configuration Quality of Service |
DEVICE.CTRLBDEVICE Control B
- Address
0x4100A008- Reset
0x0001- Access
- read/write
- Size
- 16-bit
6 fields
| Field | Bits | What it does |
|---|---|---|
| LPMHDSK | 11:10 | Link Power Management Handshake
|
| GNAK | 9 | Global NAK |
| NREPLY | 4 | No Reply |
| SPDCONF | 3:2 | Speed Configuration
|
| UPRSM | 1 | Upstream Resume |
| DETACH | 0 | Detach |
HOST.CTRLBHOST Control B
- Address
0x4100A008- Reset
0x0000- Access
- read/write
- Size
- 16-bit
7 fields
| Field | Bits | What it does |
|---|---|---|
| L1RESUME | 11 | Send L1 Resume |
| VBUSOK | 10 | VBUS is OK |
| BUSRESET | 9 | Send USB Reset |
| SOFE | 8 | Start of Frame Generation Enable |
| AUTORESUME | 4 | Auto Resume Enable |
| SPDCONF | 3:2 | Speed Configuration for Host
|
| RESUME | 1 | Send USB Resume |
DEVICE.DADDDEVICE Device Address
- Address
0x4100A00A- Reset
0x00- Access
- read/write
- 7ADDEN
- 6DADD6
- 5DADD5
- 4DADD4
- 3DADD3
- 2DADD2
- 1DADD1
- 0DADD0
2 fields
| Field | Bits | What it does |
|---|---|---|
| ADDEN | 7 | Device Address Enable |
| DADD | 6:0 | Device Address |
HOST.HSOFCHOST Host Start Of Frame Control
- Address
0x4100A00A- Reset
0x00- Access
- read/write
- 7FLENCE
- 6–
- 5–
- 4–
- 3FLENC3
- 2FLENC2
- 1FLENC1
- 0FLENC0
2 fields
| Field | Bits | What it does |
|---|---|---|
| FLENCE | 7 | Frame Length Control Enable |
| FLENC | 3:0 | Frame Length Control |
DEVICE.STATUSDEVICE Status
- Address
0x4100A00C- Reset
0x40- Access
- read only
- 7LINESTATE1
- 6LINESTATE0
- 5–
- 4–
- 3SPEED1
- 2SPEED0
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|---|---|
| LINESTATE | 7:6 | USB Line State Status
|
| SPEED | 3:2 | Speed Status
|
HOST.STATUSHOST Status
- Address
0x4100A00C- Reset
0x00- Access
- read only
- 7LINESTATE1
- 6LINESTATE0
- 5–
- 4–
- 3SPEED1
- 2SPEED0
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|---|---|
| LINESTATE | 7:6 | USB Line State Status
|
| SPEED | 3:2 | Speed Status
|
FSMSTATUSFinite State Machine Status
- Address
0x4100A00D- Reset
0x01- Access
- read only
- 7–
- 6FSMSTATE6
- 5FSMSTATE5
- 4FSMSTATE4
- 3FSMSTATE3
- 2FSMSTATE2
- 1FSMSTATE1
- 0FSMSTATE0
1 field
| Field | Bits | What it does |
|---|---|---|
| FSMSTATE | 6:0 | Fine State Machine Status
|
DEVICE.FNUMDEVICE Device Frame Number
- Address
0x4100A010- Reset
0x0000- Access
- read/write
- Size
- 16-bit
2 fields
| Field | Bits | What it does |
|---|---|---|
| FNCERR | 15 | Frame Number CRC Error |
| FNUM | 13:3 | Frame Number |
HOST.FNUMHOST Host Frame Number
- Address
0x4100A010- Reset
0x0000- Access
- read/write
- Size
- 16-bit
1 field
| Field | Bits | What it does |
|---|---|---|
| FNUM | 13:3 | Frame Number |
HOST.FLENHIGHHOST Host Frame Length
- Address
0x4100A012- Reset
0x00- Access
- read only
- 7FLENHIGH7
- 6FLENHIGH6
- 5FLENHIGH5
- 4FLENHIGH4
- 3FLENHIGH3
- 2FLENHIGH2
- 1FLENHIGH1
- 0FLENHIGH0
1 field
| Field | Bits | What it does |
|---|---|---|
| FLENHIGH | 7:0 | Frame Length |
DEVICE.INTENCLRDEVICE Device Interrupt Enable Clear
- Address
0x4100A014- Reset
0x0000- Access
- read/write
- Size
- 16-bit
9 fields
| Field | Bits | What it does |
|---|---|---|
| LPMSUSP | 9 | Link Power Management Suspend Interrupt Enable |
| LPMNYET | 8 | Link Power Management Not Yet Interrupt Enable |
| RAMACER | 7 | Ram Access Interrupt Enable |
| UPRSM | 6 | Upstream Resume Interrupt Enable |
| EORSM | 5 | End Of Resume Interrupt Enable |
| WAKEUP | 4 | Wake Up Interrupt Enable |
| EORST | 3 | End of Reset Interrupt Enable |
| SOF | 2 | Start Of Frame Interrupt Enable |
| SUSPEND | 0 | Suspend Interrupt Enable |
HOST.INTENCLRHOST Host Interrupt Enable Clear
- Address
0x4100A014- Reset
0x0000- Access
- read/write
- Size
- 16-bit
8 fields
| Field | Bits | What it does |
|---|---|---|
| DDISC | 9 | Device Disconnection Interrupt Disable |
| DCONN | 8 | Device Connection Interrupt Disable |
| RAMACER | 7 | Ram Access Interrupt Disable |
| UPRSM | 6 | Upstream Resume from Device Interrupt Disable |
| DNRSM | 5 | DownStream to Device Interrupt Disable |
| WAKEUP | 4 | Wake Up Interrupt Disable |
| RST | 3 | BUS Reset Interrupt Disable |
| HSOF | 2 | Host Start Of Frame Interrupt Disable |
DEVICE.INTENSETDEVICE Device Interrupt Enable Set
- Address
0x4100A018- Reset
0x0000- Access
- read/write
- Size
- 16-bit
9 fields
| Field | Bits | What it does |
|---|---|---|
| LPMSUSP | 9 | Link Power Management Suspend Interrupt Enable |
| LPMNYET | 8 | Link Power Management Not Yet Interrupt Enable |
| RAMACER | 7 | Ram Access Interrupt Enable |
| UPRSM | 6 | Upstream Resume Interrupt Enable |
| EORSM | 5 | End Of Resume Interrupt Enable |
| WAKEUP | 4 | Wake Up Interrupt Enable |
| EORST | 3 | End of Reset Interrupt Enable |
| SOF | 2 | Start Of Frame Interrupt Enable |
| SUSPEND | 0 | Suspend Interrupt Enable |
HOST.INTENSETHOST Host Interrupt Enable Set
- Address
0x4100A018- Reset
0x0000- Access
- read/write
- Size
- 16-bit
8 fields
| Field | Bits | What it does |
|---|---|---|
| DDISC | 9 | Device Disconnection Interrupt Enable |
| DCONN | 8 | Link Power Management Interrupt Enable |
| RAMACER | 7 | Ram Access Interrupt Enable |
| UPRSM | 6 | Upstream Resume fromthe device Interrupt Enable |
| DNRSM | 5 | DownStream to the Device Interrupt Enable |
| WAKEUP | 4 | Wake Up Interrupt Enable |
| RST | 3 | Bus Reset Interrupt Enable |
| HSOF | 2 | Host Start Of Frame Interrupt Enable |
DEVICE.INTFLAGDEVICE Device Interrupt Flag
- Address
0x4100A01C- Reset
0x0000- Access
- read/write
- Size
- 16-bit
9 fields
| Field | Bits | What it does |
|---|---|---|
| LPMSUSP | 9 | Link Power Management Suspend |
| LPMNYET | 8 | Link Power Management Not Yet |
| RAMACER | 7 | Ram Access |
| UPRSM | 6 | Upstream Resume |
| EORSM | 5 | End Of Resume |
| WAKEUP | 4 | Wake Up |
| EORST | 3 | End of Reset |
| SOF | 2 | Start Of Frame |
| SUSPEND | 0 | Suspend |
HOST.INTFLAGHOST Host Interrupt Flag
- Address
0x4100A01C- Reset
0x0000- Access
- read/write
- Size
- 16-bit
8 fields
| Field | Bits | What it does |
|---|---|---|
| DDISC | 9 | Device Disconnection |
| DCONN | 8 | Device Connection |
| RAMACER | 7 | Ram Access |
| UPRSM | 6 | Upstream Resume from the Device |
| DNRSM | 5 | Downstream |
| WAKEUP | 4 | Wake Up |
| RST | 3 | Bus Reset |
| HSOF | 2 | Host Start Of Frame |
DEVICE.EPINTSMRYDEVICE End Point Interrupt Summary
- Address
0x4100A020- Reset
0x0000- Access
- read only
- Size
- 16-bit
8 fields
| Field | Bits | What it does |
|---|---|---|
| EPINT7 | 7 | End Point 7 Interrupt |
| EPINT6 | 6 | End Point 6 Interrupt |
| EPINT5 | 5 | End Point 5 Interrupt |
| EPINT4 | 4 | End Point 4 Interrupt |
| EPINT3 | 3 | End Point 3 Interrupt |
| EPINT2 | 2 | End Point 2 Interrupt |
| EPINT1 | 1 | End Point 1 Interrupt |
| EPINT0 | 0 | End Point 0 Interrupt |
HOST.PINTSMRYHOST Pipe Interrupt Summary
- Address
0x4100A020- Reset
0x0000- Access
- read only
- Size
- 16-bit
8 fields
| Field | Bits | What it does |
|---|---|---|
| PINT7 | 7 | Pipe 7 Interrupt |
| PINT6 | 6 | Pipe 6 Interrupt |
| PINT5 | 5 | Pipe 5 Interrupt |
| PINT4 | 4 | Pipe 4 Interrupt |
| PINT3 | 3 | Pipe 3 Interrupt |
| PINT2 | 2 | Pipe 2 Interrupt |
| PINT1 | 1 | Pipe 1 Interrupt |
| PINT0 | 0 | Pipe 0 Interrupt |
DESCADDDescriptor Address
- Address
0x4100A024- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
1 field
| Field | Bits | What it does |
|---|---|---|
| DESCADD | 31:0 | Descriptor Address Value |
PADCALUSB PAD Calibration
- Address
0x4100A028- Reset
0x0000- Access
- read/write
- Size
- 16-bit
3 fields
| Field | Bits | What it does |
|---|---|---|
| TRIM | 14:12 | USB Pad Trim calibration |
| TRANSN | 10:6 | USB Pad Transn calibration |
| TRANSP | 4:0 | USB Pad Transp calibration |
DEVICE_ENDPOINT0.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A100- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE0.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A100- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE0.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A103- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT0.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A104- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE0.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A104- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT0.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A105- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE0.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A105- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT0.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A106- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE0.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A106- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT0.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A107- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE0.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A107- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT0.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A108- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE0.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A108- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT0.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A109- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE0.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A109- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT1.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A120- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE1.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A120- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE1.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A123- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT1.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A124- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE1.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A124- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT1.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A125- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE1.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A125- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT1.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A126- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE1.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A126- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT1.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A127- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE1.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A127- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT1.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A128- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE1.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A128- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT1.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A129- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE1.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A129- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT2.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A140- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE2.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A140- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE2.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A143- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT2.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A144- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE2.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A144- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT2.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A145- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE2.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A145- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT2.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A146- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE2.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A146- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT2.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A147- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE2.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A147- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT2.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A148- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE2.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A148- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT2.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A149- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE2.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A149- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT3.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A160- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE3.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A160- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE3.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A163- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT3.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A164- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE3.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A164- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT3.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A165- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE3.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A165- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT3.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A166- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE3.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A166- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT3.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A167- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE3.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A167- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT3.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A168- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE3.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A168- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT3.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A169- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE3.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A169- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT4.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A180- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE4.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A180- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE4.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A183- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT4.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A184- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE4.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A184- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT4.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A185- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE4.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A185- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT4.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A186- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE4.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A186- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT4.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A187- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE4.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A187- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT4.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A188- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE4.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A188- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT4.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A189- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE4.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A189- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT5.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A1A0- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE5.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A1A0- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE5.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A1A3- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT5.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A1A4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE5.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A1A4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT5.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A1A5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE5.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A1A5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT5.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A1A6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE5.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A1A6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT5.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A1A7- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE5.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A1A7- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT5.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A1A8- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE5.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A1A8- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT5.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A1A9- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE5.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A1A9- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT6.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A1C0- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE6.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A1C0- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE6.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A1C3- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT6.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A1C4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE6.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A1C4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT6.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A1C5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE6.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A1C5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT6.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A1C6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE6.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A1C6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT6.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A1C7- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE6.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A1C7- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT6.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A1C8- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE6.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A1C8- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT6.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A1C9- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE6.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A1C9- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
DEVICE_ENDPOINT7.EPCFGDEVICE_ENDPOINT End Point Configuration
- Address
0x4100A1E0- Reset
0x00- Access
- read/write
- 7–
- 6EPTYPE12
- 5EPTYPE11
- 4EPTYPE10
- 3–
- 2EPTYPE02
- 1EPTYPE01
- 0EPTYPE00
2 fields
| Field | Bits | What it does |
|---|---|---|
| EPTYPE1 | 6:4 | End Point Type1 |
| EPTYPE0 | 2:0 | End Point Type0 |
HOST_PIPE7.PCFGHOST_PIPE End Point Configuration
- Address
0x4100A1E0- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5PTYPE2
- 4PTYPE1
- 3PTYPE0
- 2BK
- 1PTOKEN1
- 0PTOKEN0
3 fields
| Field | Bits | What it does |
|---|---|---|
| PTYPE | 5:3 | Pipe Type |
| BK | 2 | Pipe Bank |
| PTOKEN | 1:0 | Pipe Token |
HOST_PIPE7.BINTERVALHOST_PIPE Bus Access Period of Pipe
- Address
0x4100A1E3- Reset
0x00- Access
- read/write
- 7BINTERVAL7
- 6BINTERVAL6
- 5BINTERVAL5
- 4BINTERVAL4
- 3BINTERVAL3
- 2BINTERVAL2
- 1BINTERVAL1
- 0BINTERVAL0
1 field
| Field | Bits | What it does |
|---|---|---|
| BINTERVAL | 7:0 | Bit Interval |
DEVICE_ENDPOINT7.EPSTATUSCLRDEVICE_ENDPOINT End Point Pipe Status Clear
- Address
0x4100A1E4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| STALLRQ1 | 5 | Stall 1 Request Clear |
| STALLRQ0 | 4 | Stall 0 Request Clear |
| CURBK | 2 | Current Bank Clear |
| DTGLIN | 1 | Data Toggle IN Clear |
| DTGLOUT | 0 | Data Toggle OUT Clear |
HOST_PIPE7.PSTATUSCLRHOST_PIPE End Point Pipe Status Clear
- Address
0x4100A1E4- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Clear |
| BK0RDY | 6 | Bank 0 Ready Clear |
| PFREEZE | 4 | Pipe Freeze Clear |
| CURBK | 2 | Curren Bank clear |
| DTGL | 0 | Data Toggle clear |
DEVICE_ENDPOINT7.EPSTATUSSETDEVICE_ENDPOINT End Point Pipe Status Set
- Address
0x4100A1E5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| STALLRQ1 | 5 | Stall 1 Request Set |
| STALLRQ0 | 4 | Stall 0 Request Set |
| CURBK | 2 | Current Bank Set |
| DTGLIN | 1 | Data Toggle IN Set |
| DTGLOUT | 0 | Data Toggle OUT Set |
HOST_PIPE7.PSTATUSSETHOST_PIPE End Point Pipe Status Set
- Address
0x4100A1E5- Reset
0x00- Access
- write only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 Ready Set |
| BK0RDY | 6 | Bank 0 Ready Set |
| PFREEZE | 4 | Pipe Freeze Set |
| CURBK | 2 | Current Bank Set |
| DTGL | 0 | Data Toggle Set |
DEVICE_ENDPOINT7.EPSTATUSDEVICE_ENDPOINT End Point Pipe Status
- Address
0x4100A1E6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5STALLRQ1
- 4STALLRQ0
- 3–
- 2CURBK
- 1DTGLIN
- 0DTGLOUT
7 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| STALLRQ1 | 5 | Stall 1 Request |
| STALLRQ0 | 4 | Stall 0 Request |
| CURBK | 2 | Current Bank |
| DTGLIN | 1 | Data Toggle In |
| DTGLOUT | 0 | Data Toggle Out |
HOST_PIPE7.PSTATUSHOST_PIPE End Point Pipe Status
- Address
0x4100A1E6- Reset
0x00- Access
- read only
- 7BK1RDY
- 6BK0RDY
- 5–
- 4PFREEZE
- 3–
- 2CURBK
- 1–
- 0DTGL
5 fields
| Field | Bits | What it does |
|---|---|---|
| BK1RDY | 7 | Bank 1 ready |
| BK0RDY | 6 | Bank 0 ready |
| PFREEZE | 4 | Pipe Freeze |
| CURBK | 2 | Current Bank |
| DTGL | 0 | Data Toggle |
DEVICE_ENDPOINT7.EPINTFLAGDEVICE_ENDPOINT End Point Interrupt Flag
- Address
0x4100A1E7- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out |
| STALL0 | 5 | Stall 0 In/out |
| RXSTP | 4 | Received Setup |
| TRFAIL1 | 3 | Error Flow 1 |
| TRFAIL0 | 2 | Error Flow 0 |
| TRCPT1 | 1 | Transfer Complete 1 |
| TRCPT0 | 0 | Transfer Complete 0 |
HOST_PIPE7.PINTFLAGHOST_PIPE Pipe Interrupt Flag
- Address
0x4100A1E7- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Flag |
| TXSTP | 4 | Transmit Setup Interrupt Flag |
| PERR | 3 | Pipe Error Interrupt Flag |
| TRFAIL | 2 | Error Flow Interrupt Flag |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Flag |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Flag |
DEVICE_ENDPOINT7.EPINTENCLRDEVICE_ENDPOINT End Point Interrupt Clear Flag
- Address
0x4100A1E8- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/Out Interrupt Disable |
| STALL0 | 5 | Stall 0 In/Out Interrupt Disable |
| RXSTP | 4 | Received Setup Interrupt Disable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Disable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Disable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Disable |
HOST_PIPE7.PINTENCLRHOST_PIPE Pipe Interrupt Flag Clear
- Address
0x4100A1E8- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Inetrrupt Disable |
| TXSTP | 4 | Transmit Setup Interrupt Disable |
| PERR | 3 | Pipe Error Interrupt Disable |
| TRFAIL | 2 | Error Flow Interrupt Disable |
| TRCPT1 | 1 | Transfer Complete 1 Disable |
| TRCPT0 | 0 | Transfer Complete 0 Disable |
DEVICE_ENDPOINT7.EPINTENSETDEVICE_ENDPOINT End Point Interrupt Set Flag
- Address
0x4100A1E9- Reset
0x00- Access
- read/write
- 7–
- 6STALL1
- 5STALL0
- 4RXSTP
- 3TRFAIL1
- 2TRFAIL0
- 1TRCPT1
- 0TRCPT0
7 fields
| Field | Bits | What it does |
|---|---|---|
| STALL1 | 6 | Stall 1 In/out Interrupt enable |
| STALL0 | 5 | Stall 0 In/out Interrupt enable |
| RXSTP | 4 | Received Setup Interrupt Enable |
| TRFAIL1 | 3 | Error Flow 1 Interrupt Enable |
| TRFAIL0 | 2 | Error Flow 0 Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |
HOST_PIPE7.PINTENSETHOST_PIPE Pipe Interrupt Flag Set
- Address
0x4100A1E9- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5STALL
- 4TXSTP
- 3PERR
- 2TRFAIL
- 1TRCPT1
- 0TRCPT0
6 fields
| Field | Bits | What it does |
|---|---|---|
| STALL | 5 | Stall Interrupt Enable |
| TXSTP | 4 | Transmit Setup Interrupt Enable |
| PERR | 3 | Pipe Error Interrupt Enable |
| TRFAIL | 2 | Error Flow Interrupt Enable |
| TRCPT1 | 1 | Transfer Complete 1 Interrupt Enable |
| TRCPT0 | 0 | Transfer Complete 0 Interrupt Enable |