BETAPIC32CM3204PL10028 interrupt vectors
The vector table at the start of flash (VTOR moves it): word 0 is the initial stack pointer, then the 6 core exceptions (numbered below 0 as CMSIS does) and the 15 peripheral interrupts, IRQ 0 up. Each entry is the 4-byte address of its handler, at 4 × (IRQn + 16). The NVIC enables each IRQ and sets its priority; in C a handler is a function with the name below, e.g. void SERCOM0_Handler(void), and NVIC_EnableIRQ(SERCOM0_IRQn) turns it on.
| IRQn | Table offset | Name | Handler | Source |
|---|---|---|---|---|
| – | 0x0000 | Initial SP | the stack's top: _estack | Loaded into SP at reset, before Reset_Handler runs |
| -15 | 0x0004 | Reset | Reset_Handler | Reset Vector, invoked on Power up and warm reset |
| -14 | 0x0008 | NonMaskableInt | NonMaskableInt_Handler | Non maskable Interrupt, cannot be stopped or preempted |
| -13 | 0x000C | HardFault | HardFault_Handler | Hard Fault, all classes of Fault |
| -5 | 0x002C | SVCall | SVCall_Handler | System Service Call via SVC instruction |
| -2 | 0x0038 | PendSV | PendSV_Handler | Pendable request for system service |
| -1 | 0x003C | SysTick | SysTick_Handler | System Tick Timer |
| 0 | 0x0040 | SYSTEM | SYSTEM_Handler · SYSTEM_IRQn | |
| 1 | 0x0044 | WDT | WDT_Handler · WDT_IRQn | |
| 2 | 0x0048 | RTC | RTC_Handler · RTC_IRQn | |
| 3 | 0x004C | EIC | EIC_Handler · EIC_IRQn | |
| 4 | 0x0050 | NVMCTRL | NVMCTRL_Handler · NVMCTRL_IRQn | |
| 5 | 0x0054 | DMAC | DMAC_Handler · DMAC_IRQn | |
| 6 | 0x0058 | EVSYS | EVSYS_Handler · EVSYS_IRQn | |
| 7 | 0x005C | SERCOM0 | SERCOM0_Handler · SERCOM0_IRQn | |
| 8 | 0x0060 | SERCOM1 | SERCOM1_Handler · SERCOM1_IRQn | |
| 9 | 0x0064 | TC0 | TC0_Handler · TC0_IRQn | |
| 10 | 0x0068 | TC1 | TC1_Handler · TC1_IRQn | |
| 11 | 0x006C | TC2 | TC2_Handler · TC2_IRQn | |
| 12 | 0x0070 | TCC0 | TCC0_Handler · TCC0_IRQn | |
| 13 | 0x0074 | ADC0 | ADC0_Handler · ADC0_IRQn | |
| 14 | 0x0078 | AC | AC_Handler · AC_IRQn |