PIC32CM5112GC00064 memory map

Where everything sits, at its exact address. The PIC32CM5112GC00064 has one 32-bit address space that its Arm Cortex-M23 core reaches flash, SRAM and the peripherals through alike: flash at 0x0C000000, SRAM at 0x20000000, the peripherals from 0x40000000 and the core's own system registers (SysTick, the NVIC) at 0xE000E000.

Memory map

Flash, SRAM and the peripheral buses in the one 32-bit space (the calibration and user rows are listed below).

Private peripheral bus0xE0000000 – 0xE00FFFFF1 MB
APB2 BRIDGE0x45000000 – 0x4500FFFF64 KB
APB1 BRIDGE0x44800000 – 0x44839FFF232 KB
APB0 BRIDGE0x44000000 – 0x44033FFF208 KB
SRAM0x20000000 – 0x2001FFFF128 KB
FCR PFM0x0C000000 – 0x0C07FFFF512 KB
FCR CFM TEST0x0A006000 – 0x0A006FFF4 KB
FCR CFM VSS10x0A005000 – 0x0A005FFF4 KB
FCR CFM VSS00x0A004000 – 0x0A004FFF4 KB
FCR CFM ROMCFG0x0A003000 – 0x0A003FFF4 KB
FCR CFM BOOTCFG10x0A002000 – 0x0A002FFF4 KB
FCR CFM BOOTCFG1A0x0A000000 – 0x0A000FFF4 KB
FCR BFM0x08000000 – 0x08003FFF16 KB

Every segment

SegmentSpaceStartEndSizePage
Private peripheral busbase0xE00000000xE00FFFFF1 MB
BROMC ROMbase0x040000000x0400FFFF64 KB
FCR BFMbase0x080000000x08003FFF16 KB
FCR CFM BOOTCFG1Abase0x0A0000000x0A000FFF4 KB
FCR CFM USEROTPbase0x0A0010000x0A001FFF4 KB
FCR CFM BOOTCFG1base0x0A0020000x0A002FFF4 KB
FCR CFM ROMCFGbase0x0A0030000x0A003FFF4 KB
FCR CFM VSS0base0x0A0040000x0A004FFF4 KB
FCR CFM VSS1base0x0A0050000x0A005FFF4 KB
FCR CFM TESTbase0x0A0060000x0A006FFF4 KB
FCR CFM CALOTPbase0x0A0070000x0A007FFF4 KB
FCR PFMbase0x0C0000000x0C07FFFF512 KB
SRAMbase0x200000000x2001FFFF128 KB
APB0 BRIDGEbase0x440000000x44033FFF208 KB
APB1 BRIDGEbase0x448000000x44839FFF232 KB
APB2 BRIDGEbase0x450000000x4500FFFF64 KB