The 2 registers of BROMC (ARM GF55LPx Boot ROM Controller Macro), from 0x44804000, with their reset value and every field. The PIC32CM5112GC00064 has 2253 registers in 57 peripherals, one page each.
BROMC ARM GF55LPx Boot ROM Controller Macro
CTRLAControl A REGISTER
Address
0x44804000
Reset
0x00000002
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
PRMWS
10:8
ROM Access Time Wait State
0 No wait states, single cycle access
1 Access time extended 2 clock cycles
2 Access time extended to 3 clock cycles
7 Access time extended to 8 clock cycles
PRIV
2
Privileged Access Only
0 Macro register accessible in privileged and unprivileged modes
1 Macro registers only accessible in privileged mode
ENABLE
1
Enable bit
0 Disable ROM read access and power down the ROM. The ROM PGEN input is driven high. The ROM will clamp outputs to 1 and disable all internal current sinks. Refer to the ROM compiler specification for details on powering down the ROM.
1 Enable ROM read access, power up the ROM. The ROM PGEN input is driven low.
SWRST
0
Software Reset bit
UCFGUser Configuration REGISTER
Address
0x44804004
Reset
0x00000001
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
BCRCDIS
0
Boot CRC Disable
0 Boot ROM content is CRC verified by the ROM controller, status is reported to the DSU. On CRC failure, the controller blocks access to the ROM controller.
BETA