PIC32CM5164JH01048 memory map

Where everything sits, at its exact address. The PIC32CM5164JH01048 has one 32-bit address space that its Arm Cortex-M0+ core reaches flash, SRAM and the peripherals through alike: flash at 0x00000000, SRAM at 0x20000000, the peripherals from 0x40000000 and the core's own system registers (SysTick, the NVIC) at 0xE000E000.

Memory map

Flash, SRAM and the peripheral buses in the one 32-bit space (the calibration and user rows are listed below).

Private peripheral bus0xE0000000 – 0xE00FFFFF1 MB
DIVAS0x48000000 – 0x4800001F32 B
Peripheral bridge D (HPB3)0x43000000 – 0x430017FF6 KB
Peripheral bridge C (HPB2)0x42000000 – 0x42007FFF32 KB
Peripheral bridge B (HPB1)0x41000000 – 0x4100FFFF64 KB
Peripheral bridge A (HPB0)0x40000000 – 0x40003FFF16 KB
SRAM0x20000000 – 0x2000FFFF64 KB
DATAFLASH0x00400000 – 0x00401FFF8 KB
Flash0x00000000 – 0x0007FFFF512 KB

Every segment

SegmentSpaceStartEndSizePage
Private peripheral busbase0xE00000000xE00FFFFF1 MB
Flashbase0x000000000x0007FFFF512 KB64 B
DATAFLASHbase0x004000000x00401FFF8 KB64 B
CALbase0x008000000x008000078 B
LOCKBITbase0x008020000x008020034 B
USER PAGEbase0x008040000x008040FF256 B64 B
OTP1base0x008060000x008060078 B
OTP2base0x008060080x0080600F8 B
OTP3base0x008060100x008060178 B
OTP4base0x008060180x0080601F8 B
OTP5base0x008060200x008060278 B
TEMP LOGbase0x008060300x008060378 B
SRAMbase0x200000000x2000FFFF64 KB
Peripheral bridge A (HPB0)base0x400000000x40003FFF16 KB
Peripheral bridge B (HPB1)base0x410000000x4100FFFF64 KB
Peripheral bridge C (HPB2)base0x420000000x42007FFF32 KB
Peripheral bridge D (HPB3)base0x430000000x430017FF6 KB
DIVASbase0x480000000x4800001F32 B