The 1 register of CMP5 (Comparator 5), from 0xBF82C090, with their reset value and every field. The PIC32MK1024GPK100 has 1208 registers in 107 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CMP5 Comparator 5
CM5CONOp amp/Comparator x Control Register
Address
0xBF82C090
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ENPGA
30
Opamp Fixed Gain Enable bit
0 Op amp is operating in Open Loop mode (default)
1 Op amp is operating in Fixed Gain 1X mode
HYSPOL
28
Comparator Hysteresis Polarity Selection
0 Hysteresis on rising edge, falling edge is accurate
1 Hysteresis on falling edge, rising edge is accurate
HYSSEL
25:24
Hysteresis Selection bits
0 No hysteresis selected.
1 Set lowest hysteresis level (Typical 15 mV)
2 Set medium hysteresis level (Typical 30 mV)
3 Set highest hysteresis level (Typical 45 mV)
CFSEL
22:20
Comparator Output Filter Clock Source Select bits
0 SYSCLK Clock
1 PPBCLK2 Clock
2 PWM Secondary Special Event
3 REFCLK3 Clock
4 PBCLK2/Timer2 Period Value (PR2)
5 PBCLK2/Timer3 Period Value (PR3)
6 PBCLK2/Timer4 Period Value (PR4)
7 PBCLK2/Timer5 Period Value (PR5)
CFLTREN
19
Comparator Output Digital Filter Enable bit
0 Digital Filters disabled
1 Digital Filters enabled
CFDIV
18:16
Comparator Output Filter Clock Divide Select bits
0 1:1 Clock Divide
1 1:2 Clock Divide
2 1:4 Clock Divide
3 1:8 Clock Divide
4 1:16 Clock Divide
5 1:32 Clock Divide
6 1:64 Clock Divide
7 1:128 Clock Divide
ON
15
Comparator Enable bit
0 Comparator is disabled
1 Comparator is enabled
COE
14
Comparator Output Enable bit
0 Comparator output is internal only
1 Comparator output is present on the CxOUT pin
CPOL
13
Comparator Output Polarity Select bit
0 Comparator output is not inverted
1 Comparator output is inverted
OPLPWR
12
Opamp Low-Power Mode Select bit
0 Comparator does not operate in Low-Power mode
1 Comparator operates in Low-Power mode
CEVT
9
Comparator Event bit
0 Comparator event did not occur
1 Comparator event according to EVPOL bit settings occurred
COUT
8
Comparator Output bit
0 (When CPOL is 0) VIN+ VTH-
1 (When CPOL is 0) VIN+ > VTH+ / (When CPOL is 1) VIN+ VTH+ / (When CPOL is 1) VIN+ < VTH-
EVPOL
7:6
Trigger/Event Polarity Select bits
0 Trigger/Event generation is disabled
1 (When CPOL is 0) Trigger/Event generated only on low-to-high transition of the polarity-selected comparator output / (When CPOL is 1) Trigger/Event generated only on high-to-low transition of the polarity-selected comparator output
2 (When CPOL is 0) Trigger/Event generated only on high-to-low transition of the polarity-selected comparator output / (When CPOL is 1) Trigger/Event generated only on low-to-high transition of the polarity-selected comparator output
3 Trigger/Event generated on any change of the comparator output
CREF
4
Op amp/Comparator Reference Select bit
0 VIN+ input connects to CxIN1+ pin
1 VIN+ input connects to internal CDAC3 output voltage
CCH
1:0
Comparator Channel Select bits
0 CxIN1-
1 CxIN2-
2 CxIN3-
3 CxIN4-
OPAON
31
Opamp Enable Bit
0 Op amp disabled and pin is released to other functions
BETA