PIC32MK1024MCF064 PCACHE registers The 3 registers of PCACHE (Prefetch cache), from 0xBF800800, with their reset value and every field. The PIC32MK1024MCF064 has 1848 registers in 120 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PCACHE Prefetch cache CHECONCache Module Control Register
Address 0xBF800800
Reset 0x07000107
Access read/write
Size 32-bit 13 fields
Field Bits What it does PERCHEEN 26 Peripheral Cache Enable bit0 Peripheral cache is disabled1 Peripheral cache is enabled DCHEEN 25 Data Cache Enable bit0 Data cache is disabled1 Data cache is enabled ICHEEN 24 Instruction Cache Enable bit0 Instruction cache is disabled1 Instruction cache is enabled PERCHEINV 22 Peripheral Cache Invalidate bit0 Cache Invalidation follows CHECOH/invalid complete1 Force invalidate cache/invalidate busy DCHEINV 21 Data Cache Invalidate bit0 Cache Invalidation follows CHECOH/invalid complete1 Force invalidate cache/invalidate busy ICHEINV 20 Instruction Cache Invalidate bit0 Cache Invalidation follows CHECOH/invalid complete1 Force invalidate cache/invalidate busy PERCHECOH 18 Peripheral Auto-cache Coherency Control bit0 Do not automatically invalidate cache on a programming event1 Automatically invalidate cache on a programming event DCHECOH 17 Data Auto-cache Coherency Control bit0 Do not automatically invalidate cache on a programming event1 Automatically invalidate cache on a programming event ICHECOH 16 Instruction Auto-cache Coherency Control bit0 Do not automatically invalidate cache on a programming event1 Automatically invalidate cache on a programming event CHEPERFEN 12 Cache Performance Counters Enable bit0 Performance counters are disabled1 Performance counters are enabled PFMAWSEN 8 PFM Address Wait State Enable bit0 Add no Wait States to the flash address setup (suggested for lower system clock frequencies to achieve higher performance)1 Add one more Wait State to flash address setup (suggested for higher system clock frequencies) PREFEN 5:4 Predictive Prefetch Enable bits0 Disable predictive prefetch1 Enable predictive prefetch for CPU instructions only2 Disable predictive prefetch3 Disable predictive prefetch PFMWS 2:0 PFM Access Time Defined in Terms of SYSCLK Wait States bits0 Zero Wait states1 One Wait state2 Two Wait states7 Seven Wait states
CHEHITCACHE Hit Status Register
Address 0xBF800820
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CHEHIT 31:0
CHEMISCACHE Miss Status Register
Address 0xBF800830
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CHEMIS 31:0
BETA