PIC32MK1024MCM064 ADC registers

The 92 registers of ADC (Analog-to-digital converter), from 0xBF887000, with their reset value and every field. The PIC32MK1024MCM064 has 2203 registers in 115 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

ADC Analog-to-digital converter

ADCCON1ADC Control Register 1

Address: 0xBF887000
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
TRBERR	30	Turbo Channel Error Status bit `0` Turbo channel error did not occur `1` An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless of the TRBEN bit being set to 1
TRBMST	29:27	Turbo Master ADCx bits `0` ADC0 `1` ADC1 `2` ADC2 `3` ADC3 `4` ADC4 `5` ADC5
TRBSLV	26:24	Turbo Slave ADCx bits `0` ADC0 `1` ADC1 `2` ADC2 `3` ADC3 `4` ADC4 `5` ADC5
FRACT	23	Fractional Data Output Format bit `0` Integer `1` Fractional
SELRES	22:21	Shared ADC7 Resolution bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits (default)
STRGSRC	20:16	Scan Trigger Source Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 period end `17` Output Compare 2 period end `18` Output Compare 3 period end `19` Output Compare 4 period end `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor Control only) `29` PWM Generator 11 trigger (Motor Control only) `30` PWM Generator 12 trigger (Motor Control only)
ON	15	ADC Module Enable bit `0` ADC module is disabled `1` ADC module is enabled
SIDL	13	Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
AICPMPEN	12	Analog Input Charge Pump Enable bit `0` Analog input charge pump is disabled (default) `1` Analog input charge pump is enabled
CVDEN	11	Capacitive Voltage Division Enable bit `0` CVD operation is disabled `1` CVD operation is enabled
FSSCLKEN	10	Fast Synchronous System Clock to ADC Control Clock bit `0` Fast synchronous system clock to ADC control clock is disabled `1` Fast synchronous system clock to ADC control clock is enabled
FSPBCLKEN	9	Fast Synchronous Peripheral Clock to ADC Control Clock bit `0` Fast synchronous peripheral clock to ADC control clock is disabled `1` Fast synchronous peripheral clock to ADC control clock is enabled
IRQVS	6:4	Interrupt Vector Shift bits `0` Shift x left 0 bit position `1` Shift x left 1 bit position `2` Shift x left 2 bit position `3` Shift x left 3 bit position `4` Shift x left 4 bit position `5` Shift x left 5 bit position `6` Shift x left 6 bit position `7` Shift x left 7 bit position
STRGLVL	3	Scan Trigger High Level/Positive Edge Sensitivity bit `0` Scan trigger is positive edge sensitive. Once STRIG mode is selected only a single scan trigger will be generated which will complete the scan of all selected analog inputs. (TRGSRCx in the ADCTRGx register) `1` Scan trigger is high level sensitive. Once STRIG mode is selected the scan trigger will continue for all selected analog inputs
DMABL	2:0	DMA to System RAM Buffer Length Size bits `0` Allocates 1 location in system memory to each analog input `1` Allocates 2 locations in system memory to each analog input `2` Allocates 4 locations in system memory to each analog input `3` Allocates 8 locations in system memory to each analog input `4` Allocates 16 locations in system memory to each analog input `5` Allocates 32 locations in system memory to each analog input `6` Allocates 64 locations in system memory to each analog input `7` Allocates 128 locations in system memory to each analog input
TRBEN	31	Turbo Channel Enable bit `0` Disable the Turbo channel `1` Enable the Turbo channel

ADCCON2ADC Control Register 2

Address: 0xBF887010
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
REFFLT	30	Band Gap/ Vref / AVdd BOR Fault Status bit `0` Band gap and Vref voltage are working properly `1` Fault in band gap or the Vref voltage while the ON bit (ADCCON1) was set. Most likely a band gap or Vref fault will be caused by a BOR of the analog Vdd supply.
EOSRDY	29	End of Scan Interrupt Status bit `0` Scanning has not completed `1` All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS2 registers) have completed scanning
CVDCPL	28:26	Capacitor Voltage Divider Setting bits `0` 0 * 2.5 pF = 0 pF `1` 1 * 2.5 pF = 2.5 pF `2` 2 * 2.5 pF = 5 pF `3` 3 * 2.5 pF = 7.5 pF `4` 4 * 2.5 pF = 10 pF `5` 5 * 2.5 pF = 12.5 pF `6` 6 * 2.5 pF = 15 pF `7` 7 * 2.5 pF = 17.5 pF
SAMC	25:16	Sample Time for the Shared ADC (ADC7) bits `0` 2 Tad `1` 3 Tad `1023` 1025 Tad
BGVRIEN	15	Band Gap/ Vref Voltage Ready Interrupt Enable bit `0` No interrupt is generated when the BGVRRDY bit is set `1` Interrupt will be generated when the BGVRDDY bit is set
REFFLTIEN	14	Band Gap/ Vref Voltage Fault Interrupt Enable bit `0` No interrupt is generated when the REFFLT bit is set `1` Interrupt will be generated when the REFFLT bit is set
EOSIEN	13	End of Scan Interrupt Enable bit `0` No interrupt is generated when the EOSRDY bit is set `1` Interrupt will be generated when EOSRDY bit is set
ADCEIOVR	12	Early Interrupt Request Override bit `0` Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1 and ADCEIEN2 registers `1` Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1 and ADCGIRQEN2 registers
ADCEIS	10:8	Shared ADC Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC module clock prior to end of conversion `1` The data ready interrupt is generated 2 ADC module clocks prior to end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to end of conversion
ADCDIV	6:0	Shared ADC Clock Divider bits `0` Reserved `1` 2 * Tq = Tad `2` 4 * Tq = Tad `3` 6 * Tq = Tad `127` 254 * Tq = Tad
BGVRRDY	31	Band Gap Voltage/ADC Reference Voltage Status bit `0` Either or both band gap voltage and ADC reference voltages (Vref) are not ready `1` Both band gap voltage and ADC reference voltages (Vref) are ready

ADCCON3ADC Control Register 3

Address: 0xBF887020
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
CONCLKDIV	29:24	Analog-to-Digital Control Clock Divider bits `0` Tclk = Tq `1` 2 * Tclk = Tq `2` 4 * Tclk = Tq `3` 6 * Tclk = Tq `63` 126 * Tclk = Tq
DIGEN7	23	Shared ADC (ADC7) Digital Enable bit `0` ADC7 is digital disabled `1` ADC7 is digital enabled
DIGEN5	21	ADC5 Digital Enable bit `0` ADC5 is digital disabled (power-saving mode) `1` ADC5 is digital enabled (required for active operation)
DIGEN4	20	ADC4 Digital Enable bit `0` ADC4 is digital disabled (power-saving mode) `1` ADC4 is digital enabled (required for active operation)
DIGEN3	19	ADC3 Digital Enable bit `0` ADC3 is digital disabled (power-saving mode) `1` ADC3 is digital enabled (required for active operation)
DIGEN2	18	ADC2 Digital Enable bit `0` ADC2 is digital disabled (power-saving mode) `1` ADC2 is digital enabled (required for active operation)
DIGEN1	17	ADC1 Digital Enable bit `0` ADC1 is digital disabled (power-saving mode) `1` ADC1 is digital enabled (required for active operation)
DIGEN0	16	ADC0 Digital Enable bit `0` ADC0 is digital disabled (power-saving mode) `1` ADC0 is digital enabled (required for active operation)
VREFSEL	15:13	Voltage Reference Input Selection bits `0` ADC VREFH is AVDD, ADC VREFL is AVSS `1` ADC VREFH is VREF+, ADC VREFL is AVSS `2` ADC VREFH is AVDD, ADC VREFL is VREF- `3` ADC VREFH is VREF+, ADC VREFL is VREF-
TRGSUSP	12	Trigger Suspend bit `0` Triggers are not blocked `1` Triggers are blocked from starting a new analog-to-digital conversion
UPDIEN	11	Update Ready Interrupt Enable bit `0` No interrupt is generated `1` Interrupt will be generated when the UPDRDY bit is set by hardware
UPDRDY	10	ADC Update Ready Status bit `0` ADC SFRs cannot be updated `1` ADC SFRs can be updated
SAMP	9	Shared ADC7 Analog Input Sampling Enable bit `0` The ADC S&H amplifier is holding `1` The ADC S&H amplifier is sampling
RQCNVRT	8	Individual ADC Input Conversion Request bit `0` Do not trigger the conversion `1` Trigger the conversion of the selected ADC input as specified by the ADINSEL bits
GLSWTRG	7	Global Level Software Trigger bit `0` Do not trigger an analog-to-digital conversion `1` Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal
GSWTRG	6	Global Software Trigger bit `0` Do not trigger an analog-to-digital conversion `1` Trigger conversion for ADC inputs that have selected the GSWTRG bit as either through the associated TRGSRC bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register the trigger signal
ADINSEL	5:0	Analog Input Select bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` AN8 `9` AN9 `10` AN10 `11` AN11 `12` AN12 `13` AN13 `14` AN14 `15` AN15 `16` AN16 `17` AN17 `18` AN18 `19` AN19 `20` AN20 `21` AN21 `22` AN22 `23` AN23 `24` AN24 `25` AN25 `26` AN26 `27` AN27 `33` AN33 `34` AN34 `35` AN35 `36` AN36 `37` AN37 `38` AN38 `39` AN39 `40` AN40 `41` AN41 `45` AN45 `46` AN46 `47` AN47 `48` AN48 `49` AN49 `50` IVref 1.2V (internal AN50) `52` VBAT/2 (internal AN52) `53` CTMU Temperature Sensor (internal AN53)
ADCSEL	31:30	Analog-to-Digital Clock Source bits `0` SYSCLK `1` FRC `2` REFCLK3 `3` SYSCLK

ADCTRGMODEADC Triggering Mode for Dedicated ADC Register

Address: 0xBF887030
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
SH5ALT	27:26	ADC5 Analog Input Select bit `0` AN5 `1` AN2 `2` AN6 `3` AN25
SH4ALT	25:24	ADC4 Analog Input Select bit `0` AN4 `1` AN1 `2` AN9 `3` AN0
SH3ALT	23:22	ADC3 Analog Input Select bit `0` AN3 `1` AN0 `2` AN8 `3` AN26
SH2ALT	21:20	ADC2 Analog Input Select bit `0` AN2 `1` AN5 `2` AN6 `3` AN25
SH1ALT	19:18	ADC1 Analog Input Select bit `0` AN1 `1` AN4 `2` AN7 `3` AN0
SH0ALT	17:16	ADC0 Analog Input Select bit `0` AN0 `1` AN3 `2` AN5 `3` AN24
STRGEN5	13	ADC5 Presynchronized Triggers bit `0` ADC5 does not use presynchronized triggers `1` ADC5 uses presynchronized triggers
STRGEN4	12	ADC4 Presynchronized Triggers bit `0` ADC4 does not use presynchronized triggers `1` ADC4 uses presynchronized triggers
STRGEN3	11	ADC3 Presynchronized Triggers bit `0` ADC3 does not use presynchronized triggers `1` ADC3 uses presynchronized triggers
STRGEN2	10	ADC2 Presynchronized Triggers bit `0` ADC2 does not use presynchronized triggers `1` ADC2 uses presynchronized triggers
STRGEN1	9	ADC1 Presynchronized Triggers bit `0` ADC1 does not use presynchronized triggers `1` ADC1 uses presynchronized triggers
STRGEN0	8	ADC0 Presynchronized Triggers bit `0` ADC0 does not use presynchronized triggers `1` ADC0 uses presynchronized triggers
SSAMPEN5	5	ADC5 Synchronous Sampling bit `0` ADC5 does not use synchronous sampling `1` ADC5 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN4	4	ADC4 Synchronous Sampling bit `0` ADC4 does not use synchronous sampling `1` ADC4 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN3	3	ADC3 Synchronous Sampling bit `0` ADC3 does not use synchronous sampling `1` ADC3 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN2	2	ADC2Synchronous Sampling bit `0` ADC2 does not use synchronous sampling `1` ADC2 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN1	1	ADC1 Synchronous Sampling bit `0` ADC1 does not use synchronous sampling `1` ADC1 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN0	0	ADC0 Synchronous Sampling bit `0` ADC0 does not use synchronous sampling `1` ADC0 uses synchronous sampling for the first sample after being idle or disabled

ADCIMCON1ADC Input Mode Control Register 1

Address: 0xBF887040
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
SIGN15	30	NO_SUCH_FIELD `0` AN15 is using Unsigned Data mode `1` AN15 is using Signed Data mode
DIFF14	29	AN14 Mode bit `0` AN14 is using Single-ended mode `1` Selects AN14 differential input pair as AN14+ and AN1-
SIGN14	28	AN14 Signed Data Mode bit `0` AN14 is using Unsigned Data mode `1` AN14 is using Signed Data mode
DIFF13	27	AN13 Mode bit `0` AN13 is using Single-ended mode `1` Selects AN13 differential input pair as AN13+ and AN1-
SIGN13	26	AN13 Signed Data Mode bit `0` AN13 is using Unsigned Data mode `1` AN13 is using Signed Data mode
DIFF12	25	AN12 Mode bit `0` AN12 is using Single-ended mode `1` Selects AN12 differential input pair as AN12+ and AN1-
SIGN12	24	AN12 Signed Data Mode bit `0` AN12 is using Unsigned Data mode `1` AN12 is using Signed Data mode
DIFF11	23	AN11 Mode bit `0` AN11 is using Single-ended mode `1` Selects AN11 differential input pair as AN11+ and AN1-
SIGN11	22	AN11 Signed Data Mode bit `0` AN11 is using Unsigned Data mode `1` AN11 is using Signed Data mode
DIFF10	21	AN10 Mode bit `0` AN10 is using Single-ended mode `1` Selects AN10 differential input pair as AN10+ and AN1-
SIGN10	20	AN10 Signed Data Mode bit `0` AN10 is using Unsigned Data mode `1` AN10 is using Signed Data mode
DIFF9	19	AN9 Mode bit `0` AN9 is using Single-ended mode `1` Selects AN9 differential input pair as AN9+ and AN1-
SIGN9	18	AN9 Signed Data Mode bit `0` AN9 is using Unsigned Data mode `1` AN9 is using Signed Data mode
DIFF8	17	AN 8 Mode bit `0` AN8 is using Single-ended mode `1` Selects AN8 differential input pair as AN8+ and AN1-
SIGN8	16	AN8 Signed Data Mode bit `0` AN8 is using Unsigned Data mode `1` AN8 is using Signed Data mode
DIFF7	15	AN7 Mode bit `0` AN7 is using Single-ended mode `1` Selects AN7 differential input pair as AN7+ and AN1-
SIGN7	14	AN7 Signed Data Mode bit `0` AN7 is using Unsigned Data mode `1` AN7 is using Signed Data mode
DIFF6	13	AN6 Mode bit `0` AN6 is using Single-ended mode `1` Selects AN6 differential input pair as AN6+ and AN1-
SIGN6	12	AN6 Signed Data Mode bit `0` AN6 is using Unsigned Data mode `1` AN6 is using Signed Data mode
DIFF5	11	AN5 Mode bit `0` AN5 is using Single-ended mode `1` Selects AN5 differential input pair as AN5+ and AN11-
SIGN5	10	AN5 Signed Data Mode bit `0` AN5 is using Unsigned Data mode `1` AN5 is using Signed Data mode
DIFF4	9	AN4 Mode bit `0` AN4 is using Single-ended mode `1` Selects AN4 differential input pair as AN4+ and AN10-
SIGN4	8	AN4 Signed Data Mode bit `0` AN4 is using Unsigned Data mode `1` AN4 is using Signed Data mode
DIFF3	7	AN3 Mode bit `0` AN3 is using Single-ended mode `1` Selects AN3 differential input pair as AN3+ and AN27-
SIGN3	6	AN3 Signed Data Mode bit `0` AN3 is using Unsigned Data mode `1` AN3 is using Signed Data mode
DIFF2	5	AN2 Mode bit `0` AN2 is using Single-ended mode `1` Selects AN2 differential input pair as AN2+ and AN8-
SIGN2	4	AN2 Signed Data Mode bit `0` AN2 is using Unsigned Data mode `1` AN2 is using Signed Data mode
DIFF1	3	AN1 Mode bit `0` AN1 is using Single-ended mode `1` Selects AN1 differential input pair as AN1+ and AN7-
SIGN1	2	AN1 Signed Data Mode bit `0` AN1 is using Unsigned Data mode `1` AN1 is using Signed Data mode
DIFF0	1	AN0 Mode bit `0` AN0 is using Single-ended mode `1` Selects AN0 differential input pair as AN0+ and AN6-
SIGN0	0	AN0 Signed Data Mode bit `0` AN0 is using Unsigned Data mode `1` AN0 is using Signed Data mode
DIFF15	31	AN15 Mode bit `0` AN15 is using Single-ended mode `1` Selects AN15 differential input pair as AN15+ and AN1-

ADCIMCON2ADC Input Mode Control Register 2

Address: 0xBF887050
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
DIFF27	23	AN27 Mode bit `0` AN27 is using Single-ended mode `1` Selects AN27 differential pair input as AN27+ and AN1-
SIGN27	22	AN27 Signed Data Mode bit `0` AN27 is using Unsigned Data mode `1` AN27 is using Signed Data mode
DIFF26	21	AN26 Mode bit `0` AN26 is using Single-ended mode `1` Selects AN26 differential pair input as AN26+ and AN1-
SIGN26	20	AN26 Signed Data Mode bit `0` AN26 is using Unsigned Data mode `1` AN26 is using Signed Data mode
DIFF25	19	AN25 Mode bit `0` AN25 is using Single-ended mode `1` Selects AN25 differential pair input as AN25+ and AN1-
SIGN25	18	AN25 Signed Data Mode bit `0` AN25 is using Unsigned Data mode `1` AN25 is using Signed Data mode
DIFF24	17	AN24 Mode bit `0` AN24 is using Single-ended mode `1` Selects AN24 differential pair input as AN24+ and AN1-
SIGN24	16	AN24 Signed Data Mode bit `0` AN24 is using Unsigned Data mode `1` AN24 is using Signed Data mode
DIFF19	7	AN19 Mode bit `0` AN19 is using Single-ended mode `1` Selects AN19 differential pair input as AN19+ and AN1-
SIGN19	6	AN19 Signed Data Mode bit `0` AN19 is using Unsigned Data mode `1` AN19 is using Signed Data mode
DIFF18	5	AN18 Mode bit `0` AN18 is using Single-ended mode `1` Selects AN18 differential pair input as AN18+ and AN1-
SIGN18	4	AN18 Signed Data Mode bit `0` AN18 is using Unsigned Data mode `1` AN18 is using Signed Data mode
DIFF17	3	AN17 Mode bit `0` AN17 is using Single-ended mode `1` Selects AN17 differential pair input as AN17+ and AN1-
SIGN17	2	AN17 Signed Data Mode bit `0` AN17 is using Unsigned Data mode `1` AN17 is using Signed Data mode
DIFF16	1	AN16 Mode bit `0` AN16 is using Single-ended mode `1` Selects AN16 differential pair input as AN16+ and AN1-
SIGN16	0	AN16 Signed Data Mode bit `0` AN16 is using Unsigned Data mode `1` AN16 is using Signed Data mode

ADCIMCON3ADC Input Mode Control Register 3

Address: 0xBF887060
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCIMCON4ADC Input Mode Control Register 4

Address: 0xBF887070
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
DIFF49	3	AN49 Mode bit `0` AN49 is using Single-ended mode `1` Selects AN49 differential input pair as AN49+ and AN1-
SIGN49	2	AN41 Signed Data Mode bit `0` AN49 is using Unsigned Data mode `1` AN49 is using Signed Data mode
DIFF48	1	AN48 Mode bit `0` AN48 is using Single-ended mode `1` Selects AN40 differential input pair as AN48+ and AN1-
SIGN48	0	AN48 Signed Data Mode bit `0` AN48 is using Unsigned Data mode `1` AN48 is using Signed Data mode

ADCGIRQEN1ADC Global Interrupt Enable Register 1

Address: 0xBF887080
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
AGIEN27	27	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN26	26	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN25	25	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN24	24	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN19	19	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN18	18	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN17	17	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN16	16	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN15	15	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN14	14	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN13	13	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN12	12	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN11	11	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN10	10	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN9	9	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN8	8	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN7	7	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN6	6	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN5	5	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4	4	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN3	3	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2	2	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1	1	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN0	0	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)

ADCGIRQEN2ADC Global Interrupt Enable Register 2

Address: 0xBF887090
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
AGIEN53	21	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN52	20	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN51	19	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN50	18	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN49	17	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN48	16	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)

ADCCSS1ADC Common Scan Select Register 1

Address: 0xBF8870A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
CSS27	27	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS26	26	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS25	25	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS24	24	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS19	19	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS18	18	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS17	17	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS16	16	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS15	15	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS14	14	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS13	13	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS12	12	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS11	11	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS10	10	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS9	9	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS8	8	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS7	7	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS6	6	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS5	5	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4	4	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS3	3	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2	2	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1	1	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS0	0	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)

ADCCSS2ADC Common Scan Select Register 2

Address: 0xBF8870B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CSS53	21	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS52	20	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS51	19	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS50	18	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS49	17	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS48	16	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)

ADCDSTAT1ADC Data Ready Status Register 1

Address: 0xBF8870C0
Reset: 0x00000000
Access: read only
Size: 32-bit

24 fields

Field	Bits	What it does
ARDY27	27	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY26	26	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY25	25	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY24	24	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY19	19	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY18	18	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY17	17	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY16	16	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY15	15	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY14	14	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY13	13	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY12	12	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY11	11	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY10	10	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY9	9	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY8	8	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY7	7	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY6	6	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY5	5	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY4	4	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY3	3	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY2	2	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY1	1	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY0	0	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register

ADCDSTAT2ADC Data Ready Status Register 2

Address: 0xBF8870D0
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
ARDY53	21	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY52	20	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY51	19	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY50	18	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY49	17	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register
ARDY48	16	Conversion Data Ready for Corresponding Analog Input Ready bits `0` This bit is cleared when the associated data register is read `1` This bit is set when converted data is ready in the data register

ADCCMPEN1ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address: 0xBF8870E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
CMPE27	27
CMPE26	26
CMPE25	25
CMPE24	24
CMPE19	19
CMPE18	18
CMPE17	17
CMPE16	16
CMPE15	15
CMPE14	14
CMPE13	13
CMPE12	12
CMPE11	11
CMPE10	10
CMPE9	9
CMPE8	8
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMP1ADC Digital Comparator

Address: 0xBF8870F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DCMPLO	15:0
DCMPHI	31:16

ADCCMPEN2ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address: 0xBF887100
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
CMPE27	27
CMPE26	26
CMPE25	25
CMPE24	24
CMPE19	19
CMPE18	18
CMPE17	17
CMPE16	16
CMPE15	15
CMPE14	14
CMPE13	13
CMPE12	12
CMPE11	11
CMPE10	10
CMPE9	9
CMPE8	8
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMP2ADC Digital Comparator

Address: 0xBF887110
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DCMPLO	15:0
DCMPHI	31:16

ADCCMPEN3ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address: 0xBF887120
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
CMPE27	27
CMPE26	26
CMPE25	25
CMPE24	24
CMPE19	19
CMPE18	18
CMPE17	17
CMPE16	16
CMPE15	15
CMPE14	14
CMPE13	13
CMPE12	12
CMPE11	11
CMPE10	10
CMPE9	9
CMPE8	8
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMP3ADC Digital Comparator

Address: 0xBF887130
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DCMPLO	15:0
DCMPHI	31:16

ADCCMPEN4ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address: 0xBF887140
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
CMPE27	27
CMPE26	26
CMPE25	25
CMPE24	24
CMPE19	19
CMPE18	18
CMPE17	17
CMPE16	16
CMPE15	15
CMPE14	14
CMPE13	13
CMPE12	12
CMPE11	11
CMPE10	10
CMPE9	9
CMPE8	8
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMP4ADC Digital Comparator

Address: 0xBF887150
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DCMPLO	15:0
DCMPHI	31:16

ADCFLTR1ADC Digital Filter Register

Address: 0xBF8871A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN	30	Filter Significant Data Length bit `0` Only the first 12 bits are significant `1` All 16 bits of the filter output data are significant
DFMODE	29	ADC Filter Mode bit `0` Filter x works in Oversampling Filter mode (default) `1` Filter x works in Averaging mode
OVRSAM	28:26	Oversampling Filter Ratio bits `0` (If DFMODE is 0) 4 samples (shift sum 1 bit to right output data is 13 bits) / (If DFMODE is 1) 2 samples (2 samples to be averaged) `1` (If DFMODE is 0) 16 samples (shift sum 2 bits to right output data is 14 bits) / (If DFMODE is 1) 4 samples (4 samples to be averaged) `2` (If DFMODE is 0) 64 samples (shift sum 3 bits to right output data is 15 bits) / (If DFMODE is 1) 8 samples (8 samples to be averaged) `3` (If DFMODE is 0) 256 samples (shift sum 4 bits to right output data is 16 bits) / (If DFMODE is 1) 16 samples (16 samples to be averaged) `4` (If DFMODE is 0) 2 samples (shift sum 0 bits to right output data is in 12.1 format) / (If DFMODE is 1) 32 samples (32 samples to be averaged) `5` (If DFMODE is 0) 8 samples (shift sum 1 bit to right output data is in 13.1 format) / (If DFMODE is 1) 64 samples (64 samples to be averaged) `6` (If DFMODE is 0) 32 samples (shift sum 2 bits to right output data is in 14.1 format) / (If DFMODE is 1) 128 samples (128 samples to be averaged) `7` (If DFMODE is 0) 128 samples (shift sum 3 bits to right output data is in 15.1 format) / (If DFMODE is 1) 256 samples (256 samples to be averaged)
AFGIEN	25	Digital Filter 'x' Interrupt Enable bit `0` Digital filter is disabled `1` Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY	24	Digital Filter 'x' Data Ready Status bit `0` Data is not ready `1` Data is ready in the FLTRDATA bits
CHNLID	20:16	Digital Filter Analog Input Selection bits `0` ADC0 Module `1` ADC1 Module `2` ADC2 Module `3` ADC3 Module `4` ADC4 Module `5` ADC5 Module `6` AN6 input `7` AN7 input `8` AN8 input `9` AN9 input `10` AN10 input `11` AN11 input `12` AN12 input `13` AN13 input `14` AN14 input `15` AN15 input `16` AN16 input `17` AN17 input `18` AN18 input `19` AN19 input `20` AN20(1) input `21` AN21(1) input `22` AN22(1) input `23` AN23(1) input `24` AN24 input `25` AN25 input `26` AN26 input `27` AN27 input
FLTRDATA	15:0
AFEN	31	Digital Filter 'x' Enable bit `0` Digital filter is disabled and the AFRDY status bit is cleared `1` Digital filter is enabled

ADCFLTR2ADC Digital Filter Register

Address: 0xBF8871B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN	30	Filter Significant Data Length bit `0` Only the first 12 bits are significant `1` All 16 bits of the filter output data are significant
DFMODE	29	ADC Filter Mode bit `0` Filter x works in Oversampling Filter mode (default) `1` Filter x works in Averaging mode
OVRSAM	28:26	Oversampling Filter Ratio bits `0` (If DFMODE is 0) 4 samples (shift sum 1 bit to right output data is 13 bits) / (If DFMODE is 1) 2 samples (2 samples to be averaged) `1` (If DFMODE is 0) 16 samples (shift sum 2 bits to right output data is 14 bits) / (If DFMODE is 1) 4 samples (4 samples to be averaged) `2` (If DFMODE is 0) 64 samples (shift sum 3 bits to right output data is 15 bits) / (If DFMODE is 1) 8 samples (8 samples to be averaged) `3` (If DFMODE is 0) 256 samples (shift sum 4 bits to right output data is 16 bits) / (If DFMODE is 1) 16 samples (16 samples to be averaged) `4` (If DFMODE is 0) 2 samples (shift sum 0 bits to right output data is in 12.1 format) / (If DFMODE is 1) 32 samples (32 samples to be averaged) `5` (If DFMODE is 0) 8 samples (shift sum 1 bit to right output data is in 13.1 format) / (If DFMODE is 1) 64 samples (64 samples to be averaged) `6` (If DFMODE is 0) 32 samples (shift sum 2 bits to right output data is in 14.1 format) / (If DFMODE is 1) 128 samples (128 samples to be averaged) `7` (If DFMODE is 0) 128 samples (shift sum 3 bits to right output data is in 15.1 format) / (If DFMODE is 1) 256 samples (256 samples to be averaged)
AFGIEN	25	Digital Filter 'x' Interrupt Enable bit `0` Digital filter is disabled `1` Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY	24	Digital Filter 'x' Data Ready Status bit `0` Data is not ready `1` Data is ready in the FLTRDATA bits
CHNLID	20:16	Digital Filter Analog Input Selection bits `0` ADC0 Module `1` ADC1 Module `2` ADC2 Module `3` ADC3 Module `4` ADC4 Module `5` ADC5 Module `6` AN6 input `7` AN7 input `8` AN8 input `9` AN9 input `10` AN10 input `11` AN11 input `12` AN12 input `13` AN13 input `14` AN14 input `15` AN15 input `16` AN16 input `17` AN17 input `18` AN18 input `19` AN19 input `20` AN20(1) input `21` AN21(1) input `22` AN22(1) input `23` AN23(1) input `24` AN24 input `25` AN25 input `26` AN26 input `27` AN27 input
FLTRDATA	15:0
AFEN	31	Digital Filter 'x' Enable bit `0` Digital filter is disabled and the AFRDY status bit is cleared `1` Digital filter is enabled

ADCFLTR3ADC Digital Filter Register

Address: 0xBF8871C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN	30	Filter Significant Data Length bit `0` Only the first 12 bits are significant `1` All 16 bits of the filter output data are significant
DFMODE	29	ADC Filter Mode bit `0` Filter x works in Oversampling Filter mode (default) `1` Filter x works in Averaging mode
OVRSAM	28:26	Oversampling Filter Ratio bits `0` (If DFMODE is 0) 4 samples (shift sum 1 bit to right output data is 13 bits) / (If DFMODE is 1) 2 samples (2 samples to be averaged) `1` (If DFMODE is 0) 16 samples (shift sum 2 bits to right output data is 14 bits) / (If DFMODE is 1) 4 samples (4 samples to be averaged) `2` (If DFMODE is 0) 64 samples (shift sum 3 bits to right output data is 15 bits) / (If DFMODE is 1) 8 samples (8 samples to be averaged) `3` (If DFMODE is 0) 256 samples (shift sum 4 bits to right output data is 16 bits) / (If DFMODE is 1) 16 samples (16 samples to be averaged) `4` (If DFMODE is 0) 2 samples (shift sum 0 bits to right output data is in 12.1 format) / (If DFMODE is 1) 32 samples (32 samples to be averaged) `5` (If DFMODE is 0) 8 samples (shift sum 1 bit to right output data is in 13.1 format) / (If DFMODE is 1) 64 samples (64 samples to be averaged) `6` (If DFMODE is 0) 32 samples (shift sum 2 bits to right output data is in 14.1 format) / (If DFMODE is 1) 128 samples (128 samples to be averaged) `7` (If DFMODE is 0) 128 samples (shift sum 3 bits to right output data is in 15.1 format) / (If DFMODE is 1) 256 samples (256 samples to be averaged)
AFGIEN	25	Digital Filter 'x' Interrupt Enable bit `0` Digital filter is disabled `1` Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY	24	Digital Filter 'x' Data Ready Status bit `0` Data is not ready `1` Data is ready in the FLTRDATA bits
CHNLID	20:16	Digital Filter Analog Input Selection bits `0` ADC0 Module `1` ADC1 Module `2` ADC2 Module `3` ADC3 Module `4` ADC4 Module `5` ADC5 Module `6` AN6 input `7` AN7 input `8` AN8 input `9` AN9 input `10` AN10 input `11` AN11 input `12` AN12 input `13` AN13 input `14` AN14 input `15` AN15 input `16` AN16 input `17` AN17 input `18` AN18 input `19` AN19 input `20` AN20(1) input `21` AN21(1) input `22` AN22(1) input `23` AN23(1) input `24` AN24 input `25` AN25 input `26` AN26 input `27` AN27 input
FLTRDATA	15:0
AFEN	31	Digital Filter 'x' Enable bit `0` Digital filter is disabled and the AFRDY status bit is cleared `1` Digital filter is enabled

ADCFLTR4ADC Digital Filter Register

Address: 0xBF8871D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN	30	Filter Significant Data Length bit `0` Only the first 12 bits are significant `1` All 16 bits of the filter output data are significant
DFMODE	29	ADC Filter Mode bit `0` Filter x works in Oversampling Filter mode (default) `1` Filter x works in Averaging mode
OVRSAM	28:26	Oversampling Filter Ratio bits `0` (If DFMODE is 0) 4 samples (shift sum 1 bit to right output data is 13 bits) / (If DFMODE is 1) 2 samples (2 samples to be averaged) `1` (If DFMODE is 0) 16 samples (shift sum 2 bits to right output data is 14 bits) / (If DFMODE is 1) 4 samples (4 samples to be averaged) `2` (If DFMODE is 0) 64 samples (shift sum 3 bits to right output data is 15 bits) / (If DFMODE is 1) 8 samples (8 samples to be averaged) `3` (If DFMODE is 0) 256 samples (shift sum 4 bits to right output data is 16 bits) / (If DFMODE is 1) 16 samples (16 samples to be averaged) `4` (If DFMODE is 0) 2 samples (shift sum 0 bits to right output data is in 12.1 format) / (If DFMODE is 1) 32 samples (32 samples to be averaged) `5` (If DFMODE is 0) 8 samples (shift sum 1 bit to right output data is in 13.1 format) / (If DFMODE is 1) 64 samples (64 samples to be averaged) `6` (If DFMODE is 0) 32 samples (shift sum 2 bits to right output data is in 14.1 format) / (If DFMODE is 1) 128 samples (128 samples to be averaged) `7` (If DFMODE is 0) 128 samples (shift sum 3 bits to right output data is in 15.1 format) / (If DFMODE is 1) 256 samples (256 samples to be averaged)
AFGIEN	25	Digital Filter 'x' Interrupt Enable bit `0` Digital filter is disabled `1` Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY	24	Digital Filter 'x' Data Ready Status bit `0` Data is not ready `1` Data is ready in the FLTRDATA bits
CHNLID	20:16	Digital Filter Analog Input Selection bits `0` ADC0 Module `1` ADC1 Module `2` ADC2 Module `3` ADC3 Module `4` ADC4 Module `5` ADC5 Module `6` AN6 input `7` AN7 input `8` AN8 input `9` AN9 input `10` AN10 input `11` AN11 input `12` AN12 input `13` AN13 input `14` AN14 input `15` AN15 input `16` AN16 input `17` AN17 input `18` AN18 input `19` AN19 input `20` AN20(1) input `21` AN21(1) input `22` AN22(1) input `23` AN23(1) input `24` AN24 input `25` AN25 input `26` AN26 input `27` AN27 input
FLTRDATA	15:0
AFEN	31	Digital Filter 'x' Enable bit `0` Digital filter is disabled and the AFRDY status bit is cleared `1` Digital filter is enabled

ADCTRG1ADC Trigger Source 1 Register

Address: 0xBF887200
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC3	28:24	Trigger Source for Conversion of ADC3 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary Special Event time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 period end `17` Output Compare 2 period end `18` Output Compare 3 period end `19` Output Compare 4 period end `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC2	20:16	Trigger Source for Conversion of ADC2 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary Special Event time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 period end `17` Output Compare 2 period end `18` Output Compare 3 period end `19` Output Compare 4 period end `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC1	12:8	Trigger Source for Conversion of ADC1 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary Special Event time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 period end `17` Output Compare 2 period end `18` Output Compare 3 period end `19` Output Compare 4 period end `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC0	4:0	Trigger Source for Conversion of ADC0 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary Special Event time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 period end `17` Output Compare 2 period end `18` Output Compare 3 period end `19` Output Compare 4 period end `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)

ADCTRG2ADC Trigger Source 2 Register

Address: 0xBF887210
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC7	28:24	Trigger Source for Conversion of Analog Input AN7 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor Control Only) `29` PWM Generator 11 trigger (Motor Control Only) `30` PWM Generator 12 trigger (Motor Control Only)
TRGSRC6	20:16	Trigger Source for Conversion of Analog Input AN6 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor Control Only) `29` PWM Generator 11 trigger (Motor Control Only) `30` PWM Generator 12 trigger (Motor Control Only)
TRGSRC5	12:8	Trigger Source for Conversion of ADC5 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor Control Only) `29` PWM Generator 11 trigger (Motor Control Only) `30` PWM Generator 12 trigger (Motor Control Only)
TRGSRC4	4:0	Trigger Source for Conversion of ADC4 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control Variants Only) `9` Secondary Special time base (Motor Control Variants Only) `10` PWM Generator 1 trigger (Motor Control Variants Only) `11` PWM Generator 2 trigger (Motor Control Variants Only) `12` PWM Generator 3 trigger (Motor Control Variants Only) `13` PWM Generator 4 trigger (Motor Control Variants Only) `14` PWM Generator 5 trigger (Motor Control Variants Only) `15` PWM Generator 6 trigger (Motor Control Variants Only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control Variants Only) `25` PWM Generator 2 Current-Limit (Motor Control Variants Only) `26` PWM Generator 3 Current-Limit (Motor Control Variants Only) `27` PWM Generator 4 Current-Limit (Motor Control Variants Only) `28` PWM Generator 10 trigger (Motor Control Only) `29` PWM Generator 11 trigger (Motor Control Only) `30` PWM Generator 12 trigger (Motor Control Only)

ADCTRG3ADC Trigger Source 3 Register

Address: 0xBF887220
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC11	28:24	Trigger Source for Conversion of Analog Input AN11 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC10	20:16	Trigger Source for Conversion of Analog Input AN10 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC9	12:8	Trigger Source for Conversion of Analog Input AN9 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC8	4:0	Trigger Source for Conversion of Analog Input AN8 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)

ADCTRG4ADC Trigger Source 4 Register

Address: 0xBF887230
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC15	28:24	Trigger Source for Conversion of Analog Input AN15 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger `29` PWM Generator 11 trigger `30` PWM Generator 12 trigger
TRGSRC14	20:16	Trigger Source for Conversion of Analog Input AN14 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger `29` PWM Generator 11 trigger `30` PWM Generator 12 trigger
TRGSRC13	12:8	Trigger Source for Conversion of Analog Input AN13 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger `29` PWM Generator 11 trigger `30` PWM Generator 12 trigger
TRGSRC12	4:0	Trigger Source for Conversion of Analog Input AN12 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge Only) `17` Output Compare 2 (Rising Edge Only) `18` Output Compare 3 (Rising Edge Only) `19` Output Compare 4 (Rising Edge Only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger `29` PWM Generator 11 trigger `30` PWM Generator 12 trigger

ADCTRG5ADC Trigger Source 5 Register

Address: 0xBF887240
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC19	28:24	Trigger Source for Conversion of Analog Input AN19 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC18	20:16	Trigger Source for Conversion of Analog Input AN18 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC17	12:8	Trigger Source for Conversion of Analog Input AN17 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC16	4:0	Trigger Source for Conversion of Analog Input AN16 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)

ADCTRG7ADC Trigger Source 7 Register

Address: 0xBF887260
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC27	28:24	Trigger Source for Conversion of Analog Input AN27 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see the following Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC26	20:16	Trigger Source for Conversion of Analog Input AN26 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see the following Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC25	12:8	Trigger Source for Conversion of Analog Input AN25 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see the following Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)
TRGSRC24	4:0	Trigger Source for Conversion of Analog Input AN24 Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger (see the following Note) `4` INT0 `5` General Purpose Timer1 `6` General Purpose Timer3 `7` General Purpose Timer5 `8` Primary PWM time base (Motor Control only) `9` Secondary PWM time base (Motor Control only) `10` PWM Generator 1 trigger (Motor Control only) `11` PWM Generator 2 trigger (Motor Control only) `12` PWM Generator 3 trigger (Motor Control only) `13` PWM Generator 4 trigger (Motor Control only) `14` PWM Generator 5 trigger (Motor Control only) `15` PWM Generator 6 trigger (Motor Control only) `16` Output Compare 1 (Rising Edge only) `17` Output Compare 2 (Rising Edge only) `18` Output Compare 3 (Rising Edge only) `19` Output Compare 4 (Rising Edge only) `20` CTMU trip `21` PWM Generator 7 trigger `22` PWM Generator 8 trigger `23` PWM Generator 9 trigger `24` PWM Generator 1 Current-Limit (Motor Control only) `25` PWM Generator 2 Current-Limit (Motor Control only) `26` PWM Generator 3 Current-Limit (Motor Control only) `27` PWM Generator 4 Current-Limit (Motor Control only) `28` PWM Generator 10 trigger (Motor control only) `29` PWM Generator 11 trigger (Motor control only) `30` PWM Generator 12 trigger (Motor control only)

ADCCMPCON1ADC Digital Comparator 1 Control Register

Address: 0xBF887280
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
AINID	13:8	Digital Comparator 'x' Analog Input Identification bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` AN8 `9` AN9 `10` AN10 `11` AN11 `12` AN12 `13` AN13 `14` AN14 `15` AN15 `16` AN16 `17` AN17 `18` AN18 `19` AN19 `20` AN20 `21` AN21 `22` AN22 `23` AN23 `24` AN24 `25` AN25 `26` AN26 `27` AN27
ENDCMP	7	Digital Comparator 'x' Enable bit `0` Digital Comparator 1 is not enabled `1` Digital Comparator 1 is enabled
DCMPGIEN	6	Digital Comparator 'x' Global Interrupt Enable bit `0` A Digital Comparator 1 interrupt is disabled `1` A Digital Comparator 1 interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED	5	Digital Comparator 'x' "Output True" Event Status bit `0` Digital Comparator 1 output is false (output of Comparator is 0) `1` Digital Comparator 1 output true event has occurred (output of Comparator is 1)
IEBTWN	4	Between Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a digital comparator event when the DCMPLO bits less than DATA bits less than DCMPHI bits
IEHIHI	3	High/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 1 Event when the DCMPHI bits less than or equal to DATA(31:0) bits
IEHILO	2	High/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 1 Event when the DATA bits less than DCMPHI(15:0) bits
IELOHI	1	Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 1 Event when the DCMPLO bits less than DATA(31:0) bits
IELOLO	0	Low/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 1 Event when the DATA bits less than DCMPLO(15:0) bits
CVDDATA	31:16

ADCCMPCON2ADC Digital Comparator 2 Control Register

Address: 0xBF887290
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
AINID	12:8	Digital Comparator 'x' Analog Input Identification bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` AN8 `9` AN9 `10` AN10 `11` AN11 `12` AN12 `13` AN13 `14` AN14 `15` AN15 `16` AN16 `17` AN17 `18` AN18 `19` AN19 `20` AN20 `21` AN21 `22` AN22 `23` AN23 `24` AN24 `25` AN25 `26` AN26 `27` AN27
ENDCMP	7	Digital Comparator 'x' Enable bit `0` Digital Comparator 2 is not enabled `1` Digital Comparator 2 is enabled
DCMPGIEN	6	Digital Comparator 'x' Global Interrupt Enable bit `0` A Digital Comparator 2 interrupt is disabled `1` A Digital Comparator 2 interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED	5	Digital Comparator 'x' "Output True" Event Status bit `0` Digital Comparator 2 output is false (output of Comparator is 0) `1` Digital Comparator 2 output true event has occurred (output of Comparator is 1)
IEBTWN	4	Between Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a digital comparator event when the DCMPLO bits less than DATA bits less than DCMPHI bits
IEHIHI	3	High/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 2 Event when the DCMPHI bits less than or equal to DATA(31:0) bits
IEHILO	2	High/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 2 Event when the DATA bits less than DCMPHI(15:0) bits
IELOHI	1	Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 2 Event when the DCMPLO bits less than DATA(31:0) bits
IELOLO	0	Low/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 2 Event when the DATA bits less than DCMPLO(15:0) bits

ADCCMPCON3ADC Digital Comparator 2 Control Register

Address: 0xBF8872A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
AINID	12:8	Digital Comparator 'x' Analog Input Identification bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` AN8 `9` AN9 `10` AN10 `11` AN11 `12` AN12 `13` AN13 `14` AN14 `15` AN15 `16` AN16 `17` AN17 `18` AN18 `19` AN19 `20` AN20 `21` AN21 `22` AN22 `23` AN23 `24` AN24 `25` AN25 `26` AN26 `27` AN27
ENDCMP	7	Digital Comparator 'x' Enable bit `0` Digital Comparator 3 is not enabled `1` Digital Comparator 3 is enabled
DCMPGIEN	6	Digital Comparator 'x' Global Interrupt Enable bit `0` A Digital Comparator 3 interrupt is disabled `1` A Digital Comparator 3 interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED	5	Digital Comparator 'x' "Output True" Event Status bit `0` Digital Comparator 3 output is false (output of Comparator is 0) `1` Digital Comparator 3 output true event has occurred (output of Comparator is 1)
IEBTWN	4	Between Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a digital comparator event when the DCMPLO bits less than DATA bits less than DCMPHI bits
IEHIHI	3	High/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 3 Event when the DCMPHI bits less than or equal to DATA(31:0) bits
IEHILO	2	High/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 3 Event when the DATA bits less than DCMPHI(15:0) bits
IELOHI	1	Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 3 Event when the DCMPLO bits less than DATA(31:0) bits
IELOLO	0	Low/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 3 Event when the DATA bits less than DCMPLO(15:0) bits

ADCCMPCON4ADC Digital Comparator 2 Control Register

Address: 0xBF8872B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
AINID	12:8	Digital Comparator 'x' Analog Input Identification bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` AN8 `9` AN9 `10` AN10 `11` AN11 `12` AN12 `13` AN13 `14` AN14 `15` AN15 `16` AN16 `17` AN17 `18` AN18 `19` AN19 `20` AN20 `21` AN21 `22` AN22 `23` AN23 `24` AN24 `25` AN25 `26` AN26 `27` AN27
ENDCMP	7	Digital Comparator 'x' Enable bit `0` Digital Comparator 4 is not enabled `1` Digital Comparator 4 is enabled
DCMPGIEN	6	Digital Comparator 'x' Global Interrupt Enable bit `0` A Digital Comparator 4 interrupt is disabled `1` A Digital Comparator 4 interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED	5	Digital Comparator 'x' "Output True" Event Status bit `0` Digital Comparator 4 output is false (output of Comparator is 0) `1` Digital Comparator 4 output true event has occurred (output of Comparator is 1)
IEBTWN	4	Between Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a digital comparator event when the DCMPLO bits less than DATA bits less than DCMPHI bits
IEHIHI	3	High/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 4 Event when the DCMPHI bits less than or equal to DATA(31:0) bits
IEHILO	2	High/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 4 Event when the DATA bits less than DCMPHI(15:0) bits
IELOHI	1	Low/High Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 4 Event when the DCMPLO bits less than DATA(31:0) bits
IELOLO	0	Low/Low Digital Comparator x Event bit `0` Do not generate an event `1` Generate a Digital Comparator 4 Event when the DATA bits less than DCMPLO(15:0) bits

ADCBASEADC Base Register

Address: 0xBF887300
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCBASE	15:0	ADC ISR Base Address bits `0` Base address is 0

ADCDSTATADC DMA Status Register

Address: 0xBF887310
Reset: 0x00000000
Access: read/write
Size: 32-bit

27 fields

Field	Bits	What it does
RBFIEN5	29	RAM DMA Buffer B Full Interrupt Enable bits for ADC5 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN4	28	RAM DMA Buffer B Full Interrupt Enable bits for ADC4 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN3	27	RAM DMA Buffer B Full Interrupt Enable bits for ADC3 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN2	26	RAM DMA Buffer B Full Interrupt Enable bits for ADC2 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN1	25	RAM DMA Buffer B Full Interrupt Enable bits for ADC1 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN0	24	RAM DMA Buffer B Full Interrupt Enable bits for ADC0 `0` Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0 `1` Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
WOVERR	23
RBF5	21	RAM DMA Buffer B Full Status bits for ADC5 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
RBF4	20	RAM DMA Buffer B Full Status bits for ADC4 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
RBF3	19	RAM DMA Buffer B Full Status bits for ADC3 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
RBF2	18	RAM DMA Buffer B Full Status bits for ADC2 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
RBF1	17	RAM DMA Buffer B Full Status bits for ADC1 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
RBF0	16	RAM DMA Buffer B Full Status bits for ADC0 `0` RAM DMA pin-pong Buffer B is not full `1` RAM DMA ping-pong Buffer B is full
DMACEN	15
RAFIEN5	13	RAM DMA Buffer A Full Interrupt Enable bits for ADC5 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN4	12	RAM DMA Buffer A Full Interrupt Enable bits for ADC4 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN3	11	RAM DMA Buffer A Full Interrupt Enable bits for ADC3 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN2	10	RAM DMA Buffer A Full Interrupt Enable bits for ADC2 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN1	9	RAM DMA Buffer A Full Interrupt Enable bits for ADC1 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN0	8	RAM DMA Buffer A Full Interrupt Enable bits for ADC0 `0` Disable ping-pong DMA Buffer A interrupt requests for ADC `1` Enable ping-pong DMA Buffer A interrupt requests for ADC
RAF5	5	RAM DMA Ping-Pong Buffer A Full Status bits for ADC5 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
RAF4	4	RAM DMA Ping-Pong Buffer A Full Status bits for ADC4 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
RAF3	3	RAM DMA Ping-Pong Buffer A Full Status bits for ADC3 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
RAF2	2	RAM DMA Ping-Pong Buffer A Full Status bits for ADC2 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
RAF1	1	RAM DMA Ping-Pong Buffer A Full Status bits for ADC1 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
RAF0	0	RAM DMA Ping-Pong Buffer A Full Status bits for ADC0 `0` RAM DMA ping-pong Buffer A is not full `1` RAM DMA ping-pong Buffer A is full
DMAEN	31	Global ADC DMA Enable bit `0` DMA interface is disabled `1` DMA interface is enabled

ADCCNTBADC Channel Sample Count Base Address Register

Address: 0xBF887320
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCNTB	31:0

ADCDMABADC Channel Sample Count Base Address Register

Address: 0xBF887330
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCDMAB	31:0

ADCTRGSNSADC Trigger Level/Edge Sensitivity Register

Address: 0xBF887340
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
LVL27	27	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL26	26	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL25	25	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL24	24	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL19	19	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL18	18	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL17	17	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL16	16	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL15	15	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL14	14	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL13	13	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL12	12	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL11	11	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL10	10	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL9	9	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL8	8	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL7	7	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL6	6	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL5	5	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL4	4	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL3	3	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2	2	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1	1	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL0	0	Trigger Level and Edge Sensitivity bits `0` Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) `1` Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)

ADC0TIMEDedicated High-Speed ADCx Timing Register 0

Address: 0xBF887350
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADC1TIMEDedicated High-Speed ADCx Timing Register 1

Address: 0xBF887360
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADC2TIMEDedicated High-Speed ADCx Timing Register 2

Address: 0xBF887370
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADC3TIMEDedicated High-Speed ADCx Timing Register 3

Address: 0xBF887380
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADC4TIMEDedicated High-Speed ADCx Timing Register 4

Address: 0xBF887390
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADC5TIMEDedicated High-Speed ADCx Timing Register 5

Address: 0xBF8873A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ADCEIS	28:26	ADCx Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC clock prior to the end of conversion `1` The data ready interrupt is generated 2 ADC clocks prior to the end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to the end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to the end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to the end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to the end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to the end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES	25:24	ADCx Resolution Select bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits
BCHEN	23	Buffer Channel Enable bit `0` ADC data must be read by CPU from appropriate ADC result register `1` ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV	22:16	ADCx Clock Divisor bits `0` Reserved `1` 2 * TQ = TADx `2` 4 * TQ = TADx `3` 6 * TQ = TADx `127` 254 * TQ = TADx
SAMC	9:0	ADCx Sample Time bits `0` 2 TADx `1` 3 TADx `1023` 1025 TADx

ADCEIQEN1

Address: 0xBF8873C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
EIEN27	27
EIEN26	26
EIEN25	25
EIEN24	24
EIEN19	19
EIEN18	18
EIEN17	17
EIEN16	16
EIEN15	15
EIEN14	14
EIEN13	13
EIEN12	12
EIEN11	11
EIEN10	10
EIEN9	9
EIEN8	8
EIEN7	7
EIEN6	6
EIEN5	5
EIEN4	4
EIEN3	3
EIEN2	2
EIEN1	1
EIEN0	0

ADCEIQEN2

Address: 0xBF8873D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
EIEN53	21
EIEN52	20
EIEN51	19
EIEN50	18
EIEN49	17
EIEN48	16

ADCEISTAT1ADC Early Interrupt Status Register 1

Address: 0xBF8873E0
Reset: 0x00000000
Access: read only
Size: 32-bit

24 fields

Field	Bits	What it does
EIRDY27	27	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY26	26	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY25	25	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY24	24	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY19	19	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY18	18	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY17	17	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY16	16	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY15	15	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY14	14	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY13	13	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY12	12	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY11	11	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY10	10	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY9	9	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY8	8	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY7	7	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY6	6	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY5	5	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY4	4	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY3	3	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY2	2	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY1	1	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY0	0	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs

ADCEISTAT2ADC Early Interrupt Status Register 2

Address: 0xBF8873F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
EIRDY53	21	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY52	20	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY51	19	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY50	18	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY49	17	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs
EIRDY48	16	Early Interrupt for Corresponding Analog Input Ready bits `0` Interrupts are disabled `1` Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early interrupt event occurs

ADCANCONADC Analog Warm-up Control Register

Address: 0xBF887400
Reset: 0x00000000
Access: read/write
Size: 32-bit

22 fields

Field	Bits	What it does
WKUPCLKCNT	27:24	Wake-up Clock Count bits `0` 2^4 = 16 clocks `5` 2^5 = 32 clocks `6` 2^6 = 64 clocks `7` 2^7 = 128 clocks `8` 2^8 = 256 clocks `9` 2^9 = 512 clocks `10` 2^10 = 1024 clocks `11` 2^11 = 2048 clocks `12` 2^12 = 4096 clocks `13` 2^13 = 8192 clocks `14` 2^14 = 16384 clocks `15` 2^15 = 32768 clocks
WKIEN7	23	Shared ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDY7 status bit is set
WKIEN5	21	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN4	20	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN3	19	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN2	18	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN1	17	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN0	16	ADC Wake-up Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKRDY7	15	Shared ADC Wake-up Status bit `0` ADC7 Analog and Bias circuitry is not ready `1` ADC7 Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANEN7 to 1
WKRDY5	13	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY4	12	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY3	11	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY2	10	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY1	9	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY0	8	ADC5-ADC0 Wake-up Status bit `0` ADCx Analog and Bias circuitry is not ready `1` ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
ANEN7	7	Shared ADC Analog and Bias Circuitry Enable bit `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN5	5	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN4	4	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN3	3	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN2	2	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN1	1	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN0	0	ADC Analog and Bias Circuitry Enable bits `0` Analog and bias circuitry disabled `1` Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.

ADCDATA0ADC Output Data Register

Address: 0xBF887600
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA1ADC Output Data Register

Address: 0xBF887610
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA2ADC Output Data Register

Address: 0xBF887620
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA3ADC Output Data Register

Address: 0xBF887630
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA4ADC Output Data Register

Address: 0xBF887640
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA5ADC Output Data Register

Address: 0xBF887650
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA6ADC Output Data Register

Address: 0xBF887660
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA7ADC Output Data Register

Address: 0xBF887670
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA8ADC Output Data Register

Address: 0xBF887680
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA9ADC Output Data Register

Address: 0xBF887690
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA10ADC Output Data Register

Address: 0xBF8876A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA11ADC Output Data Register

Address: 0xBF8876B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA12ADC Output Data Register

Address: 0xBF8876C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA13ADC Output Data Register

Address: 0xBF8876D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA14ADC Output Data Register

Address: 0xBF8876E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA15ADC Output Data Register

Address: 0xBF8876F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA16ADC Output Data Register

Address: 0xBF887700
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA17ADC Output Data Register

Address: 0xBF887710
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA18ADC Output Data Register

Address: 0xBF887720
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA19ADC Output Data Register

Address: 0xBF887730
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA24ADC Output Data Register

Address: 0xBF887780
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA25ADC Output Data Register

Address: 0xBF887790
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA26ADC Output Data Register

Address: 0xBF8877A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA27ADC Output Data Register

Address: 0xBF8877B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA48ADC Output Data Register

Address: 0xBF887900
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA49ADC Output Data Register

Address: 0xBF887910
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA50ADC Output Data Register

Address: 0xBF887920
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA51

Address: 0xBF887930
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA52

Address: 0xBF887940
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA53ADC Output Data Register

Address: 0xBF887950
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADC0CFGADC0 Configuration Register

Address: 0xBF887D00
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC1CFGADC1 Configuration Register

Address: 0xBF887D10
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC2CFGADC2 Configuration Register

Address: 0xBF887D20
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC3CFGADC3 Configuration Register

Address: 0xBF887D30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC4CFGADC4 Configuration Register

Address: 0xBF887D40
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC5CFGADC5 Configuration Register

Address: 0xBF887D50
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC6CFG

Address: 0xBF887D60
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADC7CFG

Address: 0xBF887D70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCFG	31:0

ADCSYSCFG0ADC System Configuration Register 0

Address: 0xBF887E00
Reset: 0x00000000
Access: read only
Size: 32-bit

24 fields

Field	Bits	What it does
AN27	27
AN26	26
AN25	25
AN24	24
AN19	19
AN18	18
AN17	17
AN16	16
AN15	15
AN14	14
AN13	13
AN12	12
AN11	11
AN10	10
AN9	9
AN8	8
AN7	7
AN6	6
AN5	5
AN4	4
AN3	3
AN2	2
AN1	1
AN0	0

ADCSYSCFG1ADC System Configuration Register 1

Address: 0xBF887E10
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
AN53	21
AN52	20
AN51	19
AN50	18
AN49	17
AN48	16