PIC32MK1024MCM064 CAN registers

The 744 registers of CAN (CAN), from 0xBF880000, with their reset value and every field. The PIC32MK1024MCM064 has 2203 registers in 115 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CAN CAN

CFD1CONCAN Control Register

Address
0xBF880000
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
ABAT27Abort All Pending Transmissions bit
  • 0 Module will clear this bit when all transmissions aborted
  • 1 Signal all transmit buffers to abort transmission
REQOP26:24Request Operation Mode bits
  • 0 Set Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Set Disable mode
  • 2 Set Internal Loopback mode
  • 3 Set Listen Only mode
  • 4 Set Configuration mode
  • 5 Set External Loopback mode
  • 6 Set Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Set Restricted Operation mode
OPMOD23:21Operation Mode Status bits
  • 0 Module is in Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Module is in Disable mode
  • 2 Module is in Internal Loopback mode
  • 3 Module is in Listen Only mode
  • 4 Module is in Configuration mode
  • 5 Module is in External Loopback mode
  • 6 Module is Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Module is Restricted Operation mode
TXQEN20Enable Transmit Queue bit
  • 0 Dont reserve space in RAM for Transmit Queue
  • 1 Enables Transmit Queue and reserves space in RAM
STEF19Store in Transmit Event FIFO bit
  • 0 Dont save transmitted messages in TEF
  • 1 Save transmitted messages in TEF
SERR2LOM18Transition to Listen Only Mode on System Error bit
  • 0 Transition to Restricted Operation Mode
  • 1 Transition to Listen Only Mode
ESIGM17Transmit ESI in Gateway Mode bit
  • 0 ESI reflects error status of CAN controller
  • 1 ESI is transmitted as recessive when ESI of message is high or CAN controller error passive
RTXAT16Restrict Retransmission Attempts bit
  • 0 Unlimited number of retransmission attempts
  • 1 Restricted retransmission attempts
ON15Enable bit
  • 0 CAN module is disabled
  • 1 CAN module is enabled
SIDL13Stop-in-Idle Control bit
  • 0 Dont stop module operation in Idle mode
  • 1 Stop module operation in Idle mode
BRSDIS12Bit Rate Switching Disable bit
  • 0 Bit Rate Switching depends on BRS in the Transmit Message Object
  • 1 Bit Rate Switching is Disabled
BUSY11CAN Module is Busy bit
  • 0 The CAN module is inactive
  • 1 The CAN module is active
WFT10:9Selectable Wake-up Filter Time bits
  • 0 T00FILTER (Typical 100 ns)
  • 1 T01FILTER (Typical 187 ns)
  • 2 T10FILTER (Typical 375 ns)
  • 3 T11FILTER (Typical 600 ns)
WAKFIL8Enable CAN Bus Line Wake-up Filter bit
  • 0 CAN bus line filter is not used for wake-up
  • 1 Use CAN bus line filter for wake-up
CLKSEL07Module Clock Source Select bit
  • 0 SYSCLK is active when the CAN FD module is enabled
  • 1 REFCLK4 is active when the CAN FD module is enabled
PXEDIS6Protocol Exception Event Detection Disabled bit
  • 0 If a Protocol Exception is detected
  • 1 Protocol Exception is treated as a Form Error.
ISOCRCEN5Enable ISO CRC in CAN FD Frames bit
  • 0 Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros
  • 1 Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector
DNCNT4:0Device Net Filter Bit Number bits
TXBWS31:28Transmit Bandwidth Sharing bits
  • 0 No delay
  • 1 2
  • 2 4
  • 3 8
  • 4 16
  • 5 32
  • 6 64
  • 7 128
  • 8 256
  • 9 512
  • 10 1024
  • 11 2048
  • 12 4096

CFD1NBTCFGNominal Bit Time Configuration Register

Address
0xBF880010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG123:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 255 Length is 256 x Tq
TSEG214:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 31 Length is 128 x Tq
SJW6:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 127 Length is 128 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq = 1/Fsys
  • 255 Tq = 256/Fsys

CFD1DBTCFGData Bit Time Configuration Register

Address
0xBF880020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG120:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
  • 16 Length is 17 x Tq
  • 17 Length is 18 x Tq
  • 18 Length is 19 x Tq
  • 19 Length is 20 x Tq
  • 20 Length is 21 x Tq
  • 21 Length is 22 x Tq
  • 22 Length is 23 x Tq
  • 23 Length is 24 x Tq
  • 24 Length is 25 x Tq
  • 25 Length is 26 x Tq
  • 26 Length is 27 x Tq
  • 27 Length is 28 x Tq
  • 28 Length is 29 x Tq
  • 29 Length is 30 x Tq
  • 30 Length is 31 x Tq
  • 31 Length is 32 x Tq
TSEG211:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
SJW3:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq is 1/Fsys
  • 255 Tq is 256/Fsys

CFD1TDCTransmitter Delay Compensation Register

Address
0xBF880030
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EDGFLTEN25Enable Edge Filtering during Bus Integration state bit
  • 0 Edge Filtering disabled
  • 1 Edge Filtering enabled
SID11EN24Enable 12-Bit SID in CAN FD Base Format Messages bit
  • 0 Do not use RRS; SID(10-0) according to ISO11898-1 2015
  • 1 RRS is used as SID11 in CAN FD base format messages: SID(11-0) = {SID(10-0)
TDCMOD17:16Transmitter Delay Compensation Mode bits
  • 0 Disable
  • 1 Manual; Do not measure use TDCV plus TDCO from the register
  • 2 Auto; measure delay and add CFDxDBTCFG.TSEG1; add TDCO
TDCO14:8Transmitter Delay Compensation Offset bits
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK
TDCV5:0Transmitter Delay Compensation Value bits; Secondary Sample Point
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK

CFD1TBCCAN Time Base Counter Register

Address
0xBF880040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBC31:0

CFD1TSCONCAN Time Stamp Control Register

Address
0xBF880050
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSRES18Time Stamp Resolution bit
  • 0 At sample point of SOF
  • 1 At sample point of the bit following the FDF bit
TSEOF17Time Stamp EOF bit
  • 0 Time Stamp at beginning of Frame (classical frame) at sample point of SOF / FD frame: see the TSRES bit
  • 1 Time Stamp when frame is taken valid (11898-1 10.7)
TBCEN16Time Base Counter Enable bit
  • 0 Stop and reset TBC
  • 1 Enable TBC
TBCPRE9:0CAN Time Base Counter Prescaler bits
  • 0 TBC increments every 1 SYSCLK clock cycle
  • 511 TBC increments every 1024 SYSCLK clock cycles

CFD1VECInterrupt Code Register

Address
0xBF880060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
RXCODE30:24Receive Interrupt Flag Code bits
  • 0 Reserved. FIFO 0 cant receive.
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
TXCODE22:16Transmit Interrupt Flag Code bits
  • 0 FIFO 0 Interrupt
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
FILHIT12:8Filter Hit Number bits
  • 0 Filter 0
  • 1 Filter 1
  • 2 Filter 2
  • 3 Filter 3
  • 4 Filter 4
  • 5 Filter 5
  • 6 Filter 6
  • 7 Filter 7
  • 8 Filter 8
  • 9 Filter 9
  • 10 Filter 10
  • 11 Filter 11
  • 12 Filter 12
  • 13 Filter 13
  • 14 Filter 14
  • 15 Filter 15
  • 16 Filter 16
  • 17 Filter 17
  • 18 Filter 18
  • 19 Filter 19
  • 20 Filter 20
  • 21 Filter 21
  • 22 Filter 22
  • 23 Filter 23
  • 24 Filter 24
  • 25 Filter 25
  • 26 Filter 26
  • 27 Filter 27
  • 28 Filter 28
  • 29 Filter 29
  • 30 Filter 30
  • 31 Filter 31
ICODE6:0Interrupt Flag Code bits
  • 0 FIFO 0 interrupt (TFIF0 set)
  • 1 FIFO 1 interrupt (TFIF1 or RFIF1 set)
  • 2 FIFO 2 interrupt (TFIF2 or RFIF2 set)
  • 3 FIFO 3 interrupt (TFIF3 or RFIF3 set)
  • 4 FIFO 4 interrupt (TFIF4 or RFIF4 set)
  • 5 FIFO 5 interrupt (TFIF5 or RFIF5 set)
  • 6 FIFO 6 interrupt (TFIF6 or RFIF6 set)
  • 7 FIFO 7 interrupt (TFIF7 or RFIF7 set)
  • 8 FIFO 8 interrupt (TFIF8 or RFIF8 set)
  • 9 FIFO 9 interrupt (TFIF9 or RFIF9 set)
  • 10 FIFO 10 interrupt (TFIF10 or RFIF10 set)
  • 11 FIFO 11 interrupt (TFIF11 or RFIF11 set)
  • 12 FIFO 12 interrupt (TFIF12 or RFIF12 set)
  • 13 FIFO 13 interrupt (TFIF13 or RFIF13 set)
  • 14 FIFO 14 interrupt (TFIF14 or RFIF14 set)
  • 15 FIFO 15 interrupt (TFIF15 or RFIF15 set)
  • 16 FIFO 16 interrupt (TFIF16 or RFIF16 set)
  • 17 FIFO 17 interrupt (TFIF17 or RFIF17 set)
  • 18 FIFO 18 interrupt (TFIF18 or RFIF18 set)
  • 19 FIFO 19 interrupt (TFIF19 or RFIF19 set)
  • 20 FIFO 20 interrupt (TFIF20 or RFIF20 set)
  • 21 FIFO 21 interrupt (TFIF21 or RFIF21 set)
  • 22 FIFO 22 interrupt (TFIF22 or RFIF22 set)
  • 23 FIFO 23 interrupt (TFIF23 or RFIF23 set)
  • 24 FIFO 24 interrupt (TFIF24 or RFIF24 set)
  • 25 FIFO 25 interrupt (TFIF25 or RFIF25 set)
  • 26 FIFO 26 interrupt (TFIF26 or RFIF26 set)
  • 27 FIFO 27 interrupt (TFIF27 or RFIF27 set)
  • 28 FIFO 28 interrupt (TFIF28 or RFIF28 set)
  • 29 FIFO 29 interrupt (TFIF29 or RFIF29 set)
  • 30 FIFO 30 interrupt (TFIF30 or RFIF30 set)
  • 31 FIFO 31 interrupt (TFIF31 or RFIF31 set)
  • 64 No interrupt
  • 65 Error interrupt (CERRIF/IE)
  • 66 Wake-up interrupt (WAKIF/WAKIE)
  • 67 Receive FIFO overflow interrupt (any bit in CFDxRXOVIF set)
  • 68 Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
  • 69 RX/TX MAB overflow/underflow (RX: message received before previous message was saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE)
  • 70 CAN Timer Overflow (CTMRIF/IE)
  • 71 CAN module mode change Occurred (MODIF/IE)
  • 72 Invalid message occurred (IVMIF/IE)
  • 73 Transmit event FIFO interrupt (any bit in the CFDxTEFIF register is set)
  • 74 Transmit attempt interrupt (any bit in the CFDxTXATIF register is set)

CFD1INTInterrupt Register

Address
0xBF880070
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
WAKIE30Bus Wake Up Activity Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
CERRIE29CAN Bus Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SERRIE28System Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXOVIE27Receive Buffer Overflow Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXATIE26Transmit Attempt Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TEFIE20Transmit Event FIFO Interrupt Enable bit
  • 1 Interrupts are enabled
MODIE19Mode Change Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TBCIE18CAN Timer Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXIE17Receive Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXIE16Transmit Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
IVMIF15Invalid Message Interrupt Flag bit
  • 0 No invalid message interrupts are pending
  • 1 An invalid message interrupt is pending
WAKIF14Bus Wake Up Activity Interrupt Flag bit
  • 0 No wake-up interrupts are pending
  • 1 A wake-up interrupt is pending
CERRIF13CAN Bus Error Interrupt Flag bit
  • 0 No CAN bus error interrupts are pending
  • 1 A CAN bus error interrupt is pending
SERRIF12System Error Interrupt Flag bit
  • 0 No system error occurred
  • 1 A system error occurred (collision on dual-port RAM)
RXOVIF11Receive Object Overflow Interrupt Flag bit
  • 0 No receive object overflow has occurred
  • 1 Receive object overflow occurred
TXATIF10Transmit Attempt Interrupt Flag bit
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set
TEFIF4Transmit Event FIFO Interrupt Flag bit
  • 0 No receive buffer overflow has occurred
  • 1 Receive buffer overflow occurred
MODIF3CAN Mode Change Interrupt Flag bit
  • 0 No mode change occurred
  • 1 CAN module mode change occurred (OPMOD has changed to reflect the REQOP bits)
TBCIF2CAN Timer Overflow Interrupt Flag bit
  • 0 TBC did not overflow
  • 1 TBC has overflowed
RXIF1Receive Object Interrupt Flag bit
  • 0 No receive object interrupts pending
  • 1 Receive object interrupt pending
TXIF0Transmit Object Interrupt Flag bit
  • 0 No transmit object interrupts pending
  • 1 Transmit object interrupt pending
IVMIE31Invalid Message Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled

CFD1RXIFReceive Interrupt Status Register

Address
0xBF880080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFIF31:1Receive FIFO Interrupt Pending bits
  • 0 No enabled receive FIFO interrupts are pending
  • 1 One or more enabled receive FIFO interrupts are pending

CFD1TXIFTransmit Interrupt Status Register

Address
0xBF880090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFIF31:0Transmit FIFO/Transmit Queue Interrupt Pending bits
  • 0 No enabled transmit FIFO/Transmit Queue interrupt are pending
  • 1 One or more enabled transmit FIFO/Transmit Queue interrupts are pending

CFD1RXOVIFReceive Overflow Interrupt Status Register

Address
0xBF8800A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFOVIF31:1Receive FIFO Overflow Interrupt Pending bits
  • 0 Interrupt not pending
  • 1 Interrupt is pending

CFD1TXATIFTransmit Attempt Interrupt Status Register

Address
0xBF8800B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFATIF31:0Transmit FIFO/Transmit Queue Attempt Interrupt Pending bits
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set

CFD1TXREQTransmit Request Register

Address
0xBF8800C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXREQ31:0

CFD1TRECTransmit/Receive Error Count Register

Address
0xBF8800D0
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
TXBO21Transmitter in Error State Bus Off bit (TERRCNT > 255)
  • 0 Indicates that transmit errors are less than 255
  • 1 Indicates that the number of transmit errors is greater than 255.
TXBP20Transmitter in Error State Bus Passive bit (TERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of transmit errors is greater than 127.
RXBP19Receiver in Error State Bus Passive bit (RERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of receive errors is greater than 127.
TXWARN18Transmitter in Error State Warning bit (128 > TERRCNT > 95)
  • 0 Indicates that transmit errors are greater than or equal to 95
  • 1 Indicates that the number of transmit errors are less than 128
RXWARN17Receiver in Error State Warning bit (128 > RERRCNT > 95)
  • 0 Indicates that receive errors are greater than or equal to 95
  • 1 Indicates that the number of receives errors is less than 128
EWARN16Transmitter or Receiver is in Error State Warning bit
  • 0 No transmit or receive warnings
  • 1 TXWARN or RXWARN is set
TERRCNT15:8Transmit Error Counter bits
  • 0 No transmit errors
  • 1 1 transmit error
  • 254 254 Transmit errors
  • 255 Greater than or equal to 255 Transmit errors.
RERRCNT7:0Receive Error Counter bits
  • 0 No receive errors
  • 1 1 receive error
  • 254 254 receive errors
  • 255 Greater than or equal to 255 Receive errors

CFD1BDIAG0Bus Diagnostics Register 0

Address
0xBF8800E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DRERRCNT23:16
NTERRCNT15:8
NRERRCNT7:0
DTERRCNT31:24

CFD1BDIAG1Bus Diagnostics Register

Address
0xBF8800F0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
ESI30Error State Indicator (ESI) Flag Status bit
  • 0 ESI flag of a received CAN FD message was not set
  • 1 ESI flag of a received CAN FD message was set
DCRCERR29Data CRC Error Status bit
  • 0 No received message data CRC error occurred
  • 1 CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
DSTUFERR28Data Stuffing Error Status bit
  • 0 No data received message errors
  • 1 More than five equal bits in a sequence have occurred in a portion of a received message where this is not allowed
DFORMERR27Data Format Error Status bit
  • 0 No format errors occurred
  • 1 Data fixed format portion of a received frame has the wrong format
DBIT1ERR25Data Bit Logical 1 Error Status bit
  • 0 No data logical 1 bit transmission error occurred
  • 1 During the data transmission of a message (with the exception of the arbitration field)
DBIT0ERR24Data Bit Logical 0 Error Status bit
  • 0 No data logical 0 bit transmission error occurred
  • 1 During the data transmission of a message the monitored bus value was recessive. During Bus Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored.
NCRCERR21Nominal CRC Error Status bit
  • 0 No nominal CRC received message error occurred
  • 1 The CRC checksum of a nominal received message was incorrect.
NSTUFERR20Nominal Stuffing Error Status bit
  • 0 No nominal bit stuffing errors have occurred
  • 1 More than five equal bits in a sequence have occurred in a part of a nominal received message where this is not allowed
NFORMERR19Nominal Format Error Status bit
  • 0 No nominal format error occurred
  • 1 A fixed format portion of a nominal received frame has the wrong format
NACKERR18Not Acknowledged Error Status bit
  • 0 A transmitted message was acknowledged
  • 1 A transmitted message was not acknowledged
NBIT1ERR17Nominal Bit Logical 1 Error Status bit
  • 0 No nominal bit logical 1 error occurred
  • 1 During the transmission of a nominal message (with the exception of the arbitration field)
NBIT0ERR16Nominal Bit Logical 0 Error Status bit
  • 0 No nominal bit logical 0 error occurred
  • 1 During the transmission of a nominal message
EFMSGCNT15:0Error Free Message Counter Status bits
  • 0 0 error free messages since the last register read
  • 65535 65536 error free messages since the last register read
DLCMM31Data Length Code (DLC) Mismatch Status bit
  • 0 No payload size error occurred
  • 1 Payload size error. During a transmission or reception the Data Length Code exceeds the payload size of the FIFO element defined in the PLSIZE bits (CFDxFIFOCONn).

CFD1TEFCONTransmit Event FIFO Control Register

Address
0xBF880100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 message deep
  • 1 FIFO is 2 messages deep
  • 2 FIFO is 3 messages deep
  • 3 FIFO is 4 messages deep
  • 4 FIFO is 5 messages deep
  • 5 FIFO is 6 messages deep
  • 6 FIFO is 7 messages deep
  • 7 FIFO is 8 messages deep
  • 8 FIFO is 9 messages deep
  • 9 FIFO is 10 messages deep
  • 10 FIFO is 11 messages deep
  • 11 FIFO is 12 messages deep
  • 12 FIFO is 13 messages deep
  • 13 FIFO is 14 messages deep
  • 14 FIFO is 15 messages deep
  • 15 FIFO is 16 messages deep
  • 16 FIFO is 17 messages deep
  • 17 FIFO is 18 messages deep
  • 18 FIFO is 19 messages deep
  • 19 FIFO is 20 messages deep
  • 20 FIFO is 21 messages deep
  • 21 FIFO is 22 messages deep
  • 22 FIFO is 23 messages deep
  • 23 FIFO is 24 messages deep
  • 24 FIFO is 25 messages deep
  • 25 FIFO is 26 messages deep
  • 26 FIFO is 27 messages deep
  • 27 FIFO is 28 messages deep
  • 28 FIFO is 29 messages deep
  • 29 FIFO is 30 messages deep
  • 30 FIFO is 31 messages deep
  • 31 FIFO is 32 messages deep
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set
UINC8
TEFTSEN5Transmit Event FIFO Time Stamp Enable bit
  • 0 Do not time stamp elements in TEF
  • 1 Time stamp elements in TEF
TEFOVIE3Transmit Event FIFO Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TEFFIE2Transmit Event FIFO Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO full
  • 1 Interrupt enabled for FIFO full
TEFHIE1Transmit Event FIFO Half Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO half full
  • 1 Interrupt enabled for FIFO half full
TEFNEIE0Transmit Event FIFO Not Empty Interrupt Enable bit
  • 0 Interrupt disabled for FIFO not empty
  • 1 Interrupt enabled for FIFO not empty

CFD1TEFSTATransmit Event FIFO Status Register

Address
0xBF880110
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TEFOVIF3Transmit Event FIFO Overflow Interrupt Flag bit
  • 0 No overflow event has occurred
  • 1 Overflow event has occurred
TEFFIF2Transmit Event FIFO Full Interrupt Flag bit
  • 0 FIFO is not full
  • 1 FIFO is full
TEFHIF1Transmit Event FIFO Half Full Interrupt Flag bit
  • 0 FIFO is less than half full
  • 1 FIFO is greater than or equal to half full
TEFNEIF0Transmit Event FIFO Not Empty Interrupt Flag bit
  • 0 FIFO is empty
  • 1 FIFO is not empty (has at least one message)

CFD1TEFUATransmit Event FIFO User Address Register

Address
0xBF880120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TEFUA31:0

CFD1FIFOBAMessage Memory Base Address Register

Address
0xBF880130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOBA31:0

CFD1TXQCONTransmit Queue Control Register

Address
0xBF880140
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. The user application should poll whether this bit is clear before taking any action.
TXREQ9Message Send Request bit
  • 0 Clearing the bit to 0 while set will request a message abort.
  • 1 Requests sending a message; the bit will automatically clear when all the messages queued in the Transmit Queue are successfully sent
UINC8Increment Head/Tail bit
  • 0 FIFO head will not increment by a single message
  • 1 FIFO head will increment by a single message
TXEN7TX Enable
  • 1 Transmit Message Queue. This bit always reads as 1.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
TXQEIE2Transmit Queue Empty Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue empty
  • 1 Interrupt enabled for Transmit Queue empty
TXQNIE0Transmit Queue Not Full Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue not full
  • 1 Interrupt enabled for Transmit Queue not full
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1TXQSTATransmit Queue Status Register

Address
0xBF880150
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
TXQCI12:8
TXABT7Message Aborted Status bit
  • 0 Message completed successfully
  • 1 Message was aborted
TXLARB6Message Lost Arbitration Status bit
  • 0 Message did not loose arbitration while being sent
  • 1 Message lost arbitration while being sent
TXERR5Error Detected During Transmission bit
  • 0 A bus error did not occur while the message was being sent
  • 1 A bus error occurred while the message was being sent
TXATIF4Transmit Attempts Exhausted Interrupt Pending bit
  • 0 Interrupt Not pending
  • 1 Interrupt pending
TXQEIF2Transmit Queue Empty Interrupt Flag bit
  • 0 Transmit Queue is not empty
  • 1 Transmit Queue is empty
TXQNIF0Transmit Queue Not Full Interrupt Flag bit
  • 0 Transmit Queue is full
  • 1 Transmit Queue is not full

CFD1TXQUATransmit Queue User Address Register

Address
0xBF880160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXQUA31:0

CFD1FIFOCON1FIFO Control Registe

Address
0xBF880170
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA1

Address
0xBF880180
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA1

Address
0xBF880190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON2FIFO Control Register

Address
0xBF8801A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA2

Address
0xBF8801B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA2

Address
0xBF8801C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON3FIFO Control Register

Address
0xBF8801D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA3

Address
0xBF8801E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA3

Address
0xBF8801F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON4FIFO Control Register

Address
0xBF880200
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA4

Address
0xBF880210
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA4

Address
0xBF880220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON5FIFO Control Register

Address
0xBF880230
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA5

Address
0xBF880240
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA5

Address
0xBF880250
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON6FIFO Control Register

Address
0xBF880260
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA6

Address
0xBF880270
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA6

Address
0xBF880280
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON7FIFO Control Register

Address
0xBF880290
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA7

Address
0xBF8802A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA7

Address
0xBF8802B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON8FIFO Control Register

Address
0xBF8802C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA8

Address
0xBF8802D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA8

Address
0xBF8802E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON9FIFO Control Register

Address
0xBF8802F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA9

Address
0xBF880300
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA9

Address
0xBF880310
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON10FIFO Control Register

Address
0xBF880320
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA10

Address
0xBF880330
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA10

Address
0xBF880340
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON11FIFO Control Registe

Address
0xBF880350
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA11

Address
0xBF880360
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA11

Address
0xBF880370
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON12FIFO Control Register

Address
0xBF880380
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA12

Address
0xBF880390
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA12

Address
0xBF8803A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON13FIFO Control Register

Address
0xBF8803B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA13

Address
0xBF8803C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA13

Address
0xBF8803D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON14FIFO Control Register

Address
0xBF8803E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA14

Address
0xBF8803F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA14

Address
0xBF880400
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON15FIFO Control Register

Address
0xBF880410
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA15

Address
0xBF880420
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA15

Address
0xBF880430
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON16FIFO Control Register

Address
0xBF880440
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA16

Address
0xBF880450
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA16

Address
0xBF880460
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON17FIFO Control Register

Address
0xBF880470
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA17

Address
0xBF880480
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA17

Address
0xBF880490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON18FIFO Control Register

Address
0xBF8804A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA18

Address
0xBF8804B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA18

Address
0xBF8804C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON19FIFO Control Register

Address
0xBF8804D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA19

Address
0xBF8804E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA19

Address
0xBF8804F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON20FIFO Control Register

Address
0xBF880500
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA20

Address
0xBF880510
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA20

Address
0xBF880520
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON21FIFO Control Registe

Address
0xBF880530
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA21

Address
0xBF880540
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA21

Address
0xBF880550
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON22FIFO Control Register

Address
0xBF880560
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA22

Address
0xBF880570
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA22

Address
0xBF880580
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON23FIFO Control Register

Address
0xBF880590
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA23

Address
0xBF8805A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA23

Address
0xBF8805B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON24FIFO Control Register

Address
0xBF8805C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA24

Address
0xBF8805D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA24

Address
0xBF8805E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON25FIFO Control Register

Address
0xBF8805F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA25

Address
0xBF880600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA25

Address
0xBF880610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON26FIFO Control Register

Address
0xBF880620
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA26

Address
0xBF880630
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA26

Address
0xBF880640
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON27FIFO Control Register

Address
0xBF880650
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA27

Address
0xBF880660
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA27

Address
0xBF880670
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON28FIFO Control Register

Address
0xBF880680
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA28

Address
0xBF880690
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA28

Address
0xBF8806A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON29FIFO Control Register

Address
0xBF8806B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA29

Address
0xBF8806C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA29

Address
0xBF8806D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON30FIFO Control Register

Address
0xBF8806E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA30

Address
0xBF8806F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA30

Address
0xBF880700
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FIFOCON31FIFO Control Registe

Address
0xBF880710
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD1FIFOSTA31

Address
0xBF880720
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD1FIFOUA31

Address
0xBF880730
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD1FLTCON0Filter Control Register

Address
0xBF880740
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F3BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F2BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F1BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN07Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F0BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the RX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON1Filter Control Registe

Address
0xBF880750
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F7BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F6BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F5BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN47Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F4BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON2Filter Control Register

Address
0xBF880760
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F11BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1023Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F10BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F9BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN87Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F8BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON3Filter Control Register

Address
0xBF880770
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F15BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1423Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F14BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1315Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F13BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN127Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F12BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1531Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON4Filter Control Register

Address
0xBF880780
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F19BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1823Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F18BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1715Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F17BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN167Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F16BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1931Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON5Filter Control Register

Address
0xBF880790
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F23BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F22BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F21BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN207Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F20BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON6Filter Control Register

Address
0xBF8807A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F27BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F26BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F25BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN247Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F24BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTCON7Filter Control Register

Address
0xBF8807B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F31BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3023Enable Filter nto Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F30BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F29BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN287Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F28BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD1FLTOBJ0

Address
0xBF8807C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit
EID28:11
SID10:0

CFD1MASK0

Address
0xBF8807D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ1Filter Object Registe

Address
0xBF8807E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK1Filter Object Registe

Address
0xBF8807F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ2Filter Object Register

Address
0xBF880800
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK2

Address
0xBF880810
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ3Filter Object Register

Address
0xBF880820
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK3

Address
0xBF880830
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ4Filter Object Register

Address
0xBF880840
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK4Filter Object Register

Address
0xBF880850
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ5Filter Object Register

Address
0xBF880860
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK5Filter Object Register

Address
0xBF880870
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ6Filter Object Register

Address
0xBF880880
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK6Filter Object Register

Address
0xBF880890
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ7Filter Object Register

Address
0xBF8808A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK7Filter Object Register

Address
0xBF8808B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ8Filter Object Register

Address
0xBF8808C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK8Filter Object Register

Address
0xBF8808D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ9Filter Object Register

Address
0xBF8808E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK9Filter Object Register

Address
0xBF8808F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ10Filter Object Register

Address
0xBF880900
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK10Filter Object Register

Address
0xBF880910
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ11Filter Object Registe

Address
0xBF880920
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK11Filter Object Registe

Address
0xBF880930
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ12Filter Object Register

Address
0xBF880940
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK12Filter Object Register

Address
0xBF880950
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ13Filter Object Register

Address
0xBF880960
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK13Filter Object Register

Address
0xBF880970
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ14Filter Object Register

Address
0xBF880980
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK14Filter Object Register

Address
0xBF880990
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ15Filter Object Register

Address
0xBF8809A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK15Filter Object Register

Address
0xBF8809B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ16Filter Object Register

Address
0xBF8809C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD1MASK16Filter Object Register

Address
0xBF8809D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ17Filter Object Register

Address
0xBF8809E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK17Filter Object Register

Address
0xBF8809F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ18Filter Object Register

Address
0xBF880A00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK18Filter Object Register

Address
0xBF880A10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ19Filter Object Register

Address
0xBF880A20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK19Filter Object Register

Address
0xBF880A30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ20Filter Object Register

Address
0xBF880A40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK20Filter Object Register

Address
0xBF880A50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ22Filter Object Register

Address
0xBF880A80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK22Filter Object Register

Address
0xBF880A90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ23Filter Object Register

Address
0xBF880AA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK23Filter Object Register

Address
0xBF880AB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ24Filter Object Register

Address
0xBF880AC0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK24Filter Object Register

Address
0xBF880AD0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ25Filter Object Register

Address
0xBF880AE0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK25Filter Object Register

Address
0xBF880AF0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ26Filter Object Register

Address
0xBF880B00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK26Filter Object Register

Address
0xBF880B10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ27Filter Object Register

Address
0xBF880B20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK27Filter Object Register

Address
0xBF880B30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ28Filter Object Register

Address
0xBF880B40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK28Filter Object Register

Address
0xBF880B50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ29Filter Object Register

Address
0xBF880B60
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK29Filter Object Register

Address
0xBF880B70
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ30Filter Object Register

Address
0xBF880B80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK30Filter Object Register

Address
0xBF880B90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD1FLTOBJ31Filter Object Register

Address
0xBF880BA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD1MASK31Filter Object Register

Address
0xBF880BB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2CONCAN Control Register

Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
ABAT27Abort All Pending Transmissions bit
  • 0 Module will clear this bit when all transmissions aborted
  • 1 Signal all transmit buffers to abort transmission
REQOP26:24Request Operation Mode bits
  • 0 Set Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Set Disable mode
  • 2 Set Internal Loopback mode
  • 3 Set Listen Only mode
  • 4 Set Configuration mode
  • 5 Set External Loopback mode
  • 6 Set Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Set Restricted Operation mode
OPMOD23:21Operation Mode Status bits
  • 0 Module is in Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Module is in Disable mode
  • 2 Module is in Internal Loopback mode
  • 3 Module is in Listen Only mode
  • 4 Module is in Configuration mode
  • 5 Module is in External Loopback mode
  • 6 Module is Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Module is Restricted Operation mode
TXQEN20Enable Transmit Queue bit
  • 0 Dont reserve space in RAM for Transmit Queue
  • 1 Enables Transmit Queue and reserves space in RAM
STEF19Store in Transmit Event FIFO bit
  • 0 Dont save transmitted messages in TEF
  • 1 Save transmitted messages in TEF
SERR2LOM18Transition to Listen Only Mode on System Error bit
  • 0 Transition to Restricted Operation Mode
  • 1 Transition to Listen Only Mode
ESIGM17Transmit ESI in Gateway Mode bit
  • 0 ESI reflects error status of CAN controller
  • 1 ESI is transmitted as recessive when ESI of message is high or CAN controller error passive
RTXAT16Restrict Retransmission Attempts bit
  • 0 Unlimited number of retransmission attempts
  • 1 Restricted retransmission attempts
ON15Enable bit
  • 0 CAN module is disabled
  • 1 CAN module is enabled
SIDL13Stop-in-Idle Control bit
  • 0 Dont stop module operation in Idle mode
  • 1 Stop module operation in Idle mode
BRSDIS12Bit Rate Switching Disable bit
  • 0 Bit Rate Switching depends on BRS in the Transmit Message Object
  • 1 Bit Rate Switching is Disabled
BUSY11CAN Module is Busy bit
  • 0 The CAN module is inactive
  • 1 The CAN module is active
WFT10:9Selectable Wake-up Filter Time bits
  • 0 T00FILTER (Typical 100 ns)
  • 1 T01FILTER (Typical 187 ns)
  • 2 T10FILTER (Typical 375 ns)
  • 3 T11FILTER (Typical 600 ns)
WAKFIL8Enable CAN Bus Line Wake-up Filter bit
  • 0 CAN bus line filter is not used for wake-up
  • 1 Use CAN bus line filter for wake-up
CLKSEL07Module Clock Source Select bit
  • 0 SYSCLK is active when the CAN FD module is enabled
  • 1 REFCLK4 is active when the CAN FD module is enabled
PXEDIS6Protocol Exception Event Detection Disabled bit
  • 0 If a Protocol Exception is detected
  • 1 Protocol Exception is treated as a Form Error.
ISOCRCEN5Enable ISO CRC in CAN FD Frames bit
  • 0 Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros
  • 1 Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector
DNCNT4:0Device Net Filter Bit Number bits
TXBWS31:28Transmit Bandwidth Sharing bits
  • 0 No delay
  • 1 2
  • 2 4
  • 3 8
  • 4 16
  • 5 32
  • 6 64
  • 7 128
  • 8 256
  • 9 512
  • 10 1024
  • 11 2048
  • 12 4096

CFD2NBTCFGNominal Bit Time Configuration Register

Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG123:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 255 Length is 256 x Tq
TSEG214:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 31 Length is 128 x Tq
SJW6:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 127 Length is 128 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq = 1/Fsys
  • 255 Tq = 256/Fsys

CFD2DBTCFGData Bit Time Configuration Register

Address
0xBF881020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG120:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
  • 16 Length is 17 x Tq
  • 17 Length is 18 x Tq
  • 18 Length is 19 x Tq
  • 19 Length is 20 x Tq
  • 20 Length is 21 x Tq
  • 21 Length is 22 x Tq
  • 22 Length is 23 x Tq
  • 23 Length is 24 x Tq
  • 24 Length is 25 x Tq
  • 25 Length is 26 x Tq
  • 26 Length is 27 x Tq
  • 27 Length is 28 x Tq
  • 28 Length is 29 x Tq
  • 29 Length is 30 x Tq
  • 30 Length is 31 x Tq
  • 31 Length is 32 x Tq
TSEG211:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
SJW3:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq is 1/Fsys
  • 255 Tq is 256/Fsys

CFD2TDCTransmitter Delay Compensation Register

Address
0xBF881030
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EDGFLTEN25Enable Edge Filtering during Bus Integration state bit
  • 0 Edge Filtering disabled
  • 1 Edge Filtering enabled
SID11EN24Enable 12-Bit SID in CAN FD Base Format Messages bit
  • 0 Do not use RRS; SID(10-0) according to ISO11898-1 2015
  • 1 RRS is used as SID11 in CAN FD base format messages: SID(11-0) = {SID(10-0)
TDCMOD17:16Transmitter Delay Compensation Mode bits
  • 0 Disable
  • 1 Manual; Do not measure use TDCV plus TDCO from the register
  • 2 Auto; measure delay and add CFDxDBTCFG.TSEG1; add TDCO
TDCO14:8Transmitter Delay Compensation Offset bits
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK
TDCV5:0Transmitter Delay Compensation Value bits; Secondary Sample Point
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK

CFD2TBCCAN Time Base Counter Register

Address
0xBF881040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBC31:0

CFD2TSCONCAN Time Stamp Control Register

Address
0xBF881050
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSRES18Time Stamp Resolution bit
  • 0 At sample point of SOF
  • 1 At sample point of the bit following the FDF bit
TSEOF17Time Stamp EOF bit
  • 0 Time Stamp at beginning of Frame (classical frame) at sample point of SOF / FD frame: see the TSRES bit
  • 1 Time Stamp when frame is taken valid (11898-1 10.7)
TBCEN16Time Base Counter Enable bit
  • 0 Stop and reset TBC
  • 1 Enable TBC
TBCPRE9:0CAN Time Base Counter Prescaler bits
  • 0 TBC increments every 1 SYSCLK clock cycle
  • 511 TBC increments every 1024 SYSCLK clock cycles

CFD2VECInterrupt Code Register

Address
0xBF881060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
RXCODE30:24Receive Interrupt Flag Code bits
  • 0 Reserved. FIFO 0 cant receive.
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
TXCODE22:16Transmit Interrupt Flag Code bits
  • 0 FIFO 0 Interrupt
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
FILHIT12:8Filter Hit Number bits
  • 0 Filter 0
  • 1 Filter 1
  • 2 Filter 2
  • 3 Filter 3
  • 4 Filter 4
  • 5 Filter 5
  • 6 Filter 6
  • 7 Filter 7
  • 8 Filter 8
  • 9 Filter 9
  • 10 Filter 10
  • 11 Filter 11
  • 12 Filter 12
  • 13 Filter 13
  • 14 Filter 14
  • 15 Filter 15
  • 16 Filter 16
  • 17 Filter 17
  • 18 Filter 18
  • 19 Filter 19
  • 20 Filter 20
  • 21 Filter 21
  • 22 Filter 22
  • 23 Filter 23
  • 24 Filter 24
  • 25 Filter 25
  • 26 Filter 26
  • 27 Filter 27
  • 28 Filter 28
  • 29 Filter 29
  • 30 Filter 30
  • 31 Filter 31
ICODE6:0Interrupt Flag Code bits
  • 0 FIFO 0 interrupt (TFIF0 set)
  • 1 FIFO 1 interrupt (TFIF1 or RFIF1 set)
  • 2 FIFO 2 interrupt (TFIF2 or RFIF2 set)
  • 3 FIFO 3 interrupt (TFIF3 or RFIF3 set)
  • 4 FIFO 4 interrupt (TFIF4 or RFIF4 set)
  • 5 FIFO 5 interrupt (TFIF5 or RFIF5 set)
  • 6 FIFO 6 interrupt (TFIF6 or RFIF6 set)
  • 7 FIFO 7 interrupt (TFIF7 or RFIF7 set)
  • 8 FIFO 8 interrupt (TFIF8 or RFIF8 set)
  • 9 FIFO 9 interrupt (TFIF9 or RFIF9 set)
  • 10 FIFO 10 interrupt (TFIF10 or RFIF10 set)
  • 11 FIFO 11 interrupt (TFIF11 or RFIF11 set)
  • 12 FIFO 12 interrupt (TFIF12 or RFIF12 set)
  • 13 FIFO 13 interrupt (TFIF13 or RFIF13 set)
  • 14 FIFO 14 interrupt (TFIF14 or RFIF14 set)
  • 15 FIFO 15 interrupt (TFIF15 or RFIF15 set)
  • 16 FIFO 16 interrupt (TFIF16 or RFIF16 set)
  • 17 FIFO 17 interrupt (TFIF17 or RFIF17 set)
  • 18 FIFO 18 interrupt (TFIF18 or RFIF18 set)
  • 19 FIFO 19 interrupt (TFIF19 or RFIF19 set)
  • 20 FIFO 20 interrupt (TFIF20 or RFIF20 set)
  • 21 FIFO 21 interrupt (TFIF21 or RFIF21 set)
  • 22 FIFO 22 interrupt (TFIF22 or RFIF22 set)
  • 23 FIFO 23 interrupt (TFIF23 or RFIF23 set)
  • 24 FIFO 24 interrupt (TFIF24 or RFIF24 set)
  • 25 FIFO 25 interrupt (TFIF25 or RFIF25 set)
  • 26 FIFO 26 interrupt (TFIF26 or RFIF26 set)
  • 27 FIFO 27 interrupt (TFIF27 or RFIF27 set)
  • 28 FIFO 28 interrupt (TFIF28 or RFIF28 set)
  • 29 FIFO 29 interrupt (TFIF29 or RFIF29 set)
  • 30 FIFO 30 interrupt (TFIF30 or RFIF30 set)
  • 31 FIFO 31 interrupt (TFIF31 or RFIF31 set)
  • 64 No interrupt
  • 65 Error interrupt (CERRIF/IE)
  • 66 Wake-up interrupt (WAKIF/WAKIE)
  • 67 Receive FIFO overflow interrupt (any bit in CFDxRXOVIF set)
  • 68 Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
  • 69 RX/TX MAB overflow/underflow (RX: message received before previous message was saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE)
  • 70 CAN Timer Overflow (CTMRIF/IE)
  • 71 CAN module mode change Occurred (MODIF/IE)
  • 72 Invalid message occurred (IVMIF/IE)
  • 73 Transmit event FIFO interrupt (any bit in the CFDxTEFIF register is set)
  • 74 Transmit attempt interrupt (any bit in the CFDxTXATIF register is set)

CFD2INTInterrupt Register

Address
0xBF881070
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
FieldBitsWhat it does
WAKIE30Bus Wake Up Activity Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
CERRIE29CAN Bus Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SERRIE28System Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXOVIE27Receive Buffer Overflow Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXATIE26Transmit Attempt Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SPICRCIE25
ECCIE24
TEFIE20Transmit Event FIFO Interrupt Enable bit
  • 1 Interrupts are enabled
MODIE19Mode Change Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TBCIE18CAN Timer Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXIE17Receive Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXIE16Transmit Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
IVMIF15Invalid Message Interrupt Flag bit
  • 0 No invalid message interrupts are pending
  • 1 An invalid message interrupt is pending
WAKIF14Bus Wake Up Activity Interrupt Flag bit
  • 0 No wake-up interrupts are pending
  • 1 A wake-up interrupt is pending
CERRIF13CAN Bus Error Interrupt Flag bit
  • 0 No CAN bus error interrupts are pending
  • 1 A CAN bus error interrupt is pending
SERRIF12System Error Interrupt Flag bit
  • 0 No system error occurred
  • 1 A system error occurred (collision on dual-port RAM)
RXOVIF11Receive Object Overflow Interrupt Flag bit
  • 0 No receive object overflow has occurred
  • 1 Receive object overflow occurred
TXATIF10Transmit Attempt Interrupt Flag bit
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set
SPICRCIF9
ECCIF8
TEFIF4Transmit Event FIFO Interrupt Flag bit
  • 0 No receive buffer overflow has occurred
  • 1 Receive buffer overflow occurred
MODIF3CAN Mode Change Interrupt Flag bit
  • 0 No mode change occurred
  • 1 CAN module mode change occurred (OPMOD has changed to reflect the REQOP bits)
TBCIF2CAN Timer Overflow Interrupt Flag bit
  • 0 TBC did not overflow
  • 1 TBC has overflowed
RXIF1Receive Object Interrupt Flag bit
  • 0 No receive object interrupts pending
  • 1 Receive object interrupt pending
TXIF0Transmit Object Interrupt Flag bit
  • 0 No transmit object interrupts pending
  • 1 Transmit object interrupt pending
IVMIE31Invalid Message Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled

CFD2RXIFReceive Interrupt Status Register

Address
0xBF881080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFIF31:1Receive FIFO Interrupt Pending bits
  • 0 No enabled receive FIFO interrupts are pending
  • 1 One or more enabled receive FIFO interrupts are pending

CFD2TXIFTransmit Interrupt Status Register

Address
0xBF881090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFIF31:0Transmit FIFO/Transmit Queue Interrupt Pending bits
  • 0 No enabled transmit FIFO/Transmit Queue interrupt are pending
  • 1 One or more enabled transmit FIFO/Transmit Queue interrupts are pending

CFD2RXOVIFReceive Overflow Interrupt Status Register

Address
0xBF8810A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFOVIF31:1Receive FIFO Overflow Interrupt Pending bits
  • 0 Interrupt not pending
  • 1 Interrupt is pending

CFD2TXATIFTransmit Attempt Interrupt Status Register

Address
0xBF8810B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFATIF31:0Transmit FIFO/Transmit Queue Attempt Interrupt Pending bits
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set

CFD2TXREQTransmit Request Register

Address
0xBF8810C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXREQ31:0

CFD2TRECTransmit/Receive Error Count Register

Address
0xBF8810D0
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
TXBO21Transmitter in Error State Bus Off bit (TERRCNT > 255)
  • 0 Indicates that transmit errors are less than 255
  • 1 Indicates that the number of transmit errors is greater than 255.
TXBP20Transmitter in Error State Bus Passive bit (TERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of transmit errors is greater than 127.
RXBP19Receiver in Error State Bus Passive bit (RERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of receive errors is greater than 127.
TXWARN18Transmitter in Error State Warning bit (128 > TERRCNT > 95)
  • 0 Indicates that transmit errors are greater than or equal to 95
  • 1 Indicates that the number of transmit errors are less than 128
RXWARN17Receiver in Error State Warning bit (128 > RERRCNT > 95)
  • 0 Indicates that receive errors are greater than or equal to 95
  • 1 Indicates that the number of receives errors is less than 128
EWARN16Transmitter or Receiver is in Error State Warning bit
  • 0 No transmit or receive warnings
  • 1 TXWARN or RXWARN is set
TERRCNT15:8Transmit Error Counter bits
  • 0 No transmit errors
  • 1 1 transmit error
  • 254 254 Transmit errors
  • 255 Greater than or equal to 255 Transmit errors.
RERRCNT7:0Receive Error Counter bits
  • 0 No receive errors
  • 1 1 receive error
  • 254 254 receive errors
  • 255 Greater than or equal to 255 Receive errors

CFD2BDIAG0Bus Diagnostics Register 0

Address
0xBF8810E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DRERRCNT23:16
NTERRCNT15:8
NRERRCNT7:0
DTERRCNT31:24

CFD2BDIAG1Bus Diagnostics Register

Address
0xBF8810F0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
ESI30Error State Indicator (ESI) Flag Status bit
  • 0 ESI flag of a received CAN FD message was not set
  • 1 ESI flag of a received CAN FD message was set
DCRCERR29Data CRC Error Status bit
  • 0 No received message data CRC error occurred
  • 1 CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
DSTUFERR28Data Stuffing Error Status bit
  • 0 No data received message errors
  • 1 More than five equal bits in a sequence have occurred in a portion of a received message where this is not allowed
DFORMERR27Data Format Error Status bit
  • 0 No format errors occurred
  • 1 Data fixed format portion of a received frame has the wrong format
DBIT1ERR25Data Bit Logical 1 Error Status bit
  • 0 No data logical 1 bit transmission error occurred
  • 1 During the data transmission of a message (with the exception of the arbitration field)
DBIT0ERR24Data Bit Logical 0 Error Status bit
  • 0 No data logical 0 bit transmission error occurred
  • 1 During the data transmission of a message the monitored bus value was recessive. During Bus Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored.
NCRCERR21Nominal CRC Error Status bit
  • 0 No nominal CRC received message error occurred
  • 1 The CRC checksum of a nominal received message was incorrect.
NSTUFERR20Nominal Stuffing Error Status bit
  • 0 No nominal bit stuffing errors have occurred
  • 1 More than five equal bits in a sequence have occurred in a part of a nominal received message where this is not allowed
NFORMERR19Nominal Format Error Status bit
  • 0 No nominal format error occurred
  • 1 A fixed format portion of a nominal received frame has the wrong format
NACKERR18Not Acknowledged Error Status bit
  • 0 A transmitted message was acknowledged
  • 1 A transmitted message was not acknowledged
NBIT1ERR17Nominal Bit Logical 1 Error Status bit
  • 0 No nominal bit logical 1 error occurred
  • 1 During the transmission of a nominal message (with the exception of the arbitration field)
NBIT0ERR16Nominal Bit Logical 0 Error Status bit
  • 0 No nominal bit logical 0 error occurred
  • 1 During the transmission of a nominal message
EFMSGCNT15:0Error Free Message Counter Status bits
  • 0 0 error free messages since the last register read
  • 65535 65536 error free messages since the last register read
DLCMM31Data Length Code (DLC) Mismatch Status bit
  • 0 No payload size error occurred
  • 1 Payload size error. During a transmission or reception the Data Length Code exceeds the payload size of the FIFO element defined in the PLSIZE bits (CFDxFIFOCONn).

CFD2TEFCONTransmit Event FIFO Control Register

Address
0xBF881100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 message deep
  • 1 FIFO is 2 messages deep
  • 2 FIFO is 3 messages deep
  • 3 FIFO is 4 messages deep
  • 4 FIFO is 5 messages deep
  • 5 FIFO is 6 messages deep
  • 6 FIFO is 7 messages deep
  • 7 FIFO is 8 messages deep
  • 8 FIFO is 9 messages deep
  • 9 FIFO is 10 messages deep
  • 10 FIFO is 11 messages deep
  • 11 FIFO is 12 messages deep
  • 12 FIFO is 13 messages deep
  • 13 FIFO is 14 messages deep
  • 14 FIFO is 15 messages deep
  • 15 FIFO is 16 messages deep
  • 16 FIFO is 17 messages deep
  • 17 FIFO is 18 messages deep
  • 18 FIFO is 19 messages deep
  • 19 FIFO is 20 messages deep
  • 20 FIFO is 21 messages deep
  • 21 FIFO is 22 messages deep
  • 22 FIFO is 23 messages deep
  • 23 FIFO is 24 messages deep
  • 24 FIFO is 25 messages deep
  • 25 FIFO is 26 messages deep
  • 26 FIFO is 27 messages deep
  • 27 FIFO is 28 messages deep
  • 28 FIFO is 29 messages deep
  • 29 FIFO is 30 messages deep
  • 30 FIFO is 31 messages deep
  • 31 FIFO is 32 messages deep
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set
UINC8
TEFTSEN5Transmit Event FIFO Time Stamp Enable bit
  • 0 Do not time stamp elements in TEF
  • 1 Time stamp elements in TEF
TEFOVIE3Transmit Event FIFO Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TEFFIE2Transmit Event FIFO Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO full
  • 1 Interrupt enabled for FIFO full
TEFHIE1Transmit Event FIFO Half Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO half full
  • 1 Interrupt enabled for FIFO half full
TEFNEIE0Transmit Event FIFO Not Empty Interrupt Enable bit
  • 0 Interrupt disabled for FIFO not empty
  • 1 Interrupt enabled for FIFO not empty

CFD2TEFSTATransmit Event FIFO Status Register

Address
0xBF881110
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TEFOVIF3Transmit Event FIFO Overflow Interrupt Flag bit
  • 0 No overflow event has occurred
  • 1 Overflow event has occurred
TEFFIF2Transmit Event FIFO Full Interrupt Flag bit
  • 0 FIFO is not full
  • 1 FIFO is full
TEFHIF1Transmit Event FIFO Half Full Interrupt Flag bit
  • 0 FIFO is less than half full
  • 1 FIFO is greater than or equal to half full
TEFNEIF0Transmit Event FIFO Not Empty Interrupt Flag bit
  • 0 FIFO is empty
  • 1 FIFO is not empty (has at least one message)

CFD2TEFUATransmit Event FIFO User Address Register

Address
0xBF881120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TEFUA31:0

CFD2FIFOBAMessage Memory Base Address Register

Address
0xBF881130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOBA31:0

CFD2TXQCONTransmit Queue Control Register

Address
0xBF881140
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. The user application should poll whether this bit is clear before taking any action.
TXREQ9Message Send Request bit
  • 0 Clearing the bit to 0 while set will request a message abort.
  • 1 Requests sending a message; the bit will automatically clear when all the messages queued in the Transmit Queue are successfully sent
UINC8Increment Head/Tail bit
  • 0 FIFO head will not increment by a single message
  • 1 FIFO head will increment by a single message
TXEN7TX Enable
  • 1 Transmit Message Queue. This bit always reads as 1.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
TXQEIE2Transmit Queue Empty Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue empty
  • 1 Interrupt enabled for Transmit Queue empty
TXQNIE0Transmit Queue Not Full Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue not full
  • 1 Interrupt enabled for Transmit Queue not full
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2TXQSTATransmit Queue Status Register

Address
0xBF881150
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
TXQCI12:8
TXABT7Message Aborted Status bit
  • 0 Message completed successfully
  • 1 Message was aborted
TXLARB6Message Lost Arbitration Status bit
  • 0 Message did not loose arbitration while being sent
  • 1 Message lost arbitration while being sent
TXERR5Error Detected During Transmission bit
  • 0 A bus error did not occur while the message was being sent
  • 1 A bus error occurred while the message was being sent
TXATIF4Transmit Attempts Exhausted Interrupt Pending bit
  • 0 Interrupt Not pending
  • 1 Interrupt pending
TXQEIF2Transmit Queue Empty Interrupt Flag bit
  • 0 Transmit Queue is not empty
  • 1 Transmit Queue is empty
TXQNIF0Transmit Queue Not Full Interrupt Flag bit
  • 0 Transmit Queue is full
  • 1 Transmit Queue is not full

CFD2TXQUATransmit Queue User Address Register

Address
0xBF881160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXQUA31:0

CFD2FIFOCON1FIFO Control Registe

Address
0xBF881170
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA1

Address
0xBF881180
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA1

Address
0xBF881190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON2FIFO Control Register

Address
0xBF8811A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA2

Address
0xBF8811B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA2

Address
0xBF8811C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON3FIFO Control Register

Address
0xBF8811D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA3

Address
0xBF8811E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA3

Address
0xBF8811F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON4FIFO Control Register

Address
0xBF881200
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA4

Address
0xBF881210
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA4

Address
0xBF881220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON5FIFO Control Register

Address
0xBF881230
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA5

Address
0xBF881240
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA5

Address
0xBF881250
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON6FIFO Control Register

Address
0xBF881260
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA6

Address
0xBF881270
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA6

Address
0xBF881280
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON7FIFO Control Register

Address
0xBF881290
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA7

Address
0xBF8812A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA7

Address
0xBF8812B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON8FIFO Control Register

Address
0xBF8812C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA8

Address
0xBF8812D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA8

Address
0xBF8812E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON9FIFO Control Register

Address
0xBF8812F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA9

Address
0xBF881300
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA9

Address
0xBF881310
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON10FIFO Control Register

Address
0xBF881320
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA10

Address
0xBF881330
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA10

Address
0xBF881340
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON11FIFO Control Registe

Address
0xBF881350
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA11

Address
0xBF881360
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA11

Address
0xBF881370
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON12FIFO Control Register

Address
0xBF881380
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA12

Address
0xBF881390
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA12

Address
0xBF8813A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON13FIFO Control Register

Address
0xBF8813B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA13

Address
0xBF8813C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA13

Address
0xBF8813D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON14FIFO Control Register

Address
0xBF8813E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA14

Address
0xBF8813F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA14

Address
0xBF881400
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON15FIFO Control Register

Address
0xBF881410
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA15

Address
0xBF881420
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA15

Address
0xBF881430
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON16FIFO Control Register

Address
0xBF881440
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA16

Address
0xBF881450
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA16

Address
0xBF881460
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON17FIFO Control Register

Address
0xBF881470
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA17

Address
0xBF881480
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA17

Address
0xBF881490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON18FIFO Control Register

Address
0xBF8814A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA18

Address
0xBF8814B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA18

Address
0xBF8814C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON19FIFO Control Register

Address
0xBF8814D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA19

Address
0xBF8814E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA19

Address
0xBF8814F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON20FIFO Control Register

Address
0xBF881500
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA20

Address
0xBF881510
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA20

Address
0xBF881520
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON21FIFO Control Registe

Address
0xBF881530
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA21

Address
0xBF881540
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA21

Address
0xBF881550
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON22FIFO Control Register

Address
0xBF881560
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA22

Address
0xBF881570
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA22

Address
0xBF881580
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON23FIFO Control Register

Address
0xBF881590
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA23

Address
0xBF8815A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA23

Address
0xBF8815B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON24FIFO Control Register

Address
0xBF8815C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA24

Address
0xBF8815D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA24

Address
0xBF8815E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON25FIFO Control Register

Address
0xBF8815F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA25

Address
0xBF881600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA25

Address
0xBF881610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON26FIFO Control Register

Address
0xBF881620
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA26

Address
0xBF881630
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA26

Address
0xBF881640
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON27FIFO Control Register

Address
0xBF881650
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA27

Address
0xBF881660
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA27

Address
0xBF881670
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON28FIFO Control Register

Address
0xBF881680
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA28

Address
0xBF881690
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA28

Address
0xBF8816A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON29FIFO Control Register

Address
0xBF8816B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA29

Address
0xBF8816C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA29

Address
0xBF8816D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON30FIFO Control Register

Address
0xBF8816E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA30

Address
0xBF8816F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA30

Address
0xBF881700
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FIFOCON31FIFO Control Registe

Address
0xBF881710
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD2FIFOSTA31

Address
0xBF881720
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD2FIFOUA31

Address
0xBF881730
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD2FLTCON0Filter Control Register

Address
0xBF881740
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F3BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F2BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F1BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN07Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F0BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the RX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON1Filter Control Registe

Address
0xBF881750
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F7BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F6BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F5BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN47Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F4BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON2Filter Control Register

Address
0xBF881760
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F11BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1023Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F10BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F9BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN87Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F8BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON3Filter Control Register

Address
0xBF881770
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F15BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1423Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F14BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1315Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F13BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN127Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F12BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1531Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON4Filter Control Register

Address
0xBF881780
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F19BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1823Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F18BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1715Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F17BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN167Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F16BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1931Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON5Filter Control Register

Address
0xBF881790
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F23BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F22BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F21BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN207Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F20BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON6Filter Control Register

Address
0xBF8817A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F27BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F26BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F25BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN247Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F24BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTCON7Filter Control Register

Address
0xBF8817B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F31BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3023Enable Filter nto Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F30BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F29BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN287Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F28BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD2FLTOBJ0

Address
0xBF8817C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit
EID28:11
SID10:0

CFD2MASK0

Address
0xBF8817D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ1Filter Object Registe

Address
0xBF8817E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK1Filter Object Registe

Address
0xBF8817F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ2Filter Object Register

Address
0xBF881800
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK2

Address
0xBF881810
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ3Filter Object Register

Address
0xBF881820
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK3

Address
0xBF881830
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ4Filter Object Register

Address
0xBF881840
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK4Filter Object Register

Address
0xBF881850
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ5Filter Object Register

Address
0xBF881860
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK5Filter Object Register

Address
0xBF881870
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ6Filter Object Register

Address
0xBF881880
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK6Filter Object Register

Address
0xBF881890
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ7Filter Object Register

Address
0xBF8818A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK7Filter Object Register

Address
0xBF8818B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ8Filter Object Register

Address
0xBF8818C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK8Filter Object Register

Address
0xBF8818D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ9Filter Object Register

Address
0xBF8818E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK9Filter Object Register

Address
0xBF8818F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ10Filter Object Register

Address
0xBF881900
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK10Filter Object Register

Address
0xBF881910
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ11Filter Object Registe

Address
0xBF881920
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK11Filter Object Registe

Address
0xBF881930
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ12Filter Object Register

Address
0xBF881940
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK12Filter Object Register

Address
0xBF881950
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ13Filter Object Register

Address
0xBF881960
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK13Filter Object Register

Address
0xBF881970
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ14Filter Object Register

Address
0xBF881980
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK14Filter Object Register

Address
0xBF881990
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ15Filter Object Register

Address
0xBF8819A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK15Filter Object Register

Address
0xBF8819B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ16Filter Object Register

Address
0xBF8819C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD2MASK16Filter Object Register

Address
0xBF8819D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ17Filter Object Register

Address
0xBF8819E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK17Filter Object Register

Address
0xBF8819F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ18Filter Object Register

Address
0xBF881A00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK18Filter Object Register

Address
0xBF881A10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ19Filter Object Register

Address
0xBF881A20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK19Filter Object Register

Address
0xBF881A30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ20Filter Object Register

Address
0xBF881A40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK20Filter Object Register

Address
0xBF881A50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ22Filter Object Register

Address
0xBF881A80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK22Filter Object Register

Address
0xBF881A90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ23Filter Object Register

Address
0xBF881AA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK23Filter Object Register

Address
0xBF881AB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ24Filter Object Register

Address
0xBF881AC0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK24Filter Object Register

Address
0xBF881AD0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ25Filter Object Register

Address
0xBF881AE0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK25Filter Object Register

Address
0xBF881AF0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ26Filter Object Register

Address
0xBF881B00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK26Filter Object Register

Address
0xBF881B10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ27Filter Object Register

Address
0xBF881B20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK27Filter Object Register

Address
0xBF881B30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ28Filter Object Register

Address
0xBF881B40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK28Filter Object Register

Address
0xBF881B50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ29Filter Object Register

Address
0xBF881B60
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK29Filter Object Register

Address
0xBF881B70
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ30Filter Object Register

Address
0xBF881B80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK30Filter Object Register

Address
0xBF881B90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD2FLTOBJ31Filter Object Register

Address
0xBF881BA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD2MASK31Filter Object Register

Address
0xBF881BB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3CONCAN Control Register

Address
0xBF884000
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
ABAT27Abort All Pending Transmissions bit
  • 0 Module will clear this bit when all transmissions aborted
  • 1 Signal all transmit buffers to abort transmission
REQOP26:24Request Operation Mode bits
  • 0 Set Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Set Disable mode
  • 2 Set Internal Loopback mode
  • 3 Set Listen Only mode
  • 4 Set Configuration mode
  • 5 Set External Loopback mode
  • 6 Set Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Set Restricted Operation mode
OPMOD23:21Operation Mode Status bits
  • 0 Module is in Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Module is in Disable mode
  • 2 Module is in Internal Loopback mode
  • 3 Module is in Listen Only mode
  • 4 Module is in Configuration mode
  • 5 Module is in External Loopback mode
  • 6 Module is Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Module is Restricted Operation mode
TXQEN20Enable Transmit Queue bit
  • 0 Dont reserve space in RAM for Transmit Queue
  • 1 Enables Transmit Queue and reserves space in RAM
STEF19Store in Transmit Event FIFO bit
  • 0 Dont save transmitted messages in TEF
  • 1 Save transmitted messages in TEF
SERR2LOM18Transition to Listen Only Mode on System Error bit
  • 0 Transition to Restricted Operation Mode
  • 1 Transition to Listen Only Mode
ESIGM17Transmit ESI in Gateway Mode bit
  • 0 ESI reflects error status of CAN controller
  • 1 ESI is transmitted as recessive when ESI of message is high or CAN controller error passive
RTXAT16Restrict Retransmission Attempts bit
  • 0 Unlimited number of retransmission attempts
  • 1 Restricted retransmission attempts
ON15Enable bit
  • 0 CAN module is disabled
  • 1 CAN module is enabled
SIDL13Stop-in-Idle Control bit
  • 0 Dont stop module operation in Idle mode
  • 1 Stop module operation in Idle mode
BRSDIS12Bit Rate Switching Disable bit
  • 0 Bit Rate Switching depends on BRS in the Transmit Message Object
  • 1 Bit Rate Switching is Disabled
BUSY11CAN Module is Busy bit
  • 0 The CAN module is inactive
  • 1 The CAN module is active
WFT10:9Selectable Wake-up Filter Time bits
  • 0 T00FILTER (Typical 100 ns)
  • 1 T01FILTER (Typical 187 ns)
  • 2 T10FILTER (Typical 375 ns)
  • 3 T11FILTER (Typical 600 ns)
WAKFIL8Enable CAN Bus Line Wake-up Filter bit
  • 0 CAN bus line filter is not used for wake-up
  • 1 Use CAN bus line filter for wake-up
CLKSEL07Module Clock Source Select bit
  • 0 SYSCLK is active when the CAN FD module is enabled
  • 1 REFCLK4 is active when the CAN FD module is enabled
PXEDIS6Protocol Exception Event Detection Disabled bit
  • 0 If a Protocol Exception is detected
  • 1 Protocol Exception is treated as a Form Error.
ISOCRCEN5Enable ISO CRC in CAN FD Frames bit
  • 0 Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros
  • 1 Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector
DNCNT4:0Device Net Filter Bit Number bits
TXBWS31:28Transmit Bandwidth Sharing bits
  • 0 No delay
  • 1 2
  • 2 4
  • 3 8
  • 4 16
  • 5 32
  • 6 64
  • 7 128
  • 8 256
  • 9 512
  • 10 1024
  • 11 2048
  • 12 4096

CFD3NBTCFGNominal Bit Time Configuration Register

Address
0xBF884010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG123:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 255 Length is 256 x Tq
TSEG214:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 31 Length is 128 x Tq
SJW6:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 127 Length is 128 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq = 1/Fsys
  • 255 Tq = 256/Fsys

CFD3DBTCFGData Bit Time Configuration Register

Address
0xBF884020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG120:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
  • 16 Length is 17 x Tq
  • 17 Length is 18 x Tq
  • 18 Length is 19 x Tq
  • 19 Length is 20 x Tq
  • 20 Length is 21 x Tq
  • 21 Length is 22 x Tq
  • 22 Length is 23 x Tq
  • 23 Length is 24 x Tq
  • 24 Length is 25 x Tq
  • 25 Length is 26 x Tq
  • 26 Length is 27 x Tq
  • 27 Length is 28 x Tq
  • 28 Length is 29 x Tq
  • 29 Length is 30 x Tq
  • 30 Length is 31 x Tq
  • 31 Length is 32 x Tq
TSEG211:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
SJW3:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq is 1/Fsys
  • 255 Tq is 256/Fsys

CFD3TDCTransmitter Delay Compensation Register

Address
0xBF884030
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EDGFLTEN25Enable Edge Filtering during Bus Integration state bit
  • 0 Edge Filtering disabled
  • 1 Edge Filtering enabled
SID11EN24Enable 12-Bit SID in CAN FD Base Format Messages bit
  • 0 Do not use RRS; SID(10-0) according to ISO11898-1 2015
  • 1 RRS is used as SID11 in CAN FD base format messages: SID(11-0) = {SID(10-0)
TDCMOD17:16Transmitter Delay Compensation Mode bits
  • 0 Disable
  • 1 Manual; Do not measure use TDCV plus TDCO from the register
  • 2 Auto; measure delay and add CFDxDBTCFG.TSEG1; add TDCO
TDCO14:8Transmitter Delay Compensation Offset bits
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK
TDCV5:0Transmitter Delay Compensation Value bits; Secondary Sample Point
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK

CFD3TBCCAN Time Base Counter Register

Address
0xBF884040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBC31:0

CFD3TSCONCAN Time Stamp Control Register

Address
0xBF884050
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSRES18Time Stamp Resolution bit
  • 0 At sample point of SOF
  • 1 At sample point of the bit following the FDF bit
TSEOF17Time Stamp EOF bit
  • 0 Time Stamp at beginning of Frame (classical frame) at sample point of SOF / FD frame: see the TSRES bit
  • 1 Time Stamp when frame is taken valid (11898-1 10.7)
TBCEN16Time Base Counter Enable bit
  • 0 Stop and reset TBC
  • 1 Enable TBC
TBCPRE9:0CAN Time Base Counter Prescaler bits
  • 0 TBC increments every 1 SYSCLK clock cycle
  • 511 TBC increments every 1024 SYSCLK clock cycles

CFD3VECInterrupt Code Register

Address
0xBF884060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
RXCODE30:24Receive Interrupt Flag Code bits
  • 0 Reserved. FIFO 0 cant receive.
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
TXCODE22:16Transmit Interrupt Flag Code bits
  • 0 FIFO 0 Interrupt
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
FILHIT12:8Filter Hit Number bits
  • 0 Filter 0
  • 1 Filter 1
  • 2 Filter 2
  • 3 Filter 3
  • 4 Filter 4
  • 5 Filter 5
  • 6 Filter 6
  • 7 Filter 7
  • 8 Filter 8
  • 9 Filter 9
  • 10 Filter 10
  • 11 Filter 11
  • 12 Filter 12
  • 13 Filter 13
  • 14 Filter 14
  • 15 Filter 15
  • 16 Filter 16
  • 17 Filter 17
  • 18 Filter 18
  • 19 Filter 19
  • 20 Filter 20
  • 21 Filter 21
  • 22 Filter 22
  • 23 Filter 23
  • 24 Filter 24
  • 25 Filter 25
  • 26 Filter 26
  • 27 Filter 27
  • 28 Filter 28
  • 29 Filter 29
  • 30 Filter 30
  • 31 Filter 31
ICODE6:0Interrupt Flag Code bits
  • 0 FIFO 0 interrupt (TFIF0 set)
  • 1 FIFO 1 interrupt (TFIF1 or RFIF1 set)
  • 2 FIFO 2 interrupt (TFIF2 or RFIF2 set)
  • 3 FIFO 3 interrupt (TFIF3 or RFIF3 set)
  • 4 FIFO 4 interrupt (TFIF4 or RFIF4 set)
  • 5 FIFO 5 interrupt (TFIF5 or RFIF5 set)
  • 6 FIFO 6 interrupt (TFIF6 or RFIF6 set)
  • 7 FIFO 7 interrupt (TFIF7 or RFIF7 set)
  • 8 FIFO 8 interrupt (TFIF8 or RFIF8 set)
  • 9 FIFO 9 interrupt (TFIF9 or RFIF9 set)
  • 10 FIFO 10 interrupt (TFIF10 or RFIF10 set)
  • 11 FIFO 11 interrupt (TFIF11 or RFIF11 set)
  • 12 FIFO 12 interrupt (TFIF12 or RFIF12 set)
  • 13 FIFO 13 interrupt (TFIF13 or RFIF13 set)
  • 14 FIFO 14 interrupt (TFIF14 or RFIF14 set)
  • 15 FIFO 15 interrupt (TFIF15 or RFIF15 set)
  • 16 FIFO 16 interrupt (TFIF16 or RFIF16 set)
  • 17 FIFO 17 interrupt (TFIF17 or RFIF17 set)
  • 18 FIFO 18 interrupt (TFIF18 or RFIF18 set)
  • 19 FIFO 19 interrupt (TFIF19 or RFIF19 set)
  • 20 FIFO 20 interrupt (TFIF20 or RFIF20 set)
  • 21 FIFO 21 interrupt (TFIF21 or RFIF21 set)
  • 22 FIFO 22 interrupt (TFIF22 or RFIF22 set)
  • 23 FIFO 23 interrupt (TFIF23 or RFIF23 set)
  • 24 FIFO 24 interrupt (TFIF24 or RFIF24 set)
  • 25 FIFO 25 interrupt (TFIF25 or RFIF25 set)
  • 26 FIFO 26 interrupt (TFIF26 or RFIF26 set)
  • 27 FIFO 27 interrupt (TFIF27 or RFIF27 set)
  • 28 FIFO 28 interrupt (TFIF28 or RFIF28 set)
  • 29 FIFO 29 interrupt (TFIF29 or RFIF29 set)
  • 30 FIFO 30 interrupt (TFIF30 or RFIF30 set)
  • 31 FIFO 31 interrupt (TFIF31 or RFIF31 set)
  • 64 No interrupt
  • 65 Error interrupt (CERRIF/IE)
  • 66 Wake-up interrupt (WAKIF/WAKIE)
  • 67 Receive FIFO overflow interrupt (any bit in CFDxRXOVIF set)
  • 68 Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
  • 69 RX/TX MAB overflow/underflow (RX: message received before previous message was saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE)
  • 70 CAN Timer Overflow (CTMRIF/IE)
  • 71 CAN module mode change Occurred (MODIF/IE)
  • 72 Invalid message occurred (IVMIF/IE)
  • 73 Transmit event FIFO interrupt (any bit in the CFDxTEFIF register is set)
  • 74 Transmit attempt interrupt (any bit in the CFDxTXATIF register is set)

CFD3INTInterrupt Register

Address
0xBF884070
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
FieldBitsWhat it does
WAKIE30Bus Wake Up Activity Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
CERRIE29CAN Bus Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SERRIE28System Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXOVIE27Receive Buffer Overflow Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXATIE26Transmit Attempt Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SPICRCIE25
ECCIE24
TEFIE20Transmit Event FIFO Interrupt Enable bit
  • 1 Interrupts are enabled
MODIE19Mode Change Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TBCIE18CAN Timer Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXIE17Receive Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXIE16Transmit Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
IVMIF15Invalid Message Interrupt Flag bit
  • 0 No invalid message interrupts are pending
  • 1 An invalid message interrupt is pending
WAKIF14Bus Wake Up Activity Interrupt Flag bit
  • 0 No wake-up interrupts are pending
  • 1 A wake-up interrupt is pending
CERRIF13CAN Bus Error Interrupt Flag bit
  • 0 No CAN bus error interrupts are pending
  • 1 A CAN bus error interrupt is pending
SERRIF12System Error Interrupt Flag bit
  • 0 No system error occurred
  • 1 A system error occurred (collision on dual-port RAM)
RXOVIF11Receive Object Overflow Interrupt Flag bit
  • 0 No receive object overflow has occurred
  • 1 Receive object overflow occurred
TXATIF10Transmit Attempt Interrupt Flag bit
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set
SPICRCIF9
ECCIF8
TEFIF4Transmit Event FIFO Interrupt Flag bit
  • 0 No receive buffer overflow has occurred
  • 1 Receive buffer overflow occurred
MODIF3CAN Mode Change Interrupt Flag bit
  • 0 No mode change occurred
  • 1 CAN module mode change occurred (OPMOD has changed to reflect the REQOP bits)
TBCIF2CAN Timer Overflow Interrupt Flag bit
  • 0 TBC did not overflow
  • 1 TBC has overflowed
RXIF1Receive Object Interrupt Flag bit
  • 0 No receive object interrupts pending
  • 1 Receive object interrupt pending
TXIF0Transmit Object Interrupt Flag bit
  • 0 No transmit object interrupts pending
  • 1 Transmit object interrupt pending
IVMIE31Invalid Message Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled

CFD3RXIFReceive Interrupt Status Register

Address
0xBF884080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFIF31:1Receive FIFO Interrupt Pending bits
  • 0 No enabled receive FIFO interrupts are pending
  • 1 One or more enabled receive FIFO interrupts are pending

CFD3TXIFTransmit Interrupt Status Register

Address
0xBF884090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFIF31:0Transmit FIFO/Transmit Queue Interrupt Pending bits
  • 0 No enabled transmit FIFO/Transmit Queue interrupt are pending
  • 1 One or more enabled transmit FIFO/Transmit Queue interrupts are pending

CFD3RXOVIFReceive Overflow Interrupt Status Register

Address
0xBF8840A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFOVIF31:1Receive FIFO Overflow Interrupt Pending bits
  • 0 Interrupt not pending
  • 1 Interrupt is pending

CFD3TXATIFTransmit Attempt Interrupt Status Register

Address
0xBF8840B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFATIF31:0Transmit FIFO/Transmit Queue Attempt Interrupt Pending bits
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set

CFD3TXREQTransmit Request Register

Address
0xBF8840C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXREQ31:0

CFD3TRECTransmit/Receive Error Count Register

Address
0xBF8840D0
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
TXBO21Transmitter in Error State Bus Off bit (TERRCNT > 255)
  • 0 Indicates that transmit errors are less than 255
  • 1 Indicates that the number of transmit errors is greater than 255.
TXBP20Transmitter in Error State Bus Passive bit (TERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of transmit errors is greater than 127.
RXBP19Receiver in Error State Bus Passive bit (RERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of receive errors is greater than 127.
TXWARN18Transmitter in Error State Warning bit (128 > TERRCNT > 95)
  • 0 Indicates that transmit errors are greater than or equal to 95
  • 1 Indicates that the number of transmit errors are less than 128
RXWARN17Receiver in Error State Warning bit (128 > RERRCNT > 95)
  • 0 Indicates that receive errors are greater than or equal to 95
  • 1 Indicates that the number of receives errors is less than 128
EWARN16Transmitter or Receiver is in Error State Warning bit
  • 0 No transmit or receive warnings
  • 1 TXWARN or RXWARN is set
TERRCNT15:8Transmit Error Counter bits
  • 0 No transmit errors
  • 1 1 transmit error
  • 254 254 Transmit errors
  • 255 Greater than or equal to 255 Transmit errors.
RERRCNT7:0Receive Error Counter bits
  • 0 No receive errors
  • 1 1 receive error
  • 254 254 receive errors
  • 255 Greater than or equal to 255 Receive errors

CFD3BDIAG0Bus Diagnostics Register 0

Address
0xBF8840E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DRERRCNT23:16
NTERRCNT15:8
NRERRCNT7:0
DTERRCNT31:24

CFD3BDIAG1Bus Diagnostics Register

Address
0xBF8840F0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
ESI30Error State Indicator (ESI) Flag Status bit
  • 0 ESI flag of a received CAN FD message was not set
  • 1 ESI flag of a received CAN FD message was set
DCRCERR29Data CRC Error Status bit
  • 0 No received message data CRC error occurred
  • 1 CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
DSTUFERR28Data Stuffing Error Status bit
  • 0 No data received message errors
  • 1 More than five equal bits in a sequence have occurred in a portion of a received message where this is not allowed
DFORMERR27Data Format Error Status bit
  • 0 No format errors occurred
  • 1 Data fixed format portion of a received frame has the wrong format
DBIT1ERR25Data Bit Logical 1 Error Status bit
  • 0 No data logical 1 bit transmission error occurred
  • 1 During the data transmission of a message (with the exception of the arbitration field)
DBIT0ERR24Data Bit Logical 0 Error Status bit
  • 0 No data logical 0 bit transmission error occurred
  • 1 During the data transmission of a message the monitored bus value was recessive. During Bus Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored.
NCRCERR21Nominal CRC Error Status bit
  • 0 No nominal CRC received message error occurred
  • 1 The CRC checksum of a nominal received message was incorrect.
NSTUFERR20Nominal Stuffing Error Status bit
  • 0 No nominal bit stuffing errors have occurred
  • 1 More than five equal bits in a sequence have occurred in a part of a nominal received message where this is not allowed
NFORMERR19Nominal Format Error Status bit
  • 0 No nominal format error occurred
  • 1 A fixed format portion of a nominal received frame has the wrong format
NACKERR18Not Acknowledged Error Status bit
  • 0 A transmitted message was acknowledged
  • 1 A transmitted message was not acknowledged
NBIT1ERR17Nominal Bit Logical 1 Error Status bit
  • 0 No nominal bit logical 1 error occurred
  • 1 During the transmission of a nominal message (with the exception of the arbitration field)
NBIT0ERR16Nominal Bit Logical 0 Error Status bit
  • 0 No nominal bit logical 0 error occurred
  • 1 During the transmission of a nominal message
EFMSGCNT15:0Error Free Message Counter Status bits
  • 0 0 error free messages since the last register read
  • 65535 65536 error free messages since the last register read
DLCMM31Data Length Code (DLC) Mismatch Status bit
  • 0 No payload size error occurred
  • 1 Payload size error. During a transmission or reception the Data Length Code exceeds the payload size of the FIFO element defined in the PLSIZE bits (CFDxFIFOCONn).

CFD3TEFCONTransmit Event FIFO Control Register

Address
0xBF884100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 message deep
  • 1 FIFO is 2 messages deep
  • 2 FIFO is 3 messages deep
  • 3 FIFO is 4 messages deep
  • 4 FIFO is 5 messages deep
  • 5 FIFO is 6 messages deep
  • 6 FIFO is 7 messages deep
  • 7 FIFO is 8 messages deep
  • 8 FIFO is 9 messages deep
  • 9 FIFO is 10 messages deep
  • 10 FIFO is 11 messages deep
  • 11 FIFO is 12 messages deep
  • 12 FIFO is 13 messages deep
  • 13 FIFO is 14 messages deep
  • 14 FIFO is 15 messages deep
  • 15 FIFO is 16 messages deep
  • 16 FIFO is 17 messages deep
  • 17 FIFO is 18 messages deep
  • 18 FIFO is 19 messages deep
  • 19 FIFO is 20 messages deep
  • 20 FIFO is 21 messages deep
  • 21 FIFO is 22 messages deep
  • 22 FIFO is 23 messages deep
  • 23 FIFO is 24 messages deep
  • 24 FIFO is 25 messages deep
  • 25 FIFO is 26 messages deep
  • 26 FIFO is 27 messages deep
  • 27 FIFO is 28 messages deep
  • 28 FIFO is 29 messages deep
  • 29 FIFO is 30 messages deep
  • 30 FIFO is 31 messages deep
  • 31 FIFO is 32 messages deep
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set
UINC8
TEFTSEN5Transmit Event FIFO Time Stamp Enable bit
  • 0 Do not time stamp elements in TEF
  • 1 Time stamp elements in TEF
TEFOVIE3Transmit Event FIFO Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TEFFIE2Transmit Event FIFO Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO full
  • 1 Interrupt enabled for FIFO full
TEFHIE1Transmit Event FIFO Half Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO half full
  • 1 Interrupt enabled for FIFO half full
TEFNEIE0Transmit Event FIFO Not Empty Interrupt Enable bit
  • 0 Interrupt disabled for FIFO not empty
  • 1 Interrupt enabled for FIFO not empty

CFD3TEFSTATransmit Event FIFO Status Register

Address
0xBF884110
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TEFOVIF3Transmit Event FIFO Overflow Interrupt Flag bit
  • 0 No overflow event has occurred
  • 1 Overflow event has occurred
TEFFIF2Transmit Event FIFO Full Interrupt Flag bit
  • 0 FIFO is not full
  • 1 FIFO is full
TEFHIF1Transmit Event FIFO Half Full Interrupt Flag bit
  • 0 FIFO is less than half full
  • 1 FIFO is greater than or equal to half full
TEFNEIF0Transmit Event FIFO Not Empty Interrupt Flag bit
  • 0 FIFO is empty
  • 1 FIFO is not empty (has at least one message)

CFD3TEFUATransmit Event FIFO User Address Register

Address
0xBF884120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TEFUA31:0

CFD3FIFOBAMessage Memory Base Address Register

Address
0xBF884130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOBA31:0

CFD3TXQCONTransmit Queue Control Register

Address
0xBF884140
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. The user application should poll whether this bit is clear before taking any action.
TXREQ9Message Send Request bit
  • 0 Clearing the bit to 0 while set will request a message abort.
  • 1 Requests sending a message; the bit will automatically clear when all the messages queued in the Transmit Queue are successfully sent
UINC8Increment Head/Tail bit
  • 0 FIFO head will not increment by a single message
  • 1 FIFO head will increment by a single message
TXEN7TX Enable
  • 1 Transmit Message Queue. This bit always reads as 1.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
TXQEIE2Transmit Queue Empty Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue empty
  • 1 Interrupt enabled for Transmit Queue empty
TXQNIE0Transmit Queue Not Full Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue not full
  • 1 Interrupt enabled for Transmit Queue not full
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3TXQSTATransmit Queue Status Register

Address
0xBF884150
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
TXQCI12:8
TXABT7Message Aborted Status bit
  • 0 Message completed successfully
  • 1 Message was aborted
TXLARB6Message Lost Arbitration Status bit
  • 0 Message did not loose arbitration while being sent
  • 1 Message lost arbitration while being sent
TXERR5Error Detected During Transmission bit
  • 0 A bus error did not occur while the message was being sent
  • 1 A bus error occurred while the message was being sent
TXATIF4Transmit Attempts Exhausted Interrupt Pending bit
  • 0 Interrupt Not pending
  • 1 Interrupt pending
TXQEIF2Transmit Queue Empty Interrupt Flag bit
  • 0 Transmit Queue is not empty
  • 1 Transmit Queue is empty
TXQNIF0Transmit Queue Not Full Interrupt Flag bit
  • 0 Transmit Queue is full
  • 1 Transmit Queue is not full

CFD3TXQUATransmit Queue User Address Register

Address
0xBF884160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXQUA31:0

CFD3FIFOCON1FIFO Control Registe

Address
0xBF884170
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA1

Address
0xBF884180
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA1

Address
0xBF884190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON2FIFO Control Register

Address
0xBF8841A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA2

Address
0xBF8841B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA2

Address
0xBF8841C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON3FIFO Control Register

Address
0xBF8841D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA3

Address
0xBF8841E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA3

Address
0xBF8841F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON4FIFO Control Register

Address
0xBF884200
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA4

Address
0xBF884210
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA4

Address
0xBF884220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON5FIFO Control Register

Address
0xBF884230
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA5

Address
0xBF884240
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA5

Address
0xBF884250
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON6FIFO Control Register

Address
0xBF884260
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA6

Address
0xBF884270
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA6

Address
0xBF884280
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON7FIFO Control Register

Address
0xBF884290
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA7

Address
0xBF8842A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA7

Address
0xBF8842B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON8FIFO Control Register

Address
0xBF8842C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA8

Address
0xBF8842D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA8

Address
0xBF8842E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON9FIFO Control Register

Address
0xBF8842F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA9

Address
0xBF884300
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA9

Address
0xBF884310
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON10FIFO Control Register

Address
0xBF884320
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA10

Address
0xBF884330
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA10

Address
0xBF884340
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON11FIFO Control Registe

Address
0xBF884350
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA11

Address
0xBF884360
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA11

Address
0xBF884370
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON12FIFO Control Register

Address
0xBF884380
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA12

Address
0xBF884390
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA12

Address
0xBF8843A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON13FIFO Control Register

Address
0xBF8843B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA13

Address
0xBF8843C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA13

Address
0xBF8843D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON14FIFO Control Register

Address
0xBF8843E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA14

Address
0xBF8843F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA14

Address
0xBF884400
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON15FIFO Control Register

Address
0xBF884410
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA15

Address
0xBF884420
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA15

Address
0xBF884430
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON16FIFO Control Register

Address
0xBF884440
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA16

Address
0xBF884450
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA16

Address
0xBF884460
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON17FIFO Control Register

Address
0xBF884470
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA17

Address
0xBF884480
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA17

Address
0xBF884490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON18FIFO Control Register

Address
0xBF8844A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA18

Address
0xBF8844B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA18

Address
0xBF8844C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON19FIFO Control Register

Address
0xBF8844D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA19

Address
0xBF8844E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA19

Address
0xBF8844F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON20FIFO Control Register

Address
0xBF884500
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA20

Address
0xBF884510
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA20

Address
0xBF884520
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON21FIFO Control Registe

Address
0xBF884530
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA21

Address
0xBF884540
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA21

Address
0xBF884550
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON22FIFO Control Register

Address
0xBF884560
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA22

Address
0xBF884570
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA22

Address
0xBF884580
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON23FIFO Control Register

Address
0xBF884590
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA23

Address
0xBF8845A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA23

Address
0xBF8845B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON24FIFO Control Register

Address
0xBF8845C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA24

Address
0xBF8845D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA24

Address
0xBF8845E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON25FIFO Control Register

Address
0xBF8845F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA25

Address
0xBF884600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA25

Address
0xBF884610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON26FIFO Control Register

Address
0xBF884620
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA26

Address
0xBF884630
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA26

Address
0xBF884640
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON27FIFO Control Register

Address
0xBF884650
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA27

Address
0xBF884660
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA27

Address
0xBF884670
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON28FIFO Control Register

Address
0xBF884680
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA28

Address
0xBF884690
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA28

Address
0xBF8846A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON29FIFO Control Register

Address
0xBF8846B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA29

Address
0xBF8846C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA29

Address
0xBF8846D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON30FIFO Control Register

Address
0xBF8846E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA30

Address
0xBF8846F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA30

Address
0xBF884700
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FIFOCON31FIFO Control Registe

Address
0xBF884710
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD3FIFOSTA31

Address
0xBF884720
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD3FIFOUA31

Address
0xBF884730
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD3FLTCON0Filter Control Register

Address
0xBF884740
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F3BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F2BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F1BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN07Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F0BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the RX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON1Filter Control Registe

Address
0xBF884750
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F7BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F6BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F5BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN47Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F4BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON2Filter Control Register

Address
0xBF884760
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F11BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1023Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F10BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F9BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN87Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F8BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON3Filter Control Register

Address
0xBF884770
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F15BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1423Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F14BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1315Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F13BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN127Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F12BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1531Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON4Filter Control Register

Address
0xBF884780
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F19BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1823Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F18BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1715Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F17BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN167Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F16BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1931Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON5Filter Control Register

Address
0xBF884790
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F23BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F22BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F21BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN207Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F20BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON6Filter Control Register

Address
0xBF8847A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F27BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F26BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F25BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN247Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F24BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTCON7Filter Control Register

Address
0xBF8847B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F31BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3023Enable Filter nto Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F30BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F29BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN287Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F28BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD3FLTOBJ0

Address
0xBF8847C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit
EID28:11
SID10:0

CFD3MASK0

Address
0xBF8847D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ1Filter Object Registe

Address
0xBF8847E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK1Filter Object Registe

Address
0xBF8847F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ2Filter Object Register

Address
0xBF884800
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK2

Address
0xBF884810
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ3Filter Object Register

Address
0xBF884820
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK3

Address
0xBF884830
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ4Filter Object Register

Address
0xBF884840
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK4Filter Object Register

Address
0xBF884850
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ5Filter Object Register

Address
0xBF884860
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK5Filter Object Register

Address
0xBF884870
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ6Filter Object Register

Address
0xBF884880
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK6Filter Object Register

Address
0xBF884890
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ7Filter Object Register

Address
0xBF8848A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK7Filter Object Register

Address
0xBF8848B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ8Filter Object Register

Address
0xBF8848C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK8Filter Object Register

Address
0xBF8848D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ9Filter Object Register

Address
0xBF8848E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK9Filter Object Register

Address
0xBF8848F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ10Filter Object Register

Address
0xBF884900
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK10Filter Object Register

Address
0xBF884910
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ11Filter Object Registe

Address
0xBF884920
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK11Filter Object Registe

Address
0xBF884930
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ12Filter Object Register

Address
0xBF884940
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK12Filter Object Register

Address
0xBF884950
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ13Filter Object Register

Address
0xBF884960
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK13Filter Object Register

Address
0xBF884970
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ14Filter Object Register

Address
0xBF884980
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK14Filter Object Register

Address
0xBF884990
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ15Filter Object Register

Address
0xBF8849A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK15Filter Object Register

Address
0xBF8849B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ16Filter Object Register

Address
0xBF8849C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD3MASK16Filter Object Register

Address
0xBF8849D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ17Filter Object Register

Address
0xBF8849E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK17Filter Object Register

Address
0xBF8849F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ18Filter Object Register

Address
0xBF884A00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK18Filter Object Register

Address
0xBF884A10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ19Filter Object Register

Address
0xBF884A20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK19Filter Object Register

Address
0xBF884A30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ20Filter Object Register

Address
0xBF884A40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK20Filter Object Register

Address
0xBF884A50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ22Filter Object Register

Address
0xBF884A80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK22Filter Object Register

Address
0xBF884A90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ23Filter Object Register

Address
0xBF884AA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK23Filter Object Register

Address
0xBF884AB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ24Filter Object Register

Address
0xBF884AC0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK24Filter Object Register

Address
0xBF884AD0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ25Filter Object Register

Address
0xBF884AE0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK25Filter Object Register

Address
0xBF884AF0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ26Filter Object Register

Address
0xBF884B00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK26Filter Object Register

Address
0xBF884B10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ27Filter Object Register

Address
0xBF884B20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK27Filter Object Register

Address
0xBF884B30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ28Filter Object Register

Address
0xBF884B40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK28Filter Object Register

Address
0xBF884B50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ29Filter Object Register

Address
0xBF884B60
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK29Filter Object Register

Address
0xBF884B70
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ30Filter Object Register

Address
0xBF884B80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK30Filter Object Register

Address
0xBF884B90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD3FLTOBJ31Filter Object Register

Address
0xBF884BA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD3MASK31Filter Object Register

Address
0xBF884BB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4CONCAN Control Register

Address
0xBF885000
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
ABAT27Abort All Pending Transmissions bit
  • 0 Module will clear this bit when all transmissions aborted
  • 1 Signal all transmit buffers to abort transmission
REQOP26:24Request Operation Mode bits
  • 0 Set Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Set Disable mode
  • 2 Set Internal Loopback mode
  • 3 Set Listen Only mode
  • 4 Set Configuration mode
  • 5 Set External Loopback mode
  • 6 Set Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Set Restricted Operation mode
OPMOD23:21Operation Mode Status bits
  • 0 Module is in Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames
  • 1 Module is in Disable mode
  • 2 Module is in Internal Loopback mode
  • 3 Module is in Listen Only mode
  • 4 Module is in Configuration mode
  • 5 Module is in External Loopback mode
  • 6 Module is Normal CAN 2.0 mode; error frames on CAN FD frames
  • 7 Module is Restricted Operation mode
TXQEN20Enable Transmit Queue bit
  • 0 Dont reserve space in RAM for Transmit Queue
  • 1 Enables Transmit Queue and reserves space in RAM
STEF19Store in Transmit Event FIFO bit
  • 0 Dont save transmitted messages in TEF
  • 1 Save transmitted messages in TEF
SERR2LOM18Transition to Listen Only Mode on System Error bit
  • 0 Transition to Restricted Operation Mode
  • 1 Transition to Listen Only Mode
ESIGM17Transmit ESI in Gateway Mode bit
  • 0 ESI reflects error status of CAN controller
  • 1 ESI is transmitted as recessive when ESI of message is high or CAN controller error passive
RTXAT16Restrict Retransmission Attempts bit
  • 0 Unlimited number of retransmission attempts
  • 1 Restricted retransmission attempts
ON15Enable bit
  • 0 CAN module is disabled
  • 1 CAN module is enabled
SIDL13Stop-in-Idle Control bit
  • 0 Dont stop module operation in Idle mode
  • 1 Stop module operation in Idle mode
BRSDIS12Bit Rate Switching Disable bit
  • 0 Bit Rate Switching depends on BRS in the Transmit Message Object
  • 1 Bit Rate Switching is Disabled
BUSY11CAN Module is Busy bit
  • 0 The CAN module is inactive
  • 1 The CAN module is active
WFT10:9Selectable Wake-up Filter Time bits
  • 0 T00FILTER (Typical 100 ns)
  • 1 T01FILTER (Typical 187 ns)
  • 2 T10FILTER (Typical 375 ns)
  • 3 T11FILTER (Typical 600 ns)
WAKFIL8Enable CAN Bus Line Wake-up Filter bit
  • 0 CAN bus line filter is not used for wake-up
  • 1 Use CAN bus line filter for wake-up
CLKSEL07Module Clock Source Select bit
  • 0 SYSCLK is active when the CAN FD module is enabled
  • 1 REFCLK4 is active when the CAN FD module is enabled
PXEDIS6Protocol Exception Event Detection Disabled bit
  • 0 If a Protocol Exception is detected
  • 1 Protocol Exception is treated as a Form Error.
ISOCRCEN5Enable ISO CRC in CAN FD Frames bit
  • 0 Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros
  • 1 Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector
DNCNT4:0Device Net Filter Bit Number bits
TXBWS31:28Transmit Bandwidth Sharing bits
  • 0 No delay
  • 1 2
  • 2 4
  • 3 8
  • 4 16
  • 5 32
  • 6 64
  • 7 128
  • 8 256
  • 9 512
  • 10 1024
  • 11 2048
  • 12 4096

CFD4NBTCFGNominal Bit Time Configuration Register

Address
0xBF885010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG123:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 255 Length is 256 x Tq
TSEG214:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 31 Length is 128 x Tq
SJW6:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 127 Length is 128 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq = 1/Fsys
  • 255 Tq = 256/Fsys

CFD4DBTCFGData Bit Time Configuration Register

Address
0xBF885020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSEG120:16Time Segment 1 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
  • 16 Length is 17 x Tq
  • 17 Length is 18 x Tq
  • 18 Length is 19 x Tq
  • 19 Length is 20 x Tq
  • 20 Length is 21 x Tq
  • 21 Length is 22 x Tq
  • 22 Length is 23 x Tq
  • 23 Length is 24 x Tq
  • 24 Length is 25 x Tq
  • 25 Length is 26 x Tq
  • 26 Length is 27 x Tq
  • 27 Length is 28 x Tq
  • 28 Length is 29 x Tq
  • 29 Length is 30 x Tq
  • 30 Length is 31 x Tq
  • 31 Length is 32 x Tq
TSEG211:8Time Segment 2 bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
SJW3:0Synchronization Jump Width bits
  • 0 Length is 1 x Tq
  • 1 Length is 2 x Tq
  • 2 Length is 3 x Tq
  • 3 Length is 4 x Tq
  • 4 Length is 5 x Tq
  • 5 Length is 6 x Tq
  • 6 Length is 7 x Tq
  • 7 Length is 8 x Tq
  • 8 Length is 9 x Tq
  • 9 Length is 10 x Tq
  • 10 Length is 11 x Tq
  • 11 Length is 12 x Tq
  • 12 Length is 13 x Tq
  • 13 Length is 14 x Tq
  • 14 Length is 15 x Tq
  • 15 Length is 16 x Tq
BRP31:24Baud Rate Prescaler bits
  • 0 Tq is 1/Fsys
  • 255 Tq is 256/Fsys

CFD4TDCTransmitter Delay Compensation Register

Address
0xBF885030
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EDGFLTEN25Enable Edge Filtering during Bus Integration state bit
  • 0 Edge Filtering disabled
  • 1 Edge Filtering enabled
SID11EN24Enable 12-Bit SID in CAN FD Base Format Messages bit
  • 0 Do not use RRS; SID(10-0) according to ISO11898-1 2015
  • 1 RRS is used as SID11 in CAN FD base format messages: SID(11-0) = {SID(10-0)
TDCMOD17:16Transmitter Delay Compensation Mode bits
  • 0 Disable
  • 1 Manual; Do not measure use TDCV plus TDCO from the register
  • 2 Auto; measure delay and add CFDxDBTCFG.TSEG1; add TDCO
TDCO14:8Transmitter Delay Compensation Offset bits
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK
TDCV5:0Transmitter Delay Compensation Value bits; Secondary Sample Point
  • 0 0 x SYSCLK
  • 1 1 x SYSCLK
  • 2 2 x SYSCLK
  • 3 3 x SYSCLK
  • 4 4 x SYSCLK
  • 5 5 x SYSCLK
  • 6 6 x SYSCLK
  • 7 7 x SYSCLK
  • 8 8 x SYSCLK
  • 9 9 x SYSCLK
  • 10 10 x SYSCLK
  • 11 11 x SYSCLK
  • 12 12 x SYSCLK
  • 13 13 x SYSCLK
  • 14 14 x SYSCLK
  • 15 15 x SYSCLK
  • 16 16 x SYSCLK
  • 17 17 x SYSCLK
  • 18 18 x SYSCLK
  • 19 19 x SYSCLK
  • 20 20 x SYSCLK
  • 21 21 x SYSCLK
  • 22 22 x SYSCLK
  • 23 23 x SYSCLK
  • 24 24 x SYSCLK
  • 25 25 x SYSCLK
  • 26 26 x SYSCLK
  • 27 27 x SYSCLK
  • 28 28 x SYSCLK
  • 29 29 x SYSCLK
  • 30 30 x SYSCLK
  • 31 31 x SYSCLK
  • 32 32 x SYSCLK
  • 33 33 x SYSCLK
  • 34 34 x SYSCLK
  • 35 35 x SYSCLK
  • 36 36 x SYSCLK
  • 37 37 x SYSCLK
  • 38 38 x SYSCLK
  • 39 39 x SYSCLK
  • 40 40 x SYSCLK
  • 41 41 x SYSCLK
  • 42 42 x SYSCLK
  • 43 43 x SYSCLK
  • 44 44 x SYSCLK
  • 45 45 x SYSCLK
  • 46 46 x SYSCLK
  • 47 47 x SYSCLK
  • 48 48 x SYSCLK
  • 49 49 x SYSCLK
  • 50 50 x SYSCLK
  • 51 51 x SYSCLK
  • 52 52 x SYSCLK
  • 53 53 x SYSCLK
  • 54 54 x SYSCLK
  • 55 55 x SYSCLK
  • 56 56 x SYSCLK
  • 57 57 x SYSCLK
  • 58 58 x SYSCLK
  • 59 59 x SYSCLK
  • 60 60 x SYSCLK
  • 61 61 x SYSCLK
  • 62 62 x SYSCLK
  • 63 63 x SYSCLK

CFD4TBCCAN Time Base Counter Register

Address
0xBF885040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBC31:0

CFD4TSCONCAN Time Stamp Control Register

Address
0xBF885050
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TSRES18Time Stamp Resolution bit
  • 0 At sample point of SOF
  • 1 At sample point of the bit following the FDF bit
TSEOF17Time Stamp EOF bit
  • 0 Time Stamp at beginning of Frame (classical frame) at sample point of SOF / FD frame: see the TSRES bit
  • 1 Time Stamp when frame is taken valid (11898-1 10.7)
TBCEN16Time Base Counter Enable bit
  • 0 Stop and reset TBC
  • 1 Enable TBC
TBCPRE9:0CAN Time Base Counter Prescaler bits
  • 0 TBC increments every 1 SYSCLK clock cycle
  • 511 TBC increments every 1024 SYSCLK clock cycles

CFD4VECInterrupt Code Register

Address
0xBF885060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
RXCODE30:24Receive Interrupt Flag Code bits
  • 0 Reserved. FIFO 0 cant receive.
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
TXCODE22:16Transmit Interrupt Flag Code bits
  • 0 FIFO 0 Interrupt
  • 1 FIFO 1 Interrupt
  • 2 FIFO 2 Interrupt
  • 3 FIFO 3 Interrupt
  • 4 FIFO 4 Interrupt
  • 5 FIFO 5 Interrupt
  • 6 FIFO 6 Interrupt
  • 7 FIFO 7 Interrupt
  • 8 FIFO 8 Interrupt
  • 9 FIFO 9 Interrupt
  • 10 FIFO 10 Interrupt
  • 11 FIFO 11 Interrupt
  • 12 FIFO 12 Interrupt
  • 13 FIFO 13 Interrupt
  • 14 FIFO 14 Interrupt
  • 15 FIFO 15 Interrupt
  • 16 FIFO 16 Interrupt
  • 17 FIFO 17 Interrupt
  • 18 FIFO 18 Interrupt
  • 19 FIFO 19 Interrupt
  • 20 FIFO 20 Interrupt
  • 21 FIFO 21 Interrupt
  • 22 FIFO 22 Interrupt
  • 23 FIFO 23 Interrupt
  • 24 FIFO 24 Interrupt
  • 25 FIFO 25 Interrupt
  • 26 FIFO 26 Interrupt
  • 27 FIFO 27 Interrupt
  • 28 FIFO 28 Interrupt
  • 29 FIFO 29 Interrupt
  • 30 FIFO 30 Interrupt
  • 31 FIFO 31 Interrupt
  • 64 No interrupt
FILHIT12:8Filter Hit Number bits
  • 0 Filter 0
  • 1 Filter 1
  • 2 Filter 2
  • 3 Filter 3
  • 4 Filter 4
  • 5 Filter 5
  • 6 Filter 6
  • 7 Filter 7
  • 8 Filter 8
  • 9 Filter 9
  • 10 Filter 10
  • 11 Filter 11
  • 12 Filter 12
  • 13 Filter 13
  • 14 Filter 14
  • 15 Filter 15
  • 16 Filter 16
  • 17 Filter 17
  • 18 Filter 18
  • 19 Filter 19
  • 20 Filter 20
  • 21 Filter 21
  • 22 Filter 22
  • 23 Filter 23
  • 24 Filter 24
  • 25 Filter 25
  • 26 Filter 26
  • 27 Filter 27
  • 28 Filter 28
  • 29 Filter 29
  • 30 Filter 30
  • 31 Filter 31
ICODE6:0Interrupt Flag Code bits
  • 0 FIFO 0 interrupt (TFIF0 set)
  • 1 FIFO 1 interrupt (TFIF1 or RFIF1 set)
  • 2 FIFO 2 interrupt (TFIF2 or RFIF2 set)
  • 3 FIFO 3 interrupt (TFIF3 or RFIF3 set)
  • 4 FIFO 4 interrupt (TFIF4 or RFIF4 set)
  • 5 FIFO 5 interrupt (TFIF5 or RFIF5 set)
  • 6 FIFO 6 interrupt (TFIF6 or RFIF6 set)
  • 7 FIFO 7 interrupt (TFIF7 or RFIF7 set)
  • 8 FIFO 8 interrupt (TFIF8 or RFIF8 set)
  • 9 FIFO 9 interrupt (TFIF9 or RFIF9 set)
  • 10 FIFO 10 interrupt (TFIF10 or RFIF10 set)
  • 11 FIFO 11 interrupt (TFIF11 or RFIF11 set)
  • 12 FIFO 12 interrupt (TFIF12 or RFIF12 set)
  • 13 FIFO 13 interrupt (TFIF13 or RFIF13 set)
  • 14 FIFO 14 interrupt (TFIF14 or RFIF14 set)
  • 15 FIFO 15 interrupt (TFIF15 or RFIF15 set)
  • 16 FIFO 16 interrupt (TFIF16 or RFIF16 set)
  • 17 FIFO 17 interrupt (TFIF17 or RFIF17 set)
  • 18 FIFO 18 interrupt (TFIF18 or RFIF18 set)
  • 19 FIFO 19 interrupt (TFIF19 or RFIF19 set)
  • 20 FIFO 20 interrupt (TFIF20 or RFIF20 set)
  • 21 FIFO 21 interrupt (TFIF21 or RFIF21 set)
  • 22 FIFO 22 interrupt (TFIF22 or RFIF22 set)
  • 23 FIFO 23 interrupt (TFIF23 or RFIF23 set)
  • 24 FIFO 24 interrupt (TFIF24 or RFIF24 set)
  • 25 FIFO 25 interrupt (TFIF25 or RFIF25 set)
  • 26 FIFO 26 interrupt (TFIF26 or RFIF26 set)
  • 27 FIFO 27 interrupt (TFIF27 or RFIF27 set)
  • 28 FIFO 28 interrupt (TFIF28 or RFIF28 set)
  • 29 FIFO 29 interrupt (TFIF29 or RFIF29 set)
  • 30 FIFO 30 interrupt (TFIF30 or RFIF30 set)
  • 31 FIFO 31 interrupt (TFIF31 or RFIF31 set)
  • 64 No interrupt
  • 65 Error interrupt (CERRIF/IE)
  • 66 Wake-up interrupt (WAKIF/WAKIE)
  • 67 Receive FIFO overflow interrupt (any bit in CFDxRXOVIF set)
  • 68 Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
  • 69 RX/TX MAB overflow/underflow (RX: message received before previous message was saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE)
  • 70 CAN Timer Overflow (CTMRIF/IE)
  • 71 CAN module mode change Occurred (MODIF/IE)
  • 72 Invalid message occurred (IVMIF/IE)
  • 73 Transmit event FIFO interrupt (any bit in the CFDxTEFIF register is set)
  • 74 Transmit attempt interrupt (any bit in the CFDxTXATIF register is set)

CFD4INTInterrupt Register

Address
0xBF885070
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
FieldBitsWhat it does
WAKIE30Bus Wake Up Activity Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
CERRIE29CAN Bus Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SERRIE28System Error Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXOVIE27Receive Buffer Overflow Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXATIE26Transmit Attempt Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
SPICRCIE25
ECCIE24
TEFIE20Transmit Event FIFO Interrupt Enable bit
  • 1 Interrupts are enabled
MODIE19Mode Change Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TBCIE18CAN Timer Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
RXIE17Receive Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
TXIE16Transmit Object Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled
IVMIF15Invalid Message Interrupt Flag bit
  • 0 No invalid message interrupts are pending
  • 1 An invalid message interrupt is pending
WAKIF14Bus Wake Up Activity Interrupt Flag bit
  • 0 No wake-up interrupts are pending
  • 1 A wake-up interrupt is pending
CERRIF13CAN Bus Error Interrupt Flag bit
  • 0 No CAN bus error interrupts are pending
  • 1 A CAN bus error interrupt is pending
SERRIF12System Error Interrupt Flag bit
  • 0 No system error occurred
  • 1 A system error occurred (collision on dual-port RAM)
RXOVIF11Receive Object Overflow Interrupt Flag bit
  • 0 No receive object overflow has occurred
  • 1 Receive object overflow occurred
TXATIF10Transmit Attempt Interrupt Flag bit
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set
SPICRCIF9
ECCIF8
TEFIF4Transmit Event FIFO Interrupt Flag bit
  • 0 No receive buffer overflow has occurred
  • 1 Receive buffer overflow occurred
MODIF3CAN Mode Change Interrupt Flag bit
  • 0 No mode change occurred
  • 1 CAN module mode change occurred (OPMOD has changed to reflect the REQOP bits)
TBCIF2CAN Timer Overflow Interrupt Flag bit
  • 0 TBC did not overflow
  • 1 TBC has overflowed
RXIF1Receive Object Interrupt Flag bit
  • 0 No receive object interrupts pending
  • 1 Receive object interrupt pending
TXIF0Transmit Object Interrupt Flag bit
  • 0 No transmit object interrupts pending
  • 1 Transmit object interrupt pending
IVMIE31Invalid Message Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled

CFD4RXIFReceive Interrupt Status Register

Address
0xBF885080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFIF31:1Receive FIFO Interrupt Pending bits
  • 0 No enabled receive FIFO interrupts are pending
  • 1 One or more enabled receive FIFO interrupts are pending

CFD4TXIFTransmit Interrupt Status Register

Address
0xBF885090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFIF31:0Transmit FIFO/Transmit Queue Interrupt Pending bits
  • 0 No enabled transmit FIFO/Transmit Queue interrupt are pending
  • 1 One or more enabled transmit FIFO/Transmit Queue interrupts are pending

CFD4RXOVIFReceive Overflow Interrupt Status Register

Address
0xBF8850A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RFOVIF31:1Receive FIFO Overflow Interrupt Pending bits
  • 0 Interrupt not pending
  • 1 Interrupt is pending

CFD4TXATIFTransmit Attempt Interrupt Status Register

Address
0xBF8850B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TFATIF31:0Transmit FIFO/Transmit Queue Attempt Interrupt Pending bits
  • 0 No transmit FIFO interrupts are pending
  • 1 A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set

CFD4TXREQTransmit Request Register

Address
0xBF8850C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXREQ31:0

CFD4TRECTransmit/Receive Error Count Register

Address
0xBF8850D0
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
TXBO21Transmitter in Error State Bus Off bit (TERRCNT > 255)
  • 0 Indicates that transmit errors are less than 255
  • 1 Indicates that the number of transmit errors is greater than 255.
TXBP20Transmitter in Error State Bus Passive bit (TERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of transmit errors is greater than 127.
RXBP19Receiver in Error State Bus Passive bit (RERRCNT > 127)
  • 0 Indicates that transmit errors are less than or equal to 127
  • 1 Indicates that the number of receive errors is greater than 127.
TXWARN18Transmitter in Error State Warning bit (128 > TERRCNT > 95)
  • 0 Indicates that transmit errors are greater than or equal to 95
  • 1 Indicates that the number of transmit errors are less than 128
RXWARN17Receiver in Error State Warning bit (128 > RERRCNT > 95)
  • 0 Indicates that receive errors are greater than or equal to 95
  • 1 Indicates that the number of receives errors is less than 128
EWARN16Transmitter or Receiver is in Error State Warning bit
  • 0 No transmit or receive warnings
  • 1 TXWARN or RXWARN is set
TERRCNT15:8Transmit Error Counter bits
  • 0 No transmit errors
  • 1 1 transmit error
  • 254 254 Transmit errors
  • 255 Greater than or equal to 255 Transmit errors.
RERRCNT7:0Receive Error Counter bits
  • 0 No receive errors
  • 1 1 receive error
  • 254 254 receive errors
  • 255 Greater than or equal to 255 Receive errors

CFD4BDIAG0Bus Diagnostics Register 0

Address
0xBF8850E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DRERRCNT23:16
NTERRCNT15:8
NRERRCNT7:0
DTERRCNT31:24

CFD4BDIAG1Bus Diagnostics Register

Address
0xBF8850F0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
ESI30Error State Indicator (ESI) Flag Status bit
  • 0 ESI flag of a received CAN FD message was not set
  • 1 ESI flag of a received CAN FD message was set
DCRCERR29Data CRC Error Status bit
  • 0 No received message data CRC error occurred
  • 1 CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
DSTUFERR28Data Stuffing Error Status bit
  • 0 No data received message errors
  • 1 More than five equal bits in a sequence have occurred in a portion of a received message where this is not allowed
DFORMERR27Data Format Error Status bit
  • 0 No format errors occurred
  • 1 Data fixed format portion of a received frame has the wrong format
DBIT1ERR25Data Bit Logical 1 Error Status bit
  • 0 No data logical 1 bit transmission error occurred
  • 1 During the data transmission of a message (with the exception of the arbitration field)
DBIT0ERR24Data Bit Logical 0 Error Status bit
  • 0 No data logical 0 bit transmission error occurred
  • 1 During the data transmission of a message the monitored bus value was recessive. During Bus Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored.
NCRCERR21Nominal CRC Error Status bit
  • 0 No nominal CRC received message error occurred
  • 1 The CRC checksum of a nominal received message was incorrect.
NSTUFERR20Nominal Stuffing Error Status bit
  • 0 No nominal bit stuffing errors have occurred
  • 1 More than five equal bits in a sequence have occurred in a part of a nominal received message where this is not allowed
NFORMERR19Nominal Format Error Status bit
  • 0 No nominal format error occurred
  • 1 A fixed format portion of a nominal received frame has the wrong format
NACKERR18Not Acknowledged Error Status bit
  • 0 A transmitted message was acknowledged
  • 1 A transmitted message was not acknowledged
NBIT1ERR17Nominal Bit Logical 1 Error Status bit
  • 0 No nominal bit logical 1 error occurred
  • 1 During the transmission of a nominal message (with the exception of the arbitration field)
NBIT0ERR16Nominal Bit Logical 0 Error Status bit
  • 0 No nominal bit logical 0 error occurred
  • 1 During the transmission of a nominal message
EFMSGCNT15:0Error Free Message Counter Status bits
  • 0 0 error free messages since the last register read
  • 65535 65536 error free messages since the last register read
DLCMM31Data Length Code (DLC) Mismatch Status bit
  • 0 No payload size error occurred
  • 1 Payload size error. During a transmission or reception the Data Length Code exceeds the payload size of the FIFO element defined in the PLSIZE bits (CFDxFIFOCONn).

CFD4TEFCONTransmit Event FIFO Control Register

Address
0xBF885100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 message deep
  • 1 FIFO is 2 messages deep
  • 2 FIFO is 3 messages deep
  • 3 FIFO is 4 messages deep
  • 4 FIFO is 5 messages deep
  • 5 FIFO is 6 messages deep
  • 6 FIFO is 7 messages deep
  • 7 FIFO is 8 messages deep
  • 8 FIFO is 9 messages deep
  • 9 FIFO is 10 messages deep
  • 10 FIFO is 11 messages deep
  • 11 FIFO is 12 messages deep
  • 12 FIFO is 13 messages deep
  • 13 FIFO is 14 messages deep
  • 14 FIFO is 15 messages deep
  • 15 FIFO is 16 messages deep
  • 16 FIFO is 17 messages deep
  • 17 FIFO is 18 messages deep
  • 18 FIFO is 19 messages deep
  • 19 FIFO is 20 messages deep
  • 20 FIFO is 21 messages deep
  • 21 FIFO is 22 messages deep
  • 22 FIFO is 23 messages deep
  • 23 FIFO is 24 messages deep
  • 24 FIFO is 25 messages deep
  • 25 FIFO is 26 messages deep
  • 26 FIFO is 27 messages deep
  • 27 FIFO is 28 messages deep
  • 28 FIFO is 29 messages deep
  • 29 FIFO is 30 messages deep
  • 30 FIFO is 31 messages deep
  • 31 FIFO is 32 messages deep
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set
UINC8
TEFTSEN5Transmit Event FIFO Time Stamp Enable bit
  • 0 Do not time stamp elements in TEF
  • 1 Time stamp elements in TEF
TEFOVIE3Transmit Event FIFO Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TEFFIE2Transmit Event FIFO Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO full
  • 1 Interrupt enabled for FIFO full
TEFHIE1Transmit Event FIFO Half Full Interrupt Enable bit
  • 0 Interrupt disabled for FIFO half full
  • 1 Interrupt enabled for FIFO half full
TEFNEIE0Transmit Event FIFO Not Empty Interrupt Enable bit
  • 0 Interrupt disabled for FIFO not empty
  • 1 Interrupt enabled for FIFO not empty

CFD4TEFSTATransmit Event FIFO Status Register

Address
0xBF885110
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TEFOVIF3Transmit Event FIFO Overflow Interrupt Flag bit
  • 0 No overflow event has occurred
  • 1 Overflow event has occurred
TEFFIF2Transmit Event FIFO Full Interrupt Flag bit
  • 0 FIFO is not full
  • 1 FIFO is full
TEFHIF1Transmit Event FIFO Half Full Interrupt Flag bit
  • 0 FIFO is less than half full
  • 1 FIFO is greater than or equal to half full
TEFNEIF0Transmit Event FIFO Not Empty Interrupt Flag bit
  • 0 FIFO is empty
  • 1 FIFO is not empty (has at least one message)

CFD4TEFUATransmit Event FIFO User Address Register

Address
0xBF885120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TEFUA31:0

CFD4FIFOBAMessage Memory Base Address Register

Address
0xBF885130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOBA31:0

CFD4TXQCONTransmit Queue Control Register

Address
0xBF885140
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. The user application should poll whether this bit is clear before taking any action.
TXREQ9Message Send Request bit
  • 0 Clearing the bit to 0 while set will request a message abort.
  • 1 Requests sending a message; the bit will automatically clear when all the messages queued in the Transmit Queue are successfully sent
UINC8Increment Head/Tail bit
  • 0 FIFO head will not increment by a single message
  • 1 FIFO head will increment by a single message
TXEN7TX Enable
  • 1 Transmit Message Queue. This bit always reads as 1.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
TXQEIE2Transmit Queue Empty Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue empty
  • 1 Interrupt enabled for Transmit Queue empty
TXQNIE0Transmit Queue Not Full Interrupt Enable bit
  • 0 Interrupt disabled for Transmit Queue not full
  • 1 Interrupt enabled for Transmit Queue not full
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4TXQSTATransmit Queue Status Register

Address
0xBF885150
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
TXQCI12:8
TXABT7Message Aborted Status bit
  • 0 Message completed successfully
  • 1 Message was aborted
TXLARB6Message Lost Arbitration Status bit
  • 0 Message did not loose arbitration while being sent
  • 1 Message lost arbitration while being sent
TXERR5Error Detected During Transmission bit
  • 0 A bus error did not occur while the message was being sent
  • 1 A bus error occurred while the message was being sent
TXATIF4Transmit Attempts Exhausted Interrupt Pending bit
  • 0 Interrupt Not pending
  • 1 Interrupt pending
TXQEIF2Transmit Queue Empty Interrupt Flag bit
  • 0 Transmit Queue is not empty
  • 1 Transmit Queue is empty
TXQNIF0Transmit Queue Not Full Interrupt Flag bit
  • 0 Transmit Queue is full
  • 1 Transmit Queue is not full

CFD4TXQUATransmit Queue User Address Register

Address
0xBF885160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXQUA31:0

CFD4FIFOCON1FIFO Control Registe

Address
0xBF885170
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA1

Address
0xBF885180
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA1

Address
0xBF885190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON2FIFO Control Register

Address
0xBF8851A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA2

Address
0xBF8851B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA2

Address
0xBF8851C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON3FIFO Control Register

Address
0xBF8851D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA3

Address
0xBF8851E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA3

Address
0xBF8851F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON4FIFO Control Register

Address
0xBF885200
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA4

Address
0xBF885210
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA4

Address
0xBF885220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON5FIFO Control Register

Address
0xBF885230
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA5

Address
0xBF885240
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA5

Address
0xBF885250
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON6FIFO Control Register

Address
0xBF885260
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA6

Address
0xBF885270
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA6

Address
0xBF885280
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON7FIFO Control Register

Address
0xBF885290
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA7

Address
0xBF8852A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA7

Address
0xBF8852B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON8FIFO Control Register

Address
0xBF8852C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA8

Address
0xBF8852D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA8

Address
0xBF8852E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON9FIFO Control Register

Address
0xBF8852F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA9

Address
0xBF885300
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA9

Address
0xBF885310
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON10FIFO Control Register

Address
0xBF885320
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA10

Address
0xBF885330
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA10

Address
0xBF885340
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON11FIFO Control Registe

Address
0xBF885350
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA11

Address
0xBF885360
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA11

Address
0xBF885370
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON12FIFO Control Register

Address
0xBF885380
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA12

Address
0xBF885390
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA12

Address
0xBF8853A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON13FIFO Control Register

Address
0xBF8853B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA13

Address
0xBF8853C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA13

Address
0xBF8853D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON14FIFO Control Register

Address
0xBF8853E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA14

Address
0xBF8853F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA14

Address
0xBF885400
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON15FIFO Control Register

Address
0xBF885410
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA15

Address
0xBF885420
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA15

Address
0xBF885430
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON16FIFO Control Register

Address
0xBF885440
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA16

Address
0xBF885450
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA16

Address
0xBF885460
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON17FIFO Control Register

Address
0xBF885470
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA17

Address
0xBF885480
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA17

Address
0xBF885490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON18FIFO Control Register

Address
0xBF8854A0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA18

Address
0xBF8854B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA18

Address
0xBF8854C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON19FIFO Control Register

Address
0xBF8854D0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA19

Address
0xBF8854E0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA19

Address
0xBF8854F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON20FIFO Control Register

Address
0xBF885500
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA20

Address
0xBF885510
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA20

Address
0xBF885520
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON21FIFO Control Registe

Address
0xBF885530
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA21

Address
0xBF885540
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA21

Address
0xBF885550
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON22FIFO Control Register

Address
0xBF885560
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA22

Address
0xBF885570
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA22

Address
0xBF885580
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON23FIFO Control Register

Address
0xBF885590
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA23

Address
0xBF8855A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA23

Address
0xBF8855B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON24FIFO Control Register

Address
0xBF8855C0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA24

Address
0xBF8855D0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA24

Address
0xBF8855E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON25FIFO Control Register

Address
0xBF8855F0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA25

Address
0xBF885600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA25

Address
0xBF885610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON26FIFO Control Register

Address
0xBF885620
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA26

Address
0xBF885630
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA26

Address
0xBF885640
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON27FIFO Control Register

Address
0xBF885650
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA27

Address
0xBF885660
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA27

Address
0xBF885670
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON28FIFO Control Register

Address
0xBF885680
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA28

Address
0xBF885690
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA28

Address
0xBF8856A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON29FIFO Control Register

Address
0xBF8856B0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA29

Address
0xBF8856C0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA29

Address
0xBF8856D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON30FIFO Control Register

Address
0xBF8856E0
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA30

Address
0xBF8856F0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA30

Address
0xBF885700
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FIFOCON31FIFO Control Registe

Address
0xBF885710
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
FSIZE28:24FIFO Size bits
  • 0 FIFO is 1 Message deep
  • 1 FIFO is 2 Messages deep
  • 2 FIFO is 3 Messages deep
  • 3 FIFO is 4 Messages deep
  • 4 FIFO is 5 Messages deep
  • 5 FIFO is 6 Messages deep
  • 6 FIFO is 7 Messages deep
  • 7 FIFO is 8 Messages deep
  • 8 FIFO is 9 Messages deep
  • 9 FIFO is 10 Messages deep
  • 10 FIFO is 11 Messages deep
  • 11 FIFO is 12 Messages deep
  • 12 FIFO is 13 Messages deep
  • 13 FIFO is 14 Messages deep
  • 14 FIFO is 15 Messages deep
  • 15 FIFO is 16 Messages deep
  • 16 FIFO is 17 Messages deep
  • 17 FIFO is 18 Messages deep
  • 18 FIFO is 19 Messages deep
  • 19 FIFO is 20 Messages deep
  • 20 FIFO is 21 Messages deep
  • 21 FIFO is 22 Messages deep
  • 22 FIFO is 23 Messages deep
  • 23 FIFO is 24 Messages deep
  • 24 FIFO is 25 Messages deep
  • 25 FIFO is 26 Messages deep
  • 26 FIFO is 27 Messages deep
  • 27 FIFO is 28 Messages deep
  • 28 FIFO is 29 Messages deep
  • 29 FIFO is 30 Messages deep
  • 30 FIFO is 31 Messages deep
  • 31 FIFO is 32 Messages deep
TXAT22:21Retransmission Attempts bits
  • 0 Disable retransmission attempts
  • 1 Three retransmission attempts
  • 2 Unlimited number of retransmission attempts
  • 3 Unlimited number of retransmission attempts
TXPRI20:16Message Transmit Priority bits (EXPANDED)
  • 0 Lowest Message Priority
  • 1 Message priority 1
  • 2 Message priority 2
  • 3 Message priority 3
  • 4 Message priority 4
  • 5 Message priority 5
  • 6 Message priority 6
  • 7 Message priority 7
  • 8 Message priority 8
  • 9 Message priority 9
  • 10 Message priority 10
  • 11 Message priority 11
  • 12 Message priority 12
  • 13 Message priority 13
  • 14 Message priority 14
  • 15 Message priority 15
  • 16 Message priority 16
  • 17 Message priority 17
  • 18 Message priority 18
  • 19 Message priority 19
  • 20 Message priority 20
  • 21 Message priority 21
  • 22 Message priority 22
  • 23 Message priority 23
  • 24 Message priority 24
  • 25 Message priority 25
  • 26 Message priority 26
  • 27 Message priority 27
  • 28 Message priority 28
  • 29 Message priority 29
  • 30 Message priority 30
  • 31 Highest Message Priority
FRESET10FIFO Reset bit
  • 0 No effect
  • 1 FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ9Message Send Request bit
  • 0 (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect.
  • 1 (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC8Increment Head / Tail bit
  • 0 (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message
  • 1 (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN7TX / RX Buffer Selection bit
  • 0 Receive Message Object
  • 1 Transmit Message Object
RTREN6Auto RTR Enable bit
  • 0 When a remote transmit is received
  • 1 When a remote transmit is received
RXTSEN5Received Message Time Stamp Enable bit
  • 0 Dont capture time stamp.
  • 1 Capture time stamp in received message object in RAM.
TXATIE4Transmit Attempts Exhausted Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt
RXOVIE3Overflow Interrupt Enable bit
  • 0 Interrupt disabled for overflow event
  • 1 Interrupt enabled for overflow event
TFERFFIE2Transmit/Receive FIFO Empty/Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full
  • 1 (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE1Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full
  • 1 (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE0Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
  • 0 (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty
  • 1 (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE31:29Payload Size bits
  • 0 8 data bytes
  • 1 12 data bytes
  • 2 16 data bytes
  • 3 20 data bytes
  • 4 24 data bytes
  • 5 32 data bytes
  • 6 48 data bytes
  • 7 64 data bytes

CFD4FIFOSTA31

Address
0xBF885720
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
FIFOCI12:8
TXABT7
TXLARB6
TXERR5
TXATIF4
RXOVIF3
TFERFFIF2
TFHRFHIF1
TFNRFNIF0

CFD4FIFOUA31

Address
0xBF885730
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FIFOUA31:0

CFD4FLTCON0Filter Control Register

Address
0xBF885740
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F3BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F2BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F1BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN07Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F0BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the RX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON1Filter Control Registe

Address
0xBF885750
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F7BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F6BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F5BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN47Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F4BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON2Filter Control Register

Address
0xBF885760
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F11BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1023Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F10BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F9BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN87Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F8BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON3Filter Control Register

Address
0xBF885770
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F15BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1423Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F14BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1315Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F13BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN127Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F12BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1531Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON4Filter Control Register

Address
0xBF885780
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F19BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1823Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F18BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1715Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F17BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN167Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F16BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN1931Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON5Filter Control Register

Address
0xBF885790
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F23BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2223Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F22BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2115Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F21BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN207Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F20BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2331Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON6Filter Control Register

Address
0xBF8857A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F27BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2623Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F26BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2515Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F25BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN247Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F24BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2731Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTCON7Filter Control Register

Address
0xBF8857B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
F31BP28:24Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3023Enable Filter nto Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F30BP20:16Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN2915Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F29BP12:8Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN287Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled
F28BP4:0Pointer to Object when Filter n hits bits
  • 0 Reserved. Object 0 is the TX Queue and cannot receive messages.
  • 1 Message matching filter is stored in Object 1
  • 2 Message matching filter is stored in Object 2
  • 3 Message matching filter is stored in Object 3
  • 4 Message matching filter is stored in Object 4
  • 5 Message matching filter is stored in Object 5
  • 6 Message matching filter is stored in Object 6
  • 7 Message matching filter is stored in Object 7
  • 8 Message matching filter is stored in Object 8
  • 9 Message matching filter is stored in Object 9
  • 10 Message matching filter is stored in Object 10
  • 11 Message matching filter is stored in Object 11
  • 12 Message matching filter is stored in Object 12
  • 13 Message matching filter is stored in Object 13
  • 14 Message matching filter is stored in Object 14
  • 15 Message matching filter is stored in Object 15
  • 16 Message matching filter is stored in Object 16
  • 17 Message matching filter is stored in Object 17
  • 18 Message matching filter is stored in Object 18
  • 19 Message matching filter is stored in Object 19
  • 20 Message matching filter is stored in Object 20
  • 21 Message matching filter is stored in Object 21
  • 22 Message matching filter is stored in Object 22
  • 23 Message matching filter is stored in Object 23
  • 24 Message matching filter is stored in Object 24
  • 25 Message matching filter is stored in Object 25
  • 26 Message matching filter is stored in Object 26
  • 27 Message matching filter is stored in Object 27
  • 28 Message matching filter is stored in Object 28
  • 29 Message matching filter is stored in Object 29
  • 30 Message matching filter is stored in Object 30
  • 31 Message matching filter is stored in Object 31
FLTEN3131Enable Filter n to Accept Messages bits
  • 0 Filter is disabled
  • 1 Filter is enabled

CFD4FLTOBJ0

Address
0xBF8857C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit
EID28:11
SID10:0

CFD4MASK0

Address
0xBF8857D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ1Filter Object Registe

Address
0xBF8857E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK1Filter Object Registe

Address
0xBF8857F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ2Filter Object Register

Address
0xBF885800
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK2

Address
0xBF885810
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ3Filter Object Register

Address
0xBF885820
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK3

Address
0xBF885830
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30NO_SUCH_FIELD
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129NO_SUCH_FIELD
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ4Filter Object Register

Address
0xBF885840
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK4Filter Object Register

Address
0xBF885850
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ5Filter Object Register

Address
0xBF885860
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK5Filter Object Register

Address
0xBF885870
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ6Filter Object Register

Address
0xBF885880
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK6Filter Object Register

Address
0xBF885890
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ7Filter Object Register

Address
0xBF8858A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK7Filter Object Register

Address
0xBF8858B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ8Filter Object Register

Address
0xBF8858C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK8Filter Object Register

Address
0xBF8858D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ9Filter Object Register

Address
0xBF8858E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK9Filter Object Register

Address
0xBF8858F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ10Filter Object Register

Address
0xBF885900
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK10Filter Object Register

Address
0xBF885910
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ11Filter Object Registe

Address
0xBF885920
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK11Filter Object Registe

Address
0xBF885930
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ12Filter Object Register

Address
0xBF885940
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK12Filter Object Register

Address
0xBF885950
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ13Filter Object Register

Address
0xBF885960
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK13Filter Object Register

Address
0xBF885970
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ14Filter Object Register

Address
0xBF885980
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK14Filter Object Register

Address
0xBF885990
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ15Filter Object Register

Address
0xBF8859A0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK15Filter Object Register

Address
0xBF8859B0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ16Filter Object Register

Address
0xBF8859C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
  • 0 (If MIDE is 1) Match only messages with standard identifier addresses
  • 1 (If MIDE is 1) Match only messages with extended identifier addresses
SID1129Standard Identifier Filter bit
  • 0 Do not use extended standard Identifier bits
  • 1 Extended standard identifier to 12-bit (i.e.
EID28:11
SID10:0

CFD4MASK16Filter Object Register

Address
0xBF8859D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ17Filter Object Register

Address
0xBF8859E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK17Filter Object Register

Address
0xBF8859F0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ18Filter Object Register

Address
0xBF885A00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK18Filter Object Register

Address
0xBF885A10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ19Filter Object Register

Address
0xBF885A20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK19Filter Object Register

Address
0xBF885A30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ20Filter Object Register

Address
0xBF885A40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK20Filter Object Register

Address
0xBF885A50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ22Filter Object Register

Address
0xBF885A80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK22Filter Object Register

Address
0xBF885A90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ23Filter Object Register

Address
0xBF885AA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK23Filter Object Register

Address
0xBF885AB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ24Filter Object Register

Address
0xBF885AC0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK24Filter Object Register

Address
0xBF885AD0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ25Filter Object Register

Address
0xBF885AE0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK25Filter Object Register

Address
0xBF885AF0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ26Filter Object Register

Address
0xBF885B00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK26Filter Object Register

Address
0xBF885B10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ27Filter Object Register

Address
0xBF885B20
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK27Filter Object Register

Address
0xBF885B30
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ28Filter Object Register

Address
0xBF885B40
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK28Filter Object Register

Address
0xBF885B50
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ29Filter Object Register

Address
0xBF885B60
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK29Filter Object Register

Address
0xBF885B70
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ30Filter Object Register

Address
0xBF885B80
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK30Filter Object Register

Address
0xBF885B90
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0

CFD4FLTOBJ31Filter Object Register

Address
0xBF885BA0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
EXIDE30Extended Identifier Enable bit
SID1129Standard Identifier Filter bit
EID28:11
SID10:0

CFD4MASK31Filter Object Register

Address
0xBF885BB0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MIDE30Identifier Receive Mode bit
  • 0 Match either standard or extended address message if filters match (i.e.
  • 1 Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID1129Standard Identifier Mask bit
  • 0 Do not enable extended standard identifier mask (MSID)
  • 1 Enable extended standard identifier mask to 12 bits (MSID
MEID28:11
MSID10:0