The 4 registers of OSC (Oscillator and clocks), from 0xBF802680, with their reset value and every field. The PIC32MM0256GPM028 has 419 registers in 52 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
OSC Oscillator and clocks
OSCCONOscillator Control Register
Address
0xBF802680
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
FRCDIV
26:24
Internal Fast RC Oscillator Clock Divider bits
0 FRC divided by 1 (default setting)
1 FRC divided by 2
2 FRC divided by 4
3 FRC divided by 8
4 FRC divided by 16
5 FRC divided by 32
6 FRC divided by 64
7 FRC divided by 256
DRMEN
23
SLP2SPD
21
COSC
14:12
Current Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
1 System PLL (SPLL)
2 Primary Oscillator (POSC) (HS or EC)
3 Reserved
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Reserved
7 Reserved
NOSC
10:8
New Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
1 System PLL (SPLL)
2 Primary Oscillator (POSC) (HS or EC)
3 Reserved
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Reserved
7 Reserved
CLKLOCK
7
Clock Selection Lock Enable bit
0 Clock and PLL selections are not locked and may be modified
1 Clock and PLL selections are locked
SLPEN
4
Sleep Mode Enable bit
0 Device will enter Idle mode when a WAIT instruction is executed
1 Device will enter Sleep mode when a WAIT instruction is executed
CF
3
Clock Fail Detect bit
0 No clock failure has been detected
1 FSCM has detected a clock failure
SOSCEN
1
Secondary Oscillator Enable bit
0 Disable Secondary Oscillator
1 Enable Secondary Oscillator
OSWEN
0
Oscillator Switch Enable bit
0 Oscillator switch is complete
1 Initiate an oscillator switch to selection specified by NOSC bits
SPLLCONSystem PLL Control Register
Address
0xBF8026A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PLLODIV
26:24
System PLL Output Clock Divider bits
0 PLL Divide by 1
1 PLL Divide by 2
2 PLL Divide by 4
3 PLL Divide by 8
4 PLL Divide by 16
5 PLL Divide by 32
6 PLL Divide by 64
7 PLL Divide by 256
PLLMULT
22:16
System PLL Multiplier bits
0 Multiply by 2
1 Multiply by 3
2 Multiply by 4
3 Multiply by 6
4 Multiply by 8
5 Multiply by 12
6 Multiply by 24
PLLICLK
7
System PLL Input Clock Source bit
0 POSC is selected as the input to the System PLL
1 FRC is selected as the input to the System PLL
CLKSTATOscillator Clock Status Register
Address
0xBF802770
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
SPLLRDY
7
System PLL (SPLL) Ready Status bit
0 SPLL is not ready
1 SPLL is ready
LPRCRDY
5
Low-Power RC (LPRC) Oscillator Ready Status bit
0 LPRC is disabled or not operating
1 LPRC is stable and ready
SOSCRDY
4
Secondary Oscillator (SOSC) Ready Status bit
0 SOSC is disabled or not operating
1 SOSC is stable and ready
POSCRDY
2
Primary Oscillator (POSC) Ready Status bit
0 POSC is disabled or not operating
1 POSC is stable and ready
SPDIVRDY
1
System PLL Ready Status bit
0 Divided System PLL is not ready
1 Divided System PLL is ready
FRCRDY
0
Fast RC (FRC) Oscillator Ready Status bit
0 FRC is disabled for not operating
1 FRC is stable and ready
OSCTUNFRC Tuning Register
Address
0xBF802880
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
SIDL
13
SRC
12
LOCK
11
POL
10
OR
9
ORPOL
8
TUN
5:0
FRC Oscillator Tuning bits
0 Center frequency; Oscillator runs at nominal frequency (8 MHz)
BETA