PIC32MX220F032B registers

All 326 registers by peripheral, at the virtual address XC32 and the datasheet's register tables use (the SFRs from 0xBF800000), with their reset value and every field.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

WDT Watchdog timer

WDTCONWatchdog Timer Control Register

Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ON15Watchdog Timer Enable bit
  • 0 Disable the WDT if it was enabled in software
  • 1 Enables the WDT if it is not enabled by the device configuration
SWDTPS6:2
WDTWINEN1Watchdog Timer Window Enable bit
  • 0 Disable windowed Watchdog Timer
  • 1 Enable windowed Watchdog Timer
WDTCLR0Watchdog Timer Reset bit
  • 0 Software cannot force this bit to a 0
  • 1 Writing a 1 will clear the WDT

RTCC Real-time clock and calendar

RTCCONRTC Control Register

Address
0xBF800200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
CAL25:16RTC Drift Calibration bits
  • 0 No adjustment
  • 1 Minimum positive adjustment, adds 1 RTC clock pulse every one minute
  • 511 Maximum positive adjustment, adds 511 RTC clock pulses every one minute
  • 512 Maximum negative adjustment, subtracts 512 clock pulses every one minute
  • 1023 Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
ON15RTCC On bit
  • 0 RTCC module is disabled
  • 1 RTCC module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue normal operation in Idle mode
  • 1 Disables the PBCLK to the RTCC when CPU enters in Idle mode
RTSECSEL7RTCC Seconds Clock Output Select bit
  • 0 RTCC Alarm Pulse is selected for the RTCC pin
  • 1 RTCC Seconds Clock is selected for the RTCC pin
RTCCLKON6RTCC Clock Enable Status bit
  • 0 RTCC Clock is not running
  • 1 RTCC Clock is actively running
RTCWREN3RTC Value Registers Write Enable bit
  • 0 RTC Value registers are locked out from being written to by the user
  • 1 RTC Value registers can be written to by the user
RTCSYNC2RTCC Value Registers Read Synchronization bit
  • 0 RTC Value registers can be read without concern about a rollover ripple
  • 1 RTC Value registers can change while reading due to a rollover ripple that results in an invalid data read
HALFSEC1Half-Second Status bit
  • 0 First half period of a second
  • 1 Second half period of a second
RTCOE0RTCC Output Enable bit
  • 0 RTCC clock output is disabled
  • 1 RTCC clock output is enabled clock presented onto an I/O

RTCALRMRTC ALARM Control Register

Address
0xBF800210
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ALRMEN15Alarm Enable bit
  • 0 Alarm is disabled
  • 1 Alarm is enabled
CHIME14Chime Enable bit
  • 0 Chime is disabled ARPT(7:0) stops once it reaches 0x00
  • 1 Chime is enabled ARPT(7:0) is allowed to rollover from 0x00 to 0xFF
PIV13Alarm Pulse Initial Value bit
  • 0 (When ALRMEN = 0) Alarm pulse low / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
  • 1 (When ALRMEN = 0) Alarm pulse high / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
ALRMSYNC12Alarm Sync bit
  • 0 ARPT(7:0) and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 RTC clocks away from a half-second rollover
  • 1 ARPT(7:0) and ALRMEN may change as a result of a half second rollover during a read.
AMASK11:8Alarm Mask Configuration bits
  • 0 Every half-second
  • 1 Every second
  • 2 Every 10 seconds
  • 3 Every minute
  • 4 Every 10 minutes
  • 5 Every hour
  • 6 Once a day
  • 7 Once a week
  • 8 Once a month
  • 9 Once a year (except when configured for February 29
  • 10 Reserved; do not use
  • 11 Reserved; do not use
  • 12 Reserved; do not use
  • 13 Reserved; do not use
  • 14 Reserved; do not use
  • 15 Reserved; do not use
ARPT7:0Alarm Repeat Counter Value bits
  • 0 Alarm will trigger 1 times
  • 1 Alarm will trigger 2 times
  • 2 Alarm will trigger 3 times
  • 3 Alarm will trigger 4 times
  • 4 Alarm will trigger 5 times
  • 5 Alarm will trigger 6 times
  • 6 Alarm will trigger 7 times
  • 7 Alarm will trigger 8 times
  • 8 Alarm will trigger 9 times
  • 9 Alarm will trigger 10 times
  • 10 Alarm will trigger 11 times
  • 11 Alarm will trigger 12 times
  • 12 Alarm will trigger 13 times
  • 13 Alarm will trigger 14 times
  • 14 Alarm will trigger 15 times
  • 15 Alarm will trigger 16 times
  • 16 Alarm will trigger 17 times
  • 17 Alarm will trigger 18 times
  • 18 Alarm will trigger 19 times
  • 19 Alarm will trigger 20 times
  • 20 Alarm will trigger 21 times
  • 21 Alarm will trigger 22 times
  • 22 Alarm will trigger 23 times
  • 23 Alarm will trigger 24 times
  • 24 Alarm will trigger 25 times
  • 25 Alarm will trigger 26 times
  • 26 Alarm will trigger 27 times
  • 27 Alarm will trigger 28 times
  • 28 Alarm will trigger 29 times
  • 29 Alarm will trigger 30 times
  • 30 Alarm will trigger 31 times
  • 31 Alarm will trigger 32 times
  • 32 Alarm will trigger 33 times
  • 33 Alarm will trigger 34 times
  • 34 Alarm will trigger 35 times
  • 35 Alarm will trigger 36 times
  • 36 Alarm will trigger 37 times
  • 37 Alarm will trigger 38 times
  • 38 Alarm will trigger 39 times
  • 39 Alarm will trigger 40 times
  • 40 Alarm will trigger 41 times
  • 41 Alarm will trigger 42 times
  • 42 Alarm will trigger 43 times
  • 43 Alarm will trigger 44 times
  • 44 Alarm will trigger 45 times
  • 45 Alarm will trigger 46 times
  • 46 Alarm will trigger 47 times
  • 47 Alarm will trigger 48 times
  • 48 Alarm will trigger 49 times
  • 49 Alarm will trigger 50 times
  • 50 Alarm will trigger 51 times
  • 51 Alarm will trigger 52 times
  • 52 Alarm will trigger 53 times
  • 53 Alarm will trigger 54 times
  • 54 Alarm will trigger 55 times
  • 55 Alarm will trigger 56 times
  • 56 Alarm will trigger 57 times
  • 57 Alarm will trigger 58 times
  • 58 Alarm will trigger 59 times
  • 59 Alarm will trigger 60 times
  • 60 Alarm will trigger 61 times
  • 61 Alarm will trigger 62 times
  • 62 Alarm will trigger 63 times
  • 63 Alarm will trigger 64 times
  • 64 Alarm will trigger 65 times
  • 65 Alarm will trigger 66 times
  • 66 Alarm will trigger 67 times
  • 67 Alarm will trigger 68 times
  • 68 Alarm will trigger 69 times
  • 69 Alarm will trigger 70 times
  • 70 Alarm will trigger 71 times
  • 71 Alarm will trigger 72 times
  • 72 Alarm will trigger 73 times
  • 73 Alarm will trigger 74 times
  • 74 Alarm will trigger 75 times
  • 75 Alarm will trigger 76 times
  • 76 Alarm will trigger 77 times
  • 77 Alarm will trigger 78 times
  • 78 Alarm will trigger 79 times
  • 79 Alarm will trigger 80 times
  • 80 Alarm will trigger 81 times
  • 81 Alarm will trigger 82 times
  • 82 Alarm will trigger 83 times
  • 83 Alarm will trigger 84 times
  • 84 Alarm will trigger 85 times
  • 85 Alarm will trigger 86 times
  • 86 Alarm will trigger 87 times
  • 87 Alarm will trigger 88 times
  • 88 Alarm will trigger 89 times
  • 89 Alarm will trigger 90 times
  • 90 Alarm will trigger 91 times
  • 91 Alarm will trigger 92 times
  • 92 Alarm will trigger 93 times
  • 93 Alarm will trigger 94 times
  • 94 Alarm will trigger 95 times
  • 95 Alarm will trigger 96 times
  • 96 Alarm will trigger 97 times
  • 97 Alarm will trigger 98 times
  • 98 Alarm will trigger 99 times
  • 99 Alarm will trigger 100 times
  • 100 Alarm will trigger 101 times
  • 101 Alarm will trigger 102 times
  • 102 Alarm will trigger 103 times
  • 103 Alarm will trigger 104 times
  • 104 Alarm will trigger 105 times
  • 105 Alarm will trigger 106 times
  • 106 Alarm will trigger 107 times
  • 107 Alarm will trigger 108 times
  • 108 Alarm will trigger 109 times
  • 109 Alarm will trigger 110 times
  • 110 Alarm will trigger 111 times
  • 111 Alarm will trigger 112 times
  • 112 Alarm will trigger 113 times
  • 113 Alarm will trigger 114 times
  • 114 Alarm will trigger 115 times
  • 115 Alarm will trigger 116 times
  • 116 Alarm will trigger 117 times
  • 117 Alarm will trigger 118 times
  • 118 Alarm will trigger 119 times
  • 119 Alarm will trigger 120 times
  • 120 Alarm will trigger 121 times
  • 121 Alarm will trigger 122 times
  • 122 Alarm will trigger 123 times
  • 123 Alarm will trigger 124 times
  • 124 Alarm will trigger 125 times
  • 125 Alarm will trigger 126 times
  • 126 Alarm will trigger 127 times
  • 127 Alarm will trigger 128 times
  • 128 Alarm will trigger 129 times
  • 129 Alarm will trigger 130 times
  • 130 Alarm will trigger 131 times
  • 131 Alarm will trigger 132 times
  • 132 Alarm will trigger 133 times
  • 133 Alarm will trigger 134 times
  • 134 Alarm will trigger 135 times
  • 135 Alarm will trigger 136 times
  • 136 Alarm will trigger 137 times
  • 137 Alarm will trigger 138 times
  • 138 Alarm will trigger 139 times
  • 139 Alarm will trigger 140 times
  • 140 Alarm will trigger 141 times
  • 141 Alarm will trigger 142 times
  • 142 Alarm will trigger 143 times
  • 143 Alarm will trigger 144 times
  • 144 Alarm will trigger 145 times
  • 145 Alarm will trigger 146 times
  • 146 Alarm will trigger 147 times
  • 147 Alarm will trigger 148 times
  • 148 Alarm will trigger 149 times
  • 149 Alarm will trigger 150 times
  • 150 Alarm will trigger 151 times
  • 151 Alarm will trigger 152 times
  • 152 Alarm will trigger 153 times
  • 153 Alarm will trigger 154 times
  • 154 Alarm will trigger 155 times
  • 155 Alarm will trigger 156 times
  • 156 Alarm will trigger 157 times
  • 157 Alarm will trigger 158 times
  • 158 Alarm will trigger 159 times
  • 159 Alarm will trigger 160 times
  • 160 Alarm will trigger 161 times
  • 161 Alarm will trigger 162 times
  • 162 Alarm will trigger 163 times
  • 163 Alarm will trigger 164 times
  • 164 Alarm will trigger 165 times
  • 165 Alarm will trigger 166 times
  • 166 Alarm will trigger 167 times
  • 167 Alarm will trigger 168 times
  • 168 Alarm will trigger 169 times
  • 169 Alarm will trigger 170 times
  • 170 Alarm will trigger 171 times
  • 171 Alarm will trigger 172 times
  • 172 Alarm will trigger 173 times
  • 173 Alarm will trigger 174 times
  • 174 Alarm will trigger 175 times
  • 175 Alarm will trigger 176 times
  • 176 Alarm will trigger 177 times
  • 177 Alarm will trigger 178 times
  • 178 Alarm will trigger 179 times
  • 179 Alarm will trigger 180 times
  • 180 Alarm will trigger 181 times
  • 181 Alarm will trigger 182 times
  • 182 Alarm will trigger 183 times
  • 183 Alarm will trigger 184 times
  • 184 Alarm will trigger 185 times
  • 185 Alarm will trigger 186 times
  • 186 Alarm will trigger 187 times
  • 187 Alarm will trigger 188 times
  • 188 Alarm will trigger 189 times
  • 189 Alarm will trigger 190 times
  • 190 Alarm will trigger 191 times
  • 191 Alarm will trigger 192 times
  • 192 Alarm will trigger 193 times
  • 193 Alarm will trigger 194 times
  • 194 Alarm will trigger 195 times
  • 195 Alarm will trigger 196 times
  • 196 Alarm will trigger 197 times
  • 197 Alarm will trigger 198 times
  • 198 Alarm will trigger 199 times
  • 199 Alarm will trigger 200 times
  • 200 Alarm will trigger 201 times
  • 201 Alarm will trigger 202 times
  • 202 Alarm will trigger 203 times
  • 203 Alarm will trigger 204 times
  • 204 Alarm will trigger 205 times
  • 205 Alarm will trigger 206 times
  • 206 Alarm will trigger 207 times
  • 207 Alarm will trigger 208 times
  • 208 Alarm will trigger 209 times
  • 209 Alarm will trigger 210 times
  • 210 Alarm will trigger 211 times
  • 211 Alarm will trigger 212 times
  • 212 Alarm will trigger 213 times
  • 213 Alarm will trigger 214 times
  • 214 Alarm will trigger 215 times
  • 215 Alarm will trigger 216 times
  • 216 Alarm will trigger 217 times
  • 217 Alarm will trigger 218 times
  • 218 Alarm will trigger 219 times
  • 219 Alarm will trigger 220 times
  • 220 Alarm will trigger 221 times
  • 221 Alarm will trigger 222 times
  • 222 Alarm will trigger 223 times
  • 223 Alarm will trigger 224 times
  • 224 Alarm will trigger 225 times
  • 225 Alarm will trigger 226 times
  • 226 Alarm will trigger 227 times
  • 227 Alarm will trigger 228 times
  • 228 Alarm will trigger 229 times
  • 229 Alarm will trigger 230 times
  • 230 Alarm will trigger 231 times
  • 231 Alarm will trigger 232 times
  • 232 Alarm will trigger 233 times
  • 233 Alarm will trigger 234 times
  • 234 Alarm will trigger 235 times
  • 235 Alarm will trigger 236 times
  • 236 Alarm will trigger 237 times
  • 237 Alarm will trigger 238 times
  • 238 Alarm will trigger 239 times
  • 239 Alarm will trigger 240 times
  • 240 Alarm will trigger 241 times
  • 241 Alarm will trigger 242 times
  • 242 Alarm will trigger 243 times
  • 243 Alarm will trigger 244 times
  • 244 Alarm will trigger 245 times
  • 245 Alarm will trigger 246 times
  • 246 Alarm will trigger 247 times
  • 247 Alarm will trigger 248 times
  • 248 Alarm will trigger 249 times
  • 249 Alarm will trigger 250 times
  • 250 Alarm will trigger 251 times
  • 251 Alarm will trigger 252 times
  • 252 Alarm will trigger 253 times
  • 253 Alarm will trigger 254 times
  • 254 Alarm will trigger 255 times
  • 255 Alarm will trigger 256 times

RTCTIMERTC Time Value Register

Address
0xBF800220
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
HR0127:24
MIN1023:20
MIN0119:16
SEC1015:12
SEC0111:8
HR1031:28

RTCDATERTC Date Value Register

Address
0xBF800230
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
YEAR0127:24
MONTH1023:20
MONTH0119:16
DAY1015:12
DAY0111:8
WDAY013:0
YEAR1031:28

ALRMTIMEAlarm Time Value Register

Address
0xBF800240
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
HR0127:24
MIN1023:20
MIN0119:16
SEC1015:12
SEC0111:8
HR1031:28

ALRMDATEAlarm Date Value Register

Address
0xBF800250
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
MONTH1023:20
MONTH0119:16
DAY1015:12
DAY0111:8
WDAY013:0

TMR1 Timer 1

T1CONTYPE A TIMER CONTROL REGISTER

Address
0xBF800600
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
ON15Timer On bit
  • 0 Timer is disabled
  • 1 Timer is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation even in Idle mode
  • 1 Discontinue operation when device enters Idle mode
TWDIS12Asynchronous Timer Write Disable bit
  • 0 Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
  • 1 Writes to TMR1 are ignored until pending write operation completes
TWIP11Asynchronous Timer Write in Progress bit
  • 0 (In Asynchronous Timer mode) Asynchronous write to TMR1 register complete / (in synchronous mode) read as 0
  • 1 (In Asynchronous Timer mode) Asynchronous write to TMR1 register in progress / (in synchronous mode) read as 0
TGATE7Timer Gated Time Accumulation Enable bit
  • 0 (When TCS is 0) Gated time accumulation is disabled / (When TCS is 1) bit is ignored
  • 1 (When TCS is 0) Gated time accumulation is enabled / (When TCS is 1) bit is ignored
TCKPS5:4Timer Input Clock Prescale Select bits
  • 0 1:1 prescale value
  • 1 1:8 prescale value
  • 2 1:64 prescale value
  • 3 1:256 prescale value
TSYNC2Timer External Clock Input Synchronization Selection bit
  • 0 (When TCS is 1) External clock input is not synchronized / (When TCS is 0) bit is ignored
  • 1 (When TCS is 1) External clock input is synchronized / (When TCS is 0) bit is ignored
TCS1Timer Clock Source Select bit
  • 0 Internal peripheral clock
  • 1 External clock from T1CKI pin

TMR1

Address
0xBF800610
Reset
0x00000000
Access
read/write
Size
32-bit

PR1

Address
0xBF800620
Reset
0x0000FFFF
Access
read/write
Size
32-bit

TMR2 Timer 2

T2CONType B Timer Control Register

Address
0xBF800800
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Timer On bit
  • 0 Module is disabled
  • 1 Module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation even in Idle mode
  • 1 Discontinue operation when device enters Idle mode
TGATE7Timer Gated Time Accumulation Enable bit
  • 0 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is disabled
  • 1 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is enabled
TCKPS6:4Timer Input Clock Prescale Select bits
  • 0 1:1 prescale value
  • 1 1:2 prescale value
  • 2 1:4 prescale value
  • 3 1:8 prescale value
  • 4 1:16 prescale value
  • 5 1:32 prescale value
  • 6 1:64 prescale value
  • 7 1:256 prescale value
T32332-Bit Timer Mode Select bit
  • 0 Odd numbered and even numbered timers form a separate 16-bit timer
  • 1 Odd numbered and even numbered timers form a 32-bit timer
TCS1Timer Clock Source Select bit
  • 0 Internal peripheral clock
  • 1 External clock from TxCK pin

TMR2

Address
0xBF800810
Reset
0x00000000
Access
read/write
Size
32-bit

PR2

Address
0xBF800820
Reset
0x0000FFFF
Access
read/write
Size
32-bit

TMR3 Timer 3

T3CONType B Timer Control Register

Address
0xBF800A00
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ON15Timer On bit
  • 0 Module is disabled
  • 1 Module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation even in Idle mode
  • 1 Discontinue operation when device enters Idle mode
TGATE7Timer Gated Time Accumulation Enable bit
  • 0 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is disabled
  • 1 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is enabled
TCKPS6:4Timer Input Clock Prescale Select bits
  • 0 1:1 prescale value
  • 1 1:2 prescale value
  • 2 1:4 prescale value
  • 3 1:8 prescale value
  • 4 1:16 prescale value
  • 5 1:32 prescale value
  • 6 1:64 prescale value
  • 7 1:256 prescale value
TCS1Timer Clock Source Select bit
  • 0 Internal peripheral clock
  • 1 External clock from TxCK pin

TMR3

Address
0xBF800A10
Reset
0x00000000
Access
read/write
Size
32-bit

PR3

Address
0xBF800A20
Reset
0x0000FFFF
Access
read/write
Size
32-bit

TMR4 Timer 4

T4CONType B Timer Control Register

Address
0xBF800C00
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Timer On bit
  • 0 Module is disabled
  • 1 Module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation even in Idle mode
  • 1 Discontinue operation when device enters Idle mode
TGATE7Timer Gated Time Accumulation Enable bit
  • 0 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is disabled
  • 1 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is enabled
TCKPS6:4Timer Input Clock Prescale Select bits
  • 0 1:1 prescale value
  • 1 1:2 prescale value
  • 2 1:4 prescale value
  • 3 1:8 prescale value
  • 4 1:16 prescale value
  • 5 1:32 prescale value
  • 6 1:64 prescale value
  • 7 1:256 prescale value
T32332-Bit Timer Mode Select bit
  • 0 Odd numbered and even numbered timers form a separate 16-bit timer
  • 1 Odd numbered and even numbered timers form a 32-bit timer
TCS1Timer Clock Source Select bit
  • 0 Internal peripheral clock
  • 1 External clock from TxCK pin

TMR4

Address
0xBF800C10
Reset
0x00000000
Access
read/write
Size
32-bit

PR4

Address
0xBF800C20
Reset
0x0000FFFF
Access
read/write
Size
32-bit

TMR5 Timer 5

T5CONType B Timer Control Register

Address
0xBF800E00
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ON15Timer On bit
  • 0 Module is disabled
  • 1 Module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation even in Idle mode
  • 1 Discontinue operation when device enters Idle mode
TGATE7Timer Gated Time Accumulation Enable bit
  • 0 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is disabled
  • 1 (When TCS is 1): This bit is ignored and is read as 0 / (When TCS=0): Gated time accumulation is enabled
TCKPS6:4Timer Input Clock Prescale Select bits
  • 0 1:1 prescale value
  • 1 1:2 prescale value
  • 2 1:4 prescale value
  • 3 1:8 prescale value
  • 4 1:16 prescale value
  • 5 1:32 prescale value
  • 6 1:64 prescale value
  • 7 1:256 prescale value
TCS1Timer Clock Source Select bit
  • 0 Internal peripheral clock
  • 1 External clock from TxCK pin

TMR5

Address
0xBF800E10
Reset
0x00000000
Access
read/write
Size
32-bit

PR5

Address
0xBF800E20
Reset
0x0000FFFF
Access
read/write
Size
32-bit

IC1 Input capture 1

IC1CONInput Capture 1 Control Register

Address
0xBF802000
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ON15Input Capture Module Enable bit
  • 0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
  • 1 Module is enabled
SIDL13Stop in Idle Control bit
  • 0 Continue to operate in Idle mode
  • 1 Halt in Idle mode
FEDGE9First Capture Edge Select bit
  • 0 Capture falling edge first
  • 1 Capture rising edge first
C32832-bit Capture Select bit
  • 0 16-bit timer resource capture
  • 1 32-bit timer resource capture
ICTMR7Timer Select bit
  • 0 Timer3 is the counter source for capture
  • 1 Timer2 is the counter source for capture
ICI6:5Interrupt Control bits
  • 0 Interrupt on every capture event
  • 1 Interrupt on every second capture event
  • 2 Interrupt on every third capture event
  • 3 Interrupt on every fourth capture event
ICOV4Input Capture Overflow Status Flag bit (read-only)
  • 0 No input capture overflow has occurred
  • 1 Input capture overflow has occurred
ICBNE3Input Capture Buffer Not Empty Status bit (read-only)
  • 0 Input capture buffer is empty
  • 1 Input capture buffer is not empty; at least one more capture value can be read
ICM2:0Input Capture Mode Select bits
  • 0 Input Capture module is disabled
  • 1 Edge Detect mode every edge (rising and falling)
  • 2 Simple Capture Event mode every falling edge
  • 3 Simple Capture Event mode every rising edge
  • 4 Prescaled Capture Event mode every fourth rising edge
  • 5 Prescaled Capture Event mode every sixteenth rising edge
  • 6 Simple Capture Event mode every edge
  • 7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

IC1BUF

Address
0xBF802010
Reset
0x00000000
Access
read only
Size
32-bit

IC2 Input capture 2

IC2CONInput Capture 1 Control Register

Address
0xBF802200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ON15Input Capture Module Enable bit
  • 0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
  • 1 Module is enabled
SIDL13Stop in Idle Control bit
  • 0 Continue to operate in Idle mode
  • 1 Halt in Idle mode
FEDGE9First Capture Edge Select bit
  • 0 Capture falling edge first
  • 1 Capture rising edge first
C32832-bit Capture Select bit
  • 0 16-bit timer resource capture
  • 1 32-bit timer resource capture
ICTMR7Timer Select bit
  • 0 Timer3 is the counter source for capture
  • 1 Timer2 is the counter source for capture
ICI6:5Interrupt Control bits
  • 0 Interrupt on every capture event
  • 1 Interrupt on every second capture event
  • 2 Interrupt on every third capture event
  • 3 Interrupt on every fourth capture event
ICOV4Input Capture Overflow Status Flag bit (read-only)
  • 0 No input capture overflow has occurred
  • 1 Input capture overflow has occurred
ICBNE3Input Capture Buffer Not Empty Status bit (read-only)
  • 0 Input capture buffer is empty
  • 1 Input capture buffer is not empty; at least one more capture value can be read
ICM2:0Input Capture Mode Select bits
  • 0 Input Capture module is disabled
  • 1 Edge Detect mode every edge (rising and falling)
  • 2 Simple Capture Event mode every falling edge
  • 3 Simple Capture Event mode every rising edge
  • 4 Prescaled Capture Event mode every fourth rising edge
  • 5 Prescaled Capture Event mode every sixteenth rising edge
  • 6 Simple Capture Event mode every edge
  • 7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

IC2BUF

Address
0xBF802210
Reset
0x00000000
Access
read only
Size
32-bit

IC3 Input capture 3

IC3CONInput Capture 1 Control Register

Address
0xBF802400
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ON15Input Capture Module Enable bit
  • 0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
  • 1 Module is enabled
SIDL13Stop in Idle Control bit
  • 0 Continue to operate in Idle mode
  • 1 Halt in Idle mode
FEDGE9First Capture Edge Select bit
  • 0 Capture falling edge first
  • 1 Capture rising edge first
C32832-bit Capture Select bit
  • 0 16-bit timer resource capture
  • 1 32-bit timer resource capture
ICTMR7Timer Select bit
  • 0 Timer3 is the counter source for capture
  • 1 Timer2 is the counter source for capture
ICI6:5Interrupt Control bits
  • 0 Interrupt on every capture event
  • 1 Interrupt on every second capture event
  • 2 Interrupt on every third capture event
  • 3 Interrupt on every fourth capture event
ICOV4Input Capture Overflow Status Flag bit (read-only)
  • 0 No input capture overflow has occurred
  • 1 Input capture overflow has occurred
ICBNE3Input Capture Buffer Not Empty Status bit (read-only)
  • 0 Input capture buffer is empty
  • 1 Input capture buffer is not empty; at least one more capture value can be read
ICM2:0Input Capture Mode Select bits
  • 0 Input Capture module is disabled
  • 1 Edge Detect mode every edge (rising and falling)
  • 2 Simple Capture Event mode every falling edge
  • 3 Simple Capture Event mode every rising edge
  • 4 Prescaled Capture Event mode every fourth rising edge
  • 5 Prescaled Capture Event mode every sixteenth rising edge
  • 6 Simple Capture Event mode every edge
  • 7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

IC3BUF

Address
0xBF802410
Reset
0x00000000
Access
read only
Size
32-bit

IC4 Input capture 4

IC4CONInput Capture 1 Control Register

Address
0xBF802600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ON15Input Capture Module Enable bit
  • 0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
  • 1 Module is enabled
SIDL13Stop in Idle Control bit
  • 0 Continue to operate in Idle mode
  • 1 Halt in Idle mode
FEDGE9First Capture Edge Select bit
  • 0 Capture falling edge first
  • 1 Capture rising edge first
C32832-bit Capture Select bit
  • 0 16-bit timer resource capture
  • 1 32-bit timer resource capture
ICTMR7Timer Select bit
  • 0 Timer3 is the counter source for capture
  • 1 Timer2 is the counter source for capture
ICI6:5Interrupt Control bits
  • 0 Interrupt on every capture event
  • 1 Interrupt on every second capture event
  • 2 Interrupt on every third capture event
  • 3 Interrupt on every fourth capture event
ICOV4Input Capture Overflow Status Flag bit (read-only)
  • 0 No input capture overflow has occurred
  • 1 Input capture overflow has occurred
ICBNE3Input Capture Buffer Not Empty Status bit (read-only)
  • 0 Input capture buffer is empty
  • 1 Input capture buffer is not empty; at least one more capture value can be read
ICM2:0Input Capture Mode Select bits
  • 0 Input Capture module is disabled
  • 1 Edge Detect mode every edge (rising and falling)
  • 2 Simple Capture Event mode every falling edge
  • 3 Simple Capture Event mode every rising edge
  • 4 Prescaled Capture Event mode every fourth rising edge
  • 5 Prescaled Capture Event mode every sixteenth rising edge
  • 6 Simple Capture Event mode every edge
  • 7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

IC4BUF

Address
0xBF802610
Reset
0x00000000
Access
read only
Size
32-bit

IC5 Input capture 5

IC5CONInput Capture 1 Control Register

Address
0xBF802800
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
ON15Input Capture Module Enable bit
  • 0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
  • 1 Module is enabled
SIDL13Stop in Idle Control bit
  • 0 Continue to operate in Idle mode
  • 1 Halt in Idle mode
FEDGE9First Capture Edge Select bit
  • 0 Capture falling edge first
  • 1 Capture rising edge first
C32832-bit Capture Select bit
  • 0 16-bit timer resource capture
  • 1 32-bit timer resource capture
ICTMR7Timer Select bit
  • 0 Timer3 is the counter source for capture
  • 1 Timer2 is the counter source for capture
ICI6:5Interrupt Control bits
  • 0 Interrupt on every capture event
  • 1 Interrupt on every second capture event
  • 2 Interrupt on every third capture event
  • 3 Interrupt on every fourth capture event
ICOV4Input Capture Overflow Status Flag bit (read-only)
  • 0 No input capture overflow has occurred
  • 1 Input capture overflow has occurred
ICBNE3Input Capture Buffer Not Empty Status bit (read-only)
  • 0 Input capture buffer is empty
  • 1 Input capture buffer is not empty; at least one more capture value can be read
ICM2:0Input Capture Mode Select bits
  • 0 Input Capture module is disabled
  • 1 Edge Detect mode every edge (rising and falling)
  • 2 Simple Capture Event mode every falling edge
  • 3 Simple Capture Event mode every rising edge
  • 4 Prescaled Capture Event mode every fourth rising edge
  • 5 Prescaled Capture Event mode every sixteenth rising edge
  • 6 Simple Capture Event mode every edge
  • 7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

IC5BUF

Address
0xBF802810
Reset
0x00000000
Access
read only
Size
32-bit

OC1 Output compare 1

OC1CONOutput Compare 'x' Control Register

Address
0xBF803000
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC1R

Address
0xBF803010
Reset
0x00000000
Access
read/write
Size
32-bit

OC1RS

Address
0xBF803020
Reset
0x00000000
Access
read/write
Size
32-bit

OC2 Output compare 2

OC2CONOutput Compare 'x' Control Register

Address
0xBF803200
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC2R

Address
0xBF803210
Reset
0x00000000
Access
read/write
Size
32-bit

OC2RS

Address
0xBF803220
Reset
0x00000000
Access
read/write
Size
32-bit

OC3 Output compare 3

OC3CONOutput Compare 'x' Control Register

Address
0xBF803400
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC3R

Address
0xBF803410
Reset
0x00000000
Access
read/write
Size
32-bit

OC3RS

Address
0xBF803420
Reset
0x00000000
Access
read/write
Size
32-bit

OC4 Output compare 4

OC4CONOutput Compare 'x' Control Register

Address
0xBF803600
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC4R

Address
0xBF803610
Reset
0x00000000
Access
read/write
Size
32-bit

OC4RS

Address
0xBF803620
Reset
0x00000000
Access
read/write
Size
32-bit

OC5 Output compare 5

OC5CONOutput Compare 'x' Control Register

Address
0xBF803800
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC5R

Address
0xBF803810
Reset
0x00000000
Access
read/write
Size
32-bit

OC5RS

Address
0xBF803820
Reset
0x00000000
Access
read/write
Size
32-bit

I2C1 I²C 1

I2C1CONI2C Control Register

Address
0xBF805000
Reset
0x00001000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
ON15I2C Enable bit
  • 0 Disables the I2C module; all I2C pins are controlled by PORT functions
  • 1 Enables the I2C module and configures the SDA and SCL pins as serial port pins
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
SCLREL12SCLx Release Control bit (when operating as I2C slave)
  • 0 Hold SCLx clock low (clock stretch)
  • 1 Release SCLx clock
STRICT11Strict I 2 C Reserved Address Rule Enable bit
  • 0 Strict I2C Reserved Address Rule is not enabled
  • 1 Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space.
A10M1010-bit Slave Address bit
  • 0 I2CxADD is a 7-bit slave address
  • 1 I2CxADD is a 10-bit slave address
DISSLW9Disable Slew Rate Control bit
  • 0 Slew rate control is enabled
  • 1 Slew rate control is disabled
SMEN8SMBus Input Levels bit
  • 0 Disable SMBus input thresholds
  • 1 Enable I/O pin thresholds compliant with SMBus specification
GCEN7General Call Enable bit (when operating as I2C slave)
  • 0 General call address disabled
  • 1 Enable interrupt when a general call address is received in the I2CxRSR(module is enabled for reception)
STREN6SCLx Clock Stretch Enable bit (when operating as I2C slave)
  • 0 Disable software or receive clock stretching
  • 1 Enable software or receive clock stretching
ACKDT5Acknowledge Data bit (when operating as I2C master, applicable during master receive)
  • 0 Send ACK during Acknowledge
  • 1 Send NACK during Acknowledge
ACKEN4Acknowledge Sequence Enable bit
  • 0 Acknowledge sequence not in progress
  • 1 Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence.
RCEN3Receive Enable bit (when operating as I2C master)
  • 0 Receive sequence not in progress
  • 1 Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
PEN2Stop Condition Enable bit (when operating as I2C master)
  • 0 Stop condition not in progress
  • 1 Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
RSEN1Repeated Start Condition Enable bit (when operating as I2C master)
  • 0 Repeated Start condition not in progress
  • 1 Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence.
SEN0Start Condition Enable bit (when operating as I2C master)
  • 0 Start condition not in progress
  • 1 Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

I2C1STATI2C Status Register

Address
0xBF805010
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
ACKSTAT15Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
  • 0 Acknowledge was received from slave
  • 1 Acknowledge was not received from slave
TRSTAT14Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
  • 0 Master transmit is not in progress
  • 1 Master transmit is in progress (8 bits + ACK)
BCL10Master Bus Collision Detect bit
  • 0 No collision
  • 1 A bus collision has been detected during a master operation
GCSTAT9General Call Status bit
  • 0 General call address was not received
  • 1 General call address was received
ADD10810-bit Address Status bit
  • 0 10-bit address was not matched
  • 1 10-bit address was matched
IWCOL7Write Collision Detect bit
  • 0 No collision
  • 1 An attempt to write the I2CxTRN register failed because the I2C module is busy
I2COV6Receive Overflow Flag bit
  • 0 No overflow
  • 1 A byte was received while the I2CxRCV register is still holding the previous byte
DA5
P4Stop bit
  • 0 Stop bit was not detected last
  • 1 Indicates that a Stop bit has been detected last
S3Start bit
  • 0 Start bit was not detected last
  • 1 Indicates that a Start (or Repeated Start) bit has been detected last
RW2
RBF1Receive Buffer Full Status bit
  • 0 Receive not complete I2CxRCV is empty
  • 1 Receive complete I2CxRCV is full
TBF0Transmit Buffer Full Status bit
  • 0 Transmit complete I2CxTRN is empty
  • 1 Transmit in progress I2CxTRN is full

I2C1ADD

Address
0xBF805020
Reset
0x00000000
Access
read/write
Size
32-bit

I2C1MSK

Address
0xBF805030
Reset
0x00000000
Access
read/write
Size
32-bit

I2C1BRG

Address
0xBF805040
Reset
0x00000000
Access
read/write
Size
32-bit

I2C1TRN

Address
0xBF805050
Reset
0x00000000
Access
read/write
Size
32-bit

I2C1RCV

Address
0xBF805060
Reset
0x00000000
Access
read/write
Size
32-bit

I2C2 I²C 2

I2C2CONI2C Control Register

Address
0xBF805100
Reset
0x00001000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
ON15I2C Enable bit
  • 0 Disables the I2C module; all I2C pins are controlled by PORT functions
  • 1 Enables the I2C module and configures the SDA and SCL pins as serial port pins
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
SCLREL12SCLx Release Control bit (when operating as I2C slave)
  • 0 Hold SCLx clock low (clock stretch)
  • 1 Release SCLx clock
STRICT11Strict I 2 C Reserved Address Rule Enable bit
  • 0 Strict I2C Reserved Address Rule is not enabled
  • 1 Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space.
A10M1010-bit Slave Address bit
  • 0 I2CxADD is a 7-bit slave address
  • 1 I2CxADD is a 10-bit slave address
DISSLW9Disable Slew Rate Control bit
  • 0 Slew rate control is enabled
  • 1 Slew rate control is disabled
SMEN8SMBus Input Levels bit
  • 0 Disable SMBus input thresholds
  • 1 Enable I/O pin thresholds compliant with SMBus specification
GCEN7General Call Enable bit (when operating as I2C slave)
  • 0 General call address disabled
  • 1 Enable interrupt when a general call address is received in the I2CxRSR(module is enabled for reception)
STREN6SCLx Clock Stretch Enable bit (when operating as I2C slave)
  • 0 Disable software or receive clock stretching
  • 1 Enable software or receive clock stretching
ACKDT5Acknowledge Data bit (when operating as I2C master, applicable during master receive)
  • 0 Send ACK during Acknowledge
  • 1 Send NACK during Acknowledge
ACKEN4Acknowledge Sequence Enable bit
  • 0 Acknowledge sequence not in progress
  • 1 Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence.
RCEN3Receive Enable bit (when operating as I2C master)
  • 0 Receive sequence not in progress
  • 1 Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
PEN2Stop Condition Enable bit (when operating as I2C master)
  • 0 Stop condition not in progress
  • 1 Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
RSEN1Repeated Start Condition Enable bit (when operating as I2C master)
  • 0 Repeated Start condition not in progress
  • 1 Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence.
SEN0Start Condition Enable bit (when operating as I2C master)
  • 0 Start condition not in progress
  • 1 Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

I2C2STATI2C Status Register

Address
0xBF805110
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
ACKSTAT15Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
  • 0 Acknowledge was received from slave
  • 1 Acknowledge was not received from slave
TRSTAT14Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
  • 0 Master transmit is not in progress
  • 1 Master transmit is in progress (8 bits + ACK)
BCL10Master Bus Collision Detect bit
  • 0 No collision
  • 1 A bus collision has been detected during a master operation
GCSTAT9General Call Status bit
  • 0 General call address was not received
  • 1 General call address was received
ADD10810-bit Address Status bit
  • 0 10-bit address was not matched
  • 1 10-bit address was matched
IWCOL7Write Collision Detect bit
  • 0 No collision
  • 1 An attempt to write the I2CxTRN register failed because the I2C module is busy
I2COV6Receive Overflow Flag bit
  • 0 No overflow
  • 1 A byte was received while the I2CxRCV register is still holding the previous byte
DA5
P4Stop bit
  • 0 Stop bit was not detected last
  • 1 Indicates that a Stop bit has been detected last
S3Start bit
  • 0 Start bit was not detected last
  • 1 Indicates that a Start (or Repeated Start) bit has been detected last
RW2
RBF1Receive Buffer Full Status bit
  • 0 Receive not complete I2CxRCV is empty
  • 1 Receive complete I2CxRCV is full
TBF0Transmit Buffer Full Status bit
  • 0 Transmit complete I2CxTRN is empty
  • 1 Transmit in progress I2CxTRN is full

I2C2ADD

Address
0xBF805120
Reset
0x00000000
Access
read/write
Size
32-bit

I2C2MSK

Address
0xBF805130
Reset
0x00000000
Access
read/write
Size
32-bit

I2C2BRG

Address
0xBF805140
Reset
0x00000000
Access
read/write
Size
32-bit

I2C2TRN

Address
0xBF805150
Reset
0x00000000
Access
read/write
Size
32-bit

I2C2RCV

Address
0xBF805160
Reset
0x00000000
Access
read/write
Size
32-bit

SPI1 SPI 1

SPI1CONSPI Control Register

Address
0xBF805800
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
FRMSYNC30Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
  • 0 Frame sync pulse output (Master mode)
  • 1 Frame sync pulse input (Slave mode)
FRMPOL29Frame Sync Polarity bit (Framed SPI mode only)
  • 0 Frame pulse is active-low
  • 1 Frame pulse is active-high
MSSEN28Master Mode Slave Select Enable bit
  • 0 Slave select SPI support is disabled.
  • 1 Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
FRMSYPW27Frame Sync Pulse Width bit
  • 0 Frame sync pulse is one clock wide
  • 1 Frame sync pulse is one character wide
FRMCNT26:24Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode.
  • 0 Generate a frame sync pulse on every data character
  • 1 Generate a frame sync pulse on every 2 data characters
  • 2 Generate a frame sync pulse on every 4 data characters
  • 3 Generate a frame sync pulse on every 8 data characters
  • 4 Generate a frame sync pulse on every 16 data characters
  • 5 Generate a frame sync pulse on every 32 data characters
  • 6 Reserved
  • 7 Reserved
MCLKSEL23Master Clock Enable bit
  • 0 PBCLK is used by the Baud Rate Generator
  • 1 REFCLK is used by the Baud Rate Generator
SPIFE17Frame Sync Pulse Edge Select bit
  • 0 Frame synchronization pulse precedes the first bit clock
  • 1 Frame synchronization pulse coincides with the first bit clock
ENHBUF16Enhanced Buffer Enable bit
  • 0 Enhanced Buffer mode is disabled
  • 1 Enhanced Buffer mode is enabled
ON15SPI Peripheral On bit
  • 0 SPI Peripheral is disabled
  • 1 SPI Peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation when the device enters Idle mode
  • 1 Discontinue operation when CPU enters in Idle mode
DISSDO12Disable SDOx pin bit
  • 0 SDOx pin is controlled by the module
  • 1 SDOx pin is not used by the module. Pin is controlled by associated PORT register
MODE321132/16-Bit Communication Select bits
  • 0 (AUDEN=1) 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame/(AUDEN=0) 8-bit Data
  • 1 (AUDEN=1) 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 16-bit Data
  • 2 (AUDEN=1) 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 32-bit Data
  • 3 (AUDEN=1) 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 32-bit Data
MODE1610
SMP9SPI Data Input Sample Phase bit (master mode only)
  • 0 (Master mode) Input data sampled at middle of data output time / (Slave mode) value is ignored
  • 1 (Master mode) Input data sampled at end of data output time / (Slave mode) value is ignored
CKE8SPI Clock Edge Select bit
  • 0 Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
  • 1 Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
SSEN7Slave Select Enable bit
  • 0 SSx pin not used for Slave mode
  • 1 SSx pin used for Slave mode
CKP6Clock Polarity Select bit
  • 0 Idle state for clock is a low level; active state is a high level
  • 1 Idle state for clock is a high level; active state is a low level
MSTEN5Master Mode Enable bit
  • 0 Slave mode
  • 1 Master mode
DISSDI4Disable SDI bit
  • 0 SDI pin is controlled by the SPI module
  • 1 SDI pin is not used by the SPI module (pin is controlled by PORT function)
STXISEL3:2SPI Transmit Buffer Empty Interrupt Mode bits
  • 0 Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
  • 1 Interrupt is generated when the buffer is completely empty
  • 2 Interrupt is generated when the buffer is empty by one-half or more
  • 3 Interrupt is generated when the buffer is not full (has one or more empty elements)
SRXISEL1:0SPI Receive Buffer Full Interrupt Mode bits
  • 0 Interrupt is generated when the last word in the receive buffer is read (i.e. buffer is empty)
  • 1 Interrupt is generated when the buffer is not empty
  • 2 Interrupt is generated when the buffer is full by one-half or more
  • 3 Interrupt is generated when the buffer is full
FRMEN31Framed SPI Support bit
  • 0 Framed SPI support is disabled
  • 1 Framed SPI support is enabled (SSx pin used as FSYNC input/output)

SPI1STATSPI Status Register

Address
0xBF805810
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
RXBUFELM28:24
TXBUFELM20:16
FRMERR12SPI Frame Error status bit
  • 0 No Frame error detected
  • 1 Frame error detected
SPIBUSY11SPI Activity Status bit
  • 0 SPI peripheral is currently idle
  • 1 SPI peripheral is currently busy with some transactions
SPITUR8Transmit Under Run bit
  • 0 Transmit buffer has no underrun condition
  • 1 Transmit buffer has encountered an underrun condition
SRMT7Shift Register Empty bit (valid only when ENHBUF = 1)
  • 0 When SPI module shift register is not empty
  • 1 When SPI module shift register is empty
SPIROV6Receive Overflow Flag bit
  • 0 No overflow has occurred
  • 1 A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.
SPIRBE5RX FIFO Empty bit (valid only when ENHBUF = 1)
  • 0 RX FIFO is not empty (CRPTR != SWPTR)
  • 1 RX FIFO is empty (CRPTR = SWPTR)
SPITBE3SPI Transmit Buffer Empty Status bit
  • 0 Transmit buffer SPIxTXB is not empty
  • 1 Transmit buffer SPIxTXB is empty
SPITBF1SPI Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full
  • 1 Transmit not yet started SPITXB is full
SPIRBF0SPI Receive Buffer Full Status bit
  • 0 Receive buffer SPIxRXB is not full
  • 1 Receive buffer SPIxRXB is full

SPI1BUF

Address
0xBF805820
Reset
0x00000000
Access
read/write
Size
32-bit

SPI1BRG

Address
0xBF805830
Reset
0x00000000
Access
read/write
Size
32-bit

SPI1CON2SPI Control Register 2

Address
0xBF805840
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
SPISGNEXT15Sign Extend Read Data from the RX FIFO bit
  • 0 Data from RX FIFO is not sign extened
  • 1 Data from RX FIFO is sign extended
FRMERREN12Enable Interrupt Events via FRMERR bit
  • 0 Frame Error does not generate error events
  • 1 Frame Error overflow generates error events
SPIROVEN11Enable Interrupt Events via SPIROV bit
  • 0 Receive overflow does not generate error events
  • 1 Receive overflow generates error events
SPITUREN10Enable Interrupt Events via SPITUR bit
  • 0 Transmit Underrun Does Not Generate Error Events
  • 1 Transmit Underrun Generates Error Events
IGNROV9Ignore Receive Overflow bit
  • 0 A ROV is a critical error which stops SPI operation
  • 1 A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
IGNTUR8Ignore Transmit Underrun bit
  • 0 A TUR is a critical error which stop SPI operation
  • 1 A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
AUDEN7Enable Audio CODEC Support bit
  • 0 Audio protocol disabled
  • 1 Audio protocol enabled
AUDMONO3Transmit Audio Data Format bit
  • 0 Audio data is stereo
  • 1 Audio data is mono (Each data word is transmitted on both left and right channels)
AUDMOD1:0Audio Protocol Mode bit
  • 0 I2S mode
  • 1 Left Justified mode
  • 2 Right Justified mode
  • 3 PCM/DSP mode

SPI2 SPI 2

SPI2CONSPI Control Register

Address
0xBF805A00
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
FRMSYNC30Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
  • 0 Frame sync pulse output (Master mode)
  • 1 Frame sync pulse input (Slave mode)
FRMPOL29Frame Sync Polarity bit (Framed SPI mode only)
  • 0 Frame pulse is active-low
  • 1 Frame pulse is active-high
MSSEN28Master Mode Slave Select Enable bit
  • 0 Slave select SPI support is disabled.
  • 1 Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
FRMSYPW27Frame Sync Pulse Width bit
  • 0 Frame sync pulse is one clock wide
  • 1 Frame sync pulse is one character wide
FRMCNT26:24Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode.
  • 0 Generate a frame sync pulse on every data character
  • 1 Generate a frame sync pulse on every 2 data characters
  • 2 Generate a frame sync pulse on every 4 data characters
  • 3 Generate a frame sync pulse on every 8 data characters
  • 4 Generate a frame sync pulse on every 16 data characters
  • 5 Generate a frame sync pulse on every 32 data characters
  • 6 Reserved
  • 7 Reserved
MCLKSEL23Master Clock Enable bit
  • 0 PBCLK is used by the Baud Rate Generator
  • 1 REFCLK is used by the Baud Rate Generator
SPIFE17Frame Sync Pulse Edge Select bit
  • 0 Frame synchronization pulse precedes the first bit clock
  • 1 Frame synchronization pulse coincides with the first bit clock
ENHBUF16Enhanced Buffer Enable bit
  • 0 Enhanced Buffer mode is disabled
  • 1 Enhanced Buffer mode is enabled
ON15SPI Peripheral On bit
  • 0 SPI Peripheral is disabled
  • 1 SPI Peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation when the device enters Idle mode
  • 1 Discontinue operation when CPU enters in Idle mode
DISSDO12Disable SDOx pin bit
  • 0 SDOx pin is controlled by the module
  • 1 SDOx pin is not used by the module. Pin is controlled by associated PORT register
MODE321132/16-Bit Communication Select bits
  • 0 (AUDEN=1) 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame/(AUDEN=0) 8-bit Data
  • 1 (AUDEN=1) 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 16-bit Data
  • 2 (AUDEN=1) 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 32-bit Data
  • 3 (AUDEN=1) 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame/(AUDEN=0) 32-bit Data
MODE1610
SMP9SPI Data Input Sample Phase bit (master mode only)
  • 0 (Master mode) Input data sampled at middle of data output time / (Slave mode) value is ignored
  • 1 (Master mode) Input data sampled at end of data output time / (Slave mode) value is ignored
CKE8SPI Clock Edge Select bit
  • 0 Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
  • 1 Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
SSEN7Slave Select Enable bit
  • 0 SSx pin not used for Slave mode
  • 1 SSx pin used for Slave mode
CKP6Clock Polarity Select bit
  • 0 Idle state for clock is a low level; active state is a high level
  • 1 Idle state for clock is a high level; active state is a low level
MSTEN5Master Mode Enable bit
  • 0 Slave mode
  • 1 Master mode
DISSDI4Disable SDI bit
  • 0 SDI pin is controlled by the SPI module
  • 1 SDI pin is not used by the SPI module (pin is controlled by PORT function)
STXISEL3:2SPI Transmit Buffer Empty Interrupt Mode bits
  • 0 Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
  • 1 Interrupt is generated when the buffer is completely empty
  • 2 Interrupt is generated when the buffer is empty by one-half or more
  • 3 Interrupt is generated when the buffer is not full (has one or more empty elements)
SRXISEL1:0SPI Receive Buffer Full Interrupt Mode bits
  • 0 Interrupt is generated when the last word in the receive buffer is read (i.e. buffer is empty)
  • 1 Interrupt is generated when the buffer is not empty
  • 2 Interrupt is generated when the buffer is full by one-half or more
  • 3 Interrupt is generated when the buffer is full
FRMEN31Framed SPI Support bit
  • 0 Framed SPI support is disabled
  • 1 Framed SPI support is enabled (SSx pin used as FSYNC input/output)

SPI2STATSPI Status Register

Address
0xBF805A10
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
RXBUFELM28:24
TXBUFELM20:16
FRMERR12SPI Frame Error status bit
  • 0 No Frame error detected
  • 1 Frame error detected
SPIBUSY11SPI Activity Status bit
  • 0 SPI peripheral is currently idle
  • 1 SPI peripheral is currently busy with some transactions
SPITUR8Transmit Under Run bit
  • 0 Transmit buffer has no underrun condition
  • 1 Transmit buffer has encountered an underrun condition
SRMT7Shift Register Empty bit (valid only when ENHBUF = 1)
  • 0 When SPI module shift register is not empty
  • 1 When SPI module shift register is empty
SPIROV6Receive Overflow Flag bit
  • 0 No overflow has occurred
  • 1 A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.
SPIRBE5RX FIFO Empty bit (valid only when ENHBUF = 1)
  • 0 RX FIFO is not empty (CRPTR != SWPTR)
  • 1 RX FIFO is empty (CRPTR = SWPTR)
SPITBE3SPI Transmit Buffer Empty Status bit
  • 0 Transmit buffer SPIxTXB is not empty
  • 1 Transmit buffer SPIxTXB is empty
SPITBF1SPI Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full
  • 1 Transmit not yet started SPITXB is full
SPIRBF0SPI Receive Buffer Full Status bit
  • 0 Receive buffer SPIxRXB is not full
  • 1 Receive buffer SPIxRXB is full

SPI2BUF

Address
0xBF805A20
Reset
0x00000000
Access
read/write
Size
32-bit

SPI2BRG

Address
0xBF805A30
Reset
0x00000000
Access
read/write
Size
32-bit

SPI2CON2SPI Control Register 2

Address
0xBF805A40
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
SPISGNEXT15Sign Extend Read Data from the RX FIFO bit
  • 0 Data from RX FIFO is not sign extened
  • 1 Data from RX FIFO is sign extended
FRMERREN12Enable Interrupt Events via FRMERR bit
  • 0 Frame Error does not generate error events
  • 1 Frame Error overflow generates error events
SPIROVEN11Enable Interrupt Events via SPIROV bit
  • 0 Receive overflow does not generate error events
  • 1 Receive overflow generates error events
SPITUREN10Enable Interrupt Events via SPITUR bit
  • 0 Transmit Underrun Does Not Generate Error Events
  • 1 Transmit Underrun Generates Error Events
IGNROV9Ignore Receive Overflow bit
  • 0 A ROV is a critical error which stops SPI operation
  • 1 A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
IGNTUR8Ignore Transmit Underrun bit
  • 0 A TUR is a critical error which stop SPI operation
  • 1 A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
AUDEN7Enable Audio CODEC Support bit
  • 0 Audio protocol disabled
  • 1 Audio protocol enabled
AUDMONO3Transmit Audio Data Format bit
  • 0 Audio data is stereo
  • 1 Audio data is mono (Each data word is transmitted on both left and right channels)
AUDMOD1:0Audio Protocol Mode bit
  • 0 I2S mode
  • 1 Left Justified mode
  • 2 Right Justified mode
  • 3 PCM/DSP mode

UART1 UART 1

U1MODEUARTx Mode Register

Address
0xBF806000
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
ON15UARTx Enable bit
  • 0 UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal
  • 1 UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when device enters Idle mode
IREN12IrDA Encoder and Decoder Enable bit
  • 0 IrDA is disabled
  • 1 IrDA is enabled
RTSMD11Mode Selection for UxRTS Pin bit
  • 0 UxRTS pin is in Flow Control mode
  • 1 UxRTS pin is in Simplex mode
UEN9:8UARTx Enable bits
  • 0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
  • 1 UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
  • 2 UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
  • 3 UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
WAKE7Enable Wake-up on Start bit Detect During Sleep Mode bit
  • 0 Wake-up is disabled
  • 1 Wake-up is enabled
LPBACK6UARTx Loopback Mode Select bit
  • 0 Loopback mode is disabled
  • 1 Loopback mode is enabled
ABAUD5Auto-Baud Enable bit
  • 0 Baud rate measurement is disabled or completed
  • 1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV4Receive Polarity Inversion bit
  • 0 UxRX Idle state is 1
  • 1 UxRX Idle state is 0
BRGH3High Baud Rate Enable bit
  • 0 Standard Speed mode 16x baud clock enabled
  • 1 High-Speed mode 4x baud clock enabled
PDSEL2:1Parity and Data Selection bits
  • 0 8-bit data no parity
  • 1 8-bit data even parity
  • 2 8-bit data odd parity
  • 3 9-bit data no parity
STSEL0Stop Selection bit
  • 0 1 Stop bit
  • 1 2 Stop bits

U1STAUARTx Status and Control Register

Address
0xBF806010
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
ADM_EN24Automatic Address Detect Mode Enable bit
  • 0 Automatic Address Detect mode is disabled
  • 1 Automatic Address Detect mode is enabled
ADDR23:16
UTXISEL15:14TX Interrupt Mode Selection bits
  • 0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
  • 1 Interrupt is generated and asserted when all characters have been transmitted
  • 2 Interrupt is generated and asserted while the transmit buffer is empty
  • 3 Reserved
UTXINV13Transmit Polarity Inversion bit
  • 0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
  • 1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN12Receiver Enable bit
  • 0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the port.
  • 1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK11Transmit Break bit
  • 0 Break transmission is disabled or completed
  • 1 Send Break on next transmission. Start bit followed by twelve 0 bits, followed by Stop bit; cleared by hardware upon completion
UTXEN10Transmit Enable bit
  • 0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the port.
  • 1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF9Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full, at least one more character can be written
  • 1 Transmit buffer is full
TRMT8Transmit Shift Register is Empty bit (read-only)
  • 0 Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
  • 1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL7:6Receive Interrupt Mode Selection bit
  • 0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
  • 1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
  • 2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
  • 3 Reserved
ADDEN5Address Character Detect bit (bit 8 of received data = 1)
  • 0 Address Detect mode is disabled
  • 1 Address Detect mode is enabled. If 9-bit mode is not selected
RIDLE4Receiver Idle bit (read-only)
  • 0 Data is being received
  • 1 Receiver is Idle
PERR3Parity Error Status bit (read-only)
  • 0 Parity error has not been detected
  • 1 Parity error has been detected for the current character
FERR2Framing Error Status bit (read-only)
  • 0 Framing error has not been detected
  • 1 Framing error has been detected for the current character
OERR1Receive Buffer Overrun Error Status bit
  • 0 Receive buffer has not overflowed
  • 1 Receive buffer has overflowed
URXDA0Receive Buffer Data Available bit (read-only)
  • 0 Receive buffer is empty
  • 1 Receive buffer has data, at least one more character can be read

U1TXREG

Address
0xBF806020
Reset
0x00000000
Access
read/write
Size
32-bit

U1RXREG

Address
0xBF806030
Reset
0x00000000
Access
read only
Size
32-bit

U1BRG

Address
0xBF806040
Reset
0x00000000
Access
read/write
Size
32-bit

UART2 UART 2

U2MODEUARTx Mode Register

Address
0xBF806200
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
ON15UARTx Enable bit
  • 0 UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal
  • 1 UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when device enters Idle mode
IREN12IrDA Encoder and Decoder Enable bit
  • 0 IrDA is disabled
  • 1 IrDA is enabled
RTSMD11Mode Selection for UxRTS Pin bit
  • 0 UxRTS pin is in Flow Control mode
  • 1 UxRTS pin is in Simplex mode
UEN9:8UARTx Enable bits
  • 0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
  • 1 UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
  • 2 UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
  • 3 UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
WAKE7Enable Wake-up on Start bit Detect During Sleep Mode bit
  • 0 Wake-up is disabled
  • 1 Wake-up is enabled
LPBACK6UARTx Loopback Mode Select bit
  • 0 Loopback mode is disabled
  • 1 Loopback mode is enabled
ABAUD5Auto-Baud Enable bit
  • 0 Baud rate measurement is disabled or completed
  • 1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV4Receive Polarity Inversion bit
  • 0 UxRX Idle state is 1
  • 1 UxRX Idle state is 0
BRGH3High Baud Rate Enable bit
  • 0 Standard Speed mode 16x baud clock enabled
  • 1 High-Speed mode 4x baud clock enabled
PDSEL2:1Parity and Data Selection bits
  • 0 8-bit data no parity
  • 1 8-bit data even parity
  • 2 8-bit data odd parity
  • 3 9-bit data no parity
STSEL0Stop Selection bit
  • 0 1 Stop bit
  • 1 2 Stop bits

U2STAUARTx Status and Control Register

Address
0xBF806210
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
ADM_EN24Automatic Address Detect Mode Enable bit
  • 0 Automatic Address Detect mode is disabled
  • 1 Automatic Address Detect mode is enabled
ADDR23:16
UTXISEL15:14TX Interrupt Mode Selection bits
  • 0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
  • 1 Interrupt is generated and asserted when all characters have been transmitted
  • 2 Interrupt is generated and asserted while the transmit buffer is empty
  • 3 Reserved
UTXINV13Transmit Polarity Inversion bit
  • 0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
  • 1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN12Receiver Enable bit
  • 0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the port.
  • 1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK11Transmit Break bit
  • 0 Break transmission is disabled or completed
  • 1 Send Break on next transmission. Start bit followed by twelve 0 bits, followed by Stop bit; cleared by hardware upon completion
UTXEN10Transmit Enable bit
  • 0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the port.
  • 1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF9Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full, at least one more character can be written
  • 1 Transmit buffer is full
TRMT8Transmit Shift Register is Empty bit (read-only)
  • 0 Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
  • 1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL7:6Receive Interrupt Mode Selection bit
  • 0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
  • 1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
  • 2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
  • 3 Reserved
ADDEN5Address Character Detect bit (bit 8 of received data = 1)
  • 0 Address Detect mode is disabled
  • 1 Address Detect mode is enabled. If 9-bit mode is not selected
RIDLE4Receiver Idle bit (read-only)
  • 0 Data is being received
  • 1 Receiver is Idle
PERR3Parity Error Status bit (read-only)
  • 0 Parity error has not been detected
  • 1 Parity error has been detected for the current character
FERR2Framing Error Status bit (read-only)
  • 0 Framing error has not been detected
  • 1 Framing error has been detected for the current character
OERR1Receive Buffer Overrun Error Status bit
  • 0 Receive buffer has not overflowed
  • 1 Receive buffer has overflowed
URXDA0Receive Buffer Data Available bit (read-only)
  • 0 Receive buffer is empty
  • 1 Receive buffer has data, at least one more character can be read

U2TXREG

Address
0xBF806220
Reset
0x00000000
Access
read/write
Size
32-bit

U2RXREG

Address
0xBF806230
Reset
0x00000000
Access
read only
Size
32-bit

U2BRG

Address
0xBF806240
Reset
0x00000000
Access
read/write
Size
32-bit

PMP Parallel master port

PMCONParallel Port Control Register

Address
0xBF807000
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
ON15Parallel Master Port Enable bit
  • 0 PMP is disabled, no off-chip access performed
  • 1 PMP is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
ADRMUX12:11Address/Data Multiplexing Selection bits
  • 0 Address and data appear on separate pins
  • 1 Lower 8 bits of address are multiplexed on PMD(7:0) pins
  • 2 All 16 bits of address are multiplexed on PMD(7:0) pins
  • 3 Lower 8 bits of address are multiplexed on PMD(15:0) pins
PMPTTL10PMP Module TTL Input Buffer Select bit
  • 0 PMP module uses Schmitt Trigger input buffer
  • 1 PMP module uses TTL input buffers
PTWREN9Write Enable Strobe Port Enable bit
  • 0 PMWR/PMENB port is disabled
  • 1 PMWR/PMENB port is enabled
PTRDEN8Read/Write Strobe Port Enable bit
  • 0 PMRD/PMWR port is disabled
  • 1 PMRD/PMWR port is enabled
CSF7:6Chip Select Function bits
  • 0 PMCS1 functions as address bit 14
  • 1 PMCS1 functions as address bit 14
  • 2 PMCS1 functions as Chip Select
  • 3 Reserved
ALP5Address Latch Polarity bit
  • 0 Active-low (PMALL and PMALH)
  • 1 Active-high (PMALL and PMALH)
CS1P3Chip Select 0 Polarity bit
  • 0 Active-low (PMCS1)
  • 1 Active-high (PMCS1)
WRSP1Write Strobe Polarity bit
  • 0 (If MODE(1:0) = 00/01/10) Write strobe active-low / (If MODE(1:0) = 11) Enable strobe active-low
  • 1 (If MODE(1:0) = 00/01/10) Write strobe active-high / (If MODE(1:0) = 11) Enable strobe active-high
RDSP0Read Strobe Polarity bit
  • 0 (If MODE(1:0) = 00/01/10) Read Strobe active-low / (If MODE(1:0) = 11) Read/write strobe active-low
  • 1 (If MODE(1:0) = 00/01/10) Read Strobe active-high / (If MODE(1:0) = 11) Read/write strobe active-high

PMMODEParallel Port Mode Register

Address
0xBF807010
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
BUSY15Busy bit (Master mode only)
  • 0 Port is not busy
  • 1 Port is busy
IRQM14:13Interrupt Request Mode bits
  • 0 No Interrupt generated
  • 1 Interrupt generated at the end of the read/write cycle
  • 2 Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA(1:0) =11 (Addressable Slave mode only)
  • 3 Reserved
INCM12:11Increment Mode bits
  • 0 No increment or decrement of address
  • 1 Increment ADDR(15:0) by 1 every read/write cycle
  • 2 Decrement ADDR(15:0) by 1 every read/write cycle
  • 3 Slave mode read and write buffers auto-increment (MODE(1:0) = 00 only)
MODE9:8Parallel Port Mode Select bits
  • 0 Legacy Parallel Slave Port (PMRD, PMWR, PMCS1, and PMD)
  • 1 Enhanced Slave mode (PMRD, PMWR, PMCS1, PMD, and PMA)
  • 2 Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD)
  • 3 Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD)
WAITB7:6Data Setup to Read/Write Strobe Wait States bits
  • 0 Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
  • 1 Data wait of 2 TPB; multiplexed address phase of 2 TPB
  • 2 Data wait of 3 TPB; multiplexed address phase of 3 TPB
  • 3 Data wait of 4 TPB; multiplexed address phase of 4 TPB
WAITM5:2Data Read/Write Strobe Wait States bits
  • 0 Wait of 1TPB (default)
  • 1 Wait of 2TPB
  • 2 Wait of 3TPB
  • 3 Wait of 4TPB
  • 4 Wait of 5TPB
  • 5 Wait of 6TPB
  • 6 Wait of 7TPB
  • 7 Wait of 8TPB
  • 8 Wait of 9TPB
  • 9 Wait of 10TPB
  • 10 Wait of 11TPB
  • 11 Wait of 12TPB
  • 12 Wait of 13TPB
  • 13 Wait of 14TPB
  • 14 Wait of 15TPB
  • 15 Wait of 16TPB
WAITE1:0Data Hold After Read/Write Strobe Wait States bits
  • 0 (for write operations) Wait of 1 TPB (default) / (for read operations) Wait of 0 TPB (default)
  • 1 (for write operations) Wait of 2 TPB / (for read operations) Wait of 1 TPB
  • 2 (for write operations) Wait of 3 TPB / (for read operations) Wait of 2 TPB
  • 3 (for write operations) Wait of 4 TPB / (for read operations) Wait of 3 TPB

PMADDRParallel Port Address Register

Address
0xBF807020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
CS14
ADDR13:0Address bits
  • 0 address is 0

PMDOUT

Address
0xBF807030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATAOUT31:0

PMDIN

Address
0xBF807040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATAIN31:0

PMAENParallel Port Pin Enable Register

Address
0xBF807050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PTEN15:0PMP Address Port Enable bits
  • 0 PMA(10:2) function as port I/O
  • 512 PMA(9) functions as PMP address line, PMA(10) and PMA(8:2) function as port I/O
  • 1024 PMA(10) functions as PMP address line, PMA(9:2) function as port I/O
  • 2044 PMA(10:2) function as PMP address lines

PMSTATParallel Port Status Register (Slave modes only)

Address
0xBF807060
Reset
0x0000008F
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
IBF15Input Buffer Full Status bit
  • 0 Some or all of the writable input buffer registers are empty
  • 1 All writable input buffer registers are full
IBOV14Input Buffer Overflow Status bit
  • 0 No overflow occurred
  • 1 A write attempt to a full input byte buffer occurred (must be cleared in software)
IB3F11Input Buffer 3 status full bit
IB2F10Input Buffer 2 status full bit
IB1F9Input Buffer 1 status full bit
IB0F8Input Buffer 0 status full bit
OBE7Output Buffer Empty Status bit
  • 0 Some or all of the readable output buffer registers are full
  • 1 All readable output buffer registers are empty
OBUF6Output Buffer Underflow Status bit
  • 0 No underflow occurred
  • 1 A read occurred from an empty output byte buffer (must be cleared in software)
OB3E3Output buffer 3 status empty bit
OB2E2Output buffer 2 status empty bit
OB1E1Output buffer 1 status empty bit
OB0E0Output buffer 0 status empty bit

ADC Analog-to-digital converter

AD1CON1ADC Control Register 1

Address
0xBF809000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
ON15ADC Operating Mode bit
  • 0 ADC module is not operating
  • 1 ADC module is operating
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
FORM10:8Data Output Format bits
  • 0 Integer 16-bit
  • 1 Signed Integer 16-bit
  • 2 Fractional 16-bit
  • 3 Signed Fractional 16-bit
  • 4 Integer 32-bit
  • 5 Signed Integer 32-bit
  • 6 Fractional 32-bit
  • 7 Signed Fractional 32-bit
SSRC7:5Conversion Trigger Source Select bits
  • 0 Clearing SAMP bit ends sampling and starts conversion
  • 1 Active transition on INT0 pin ends sampling and starts conversion
  • 2 Timer 3 period match ends sampling and starts conversion
  • 3 CTMU ends sampling and starts conversion
  • 4 Reserved
  • 5 Reserved
  • 6 Reserved
  • 7 Internal counter ends sampling and starts conversion (auto convert)
CLRASAM4Stop Conversion Sequence bit (when the first ADC interrupt is generated)
  • 0 Normal operation, buffer contents will be overwritten by the next conversion sequence
  • 1 Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
ASAM2ADC Sample Auto-Start bit
  • 0 Sampling begins when SAMP bit is set
  • 1 Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
SAMP1ADC Sample Enable bit
  • 0 The ADC sample/hold amplifier is holding
  • 1 The ADC sample and hold amplifier is sampling
DONE0Analog-to-Digital Conversion Status bit
  • 0 Analog-to-digital conversion is not done or has not started
  • 1 Analog-to-digital conversion is done

AD1CON2ADC Control Register 2

Address
0xBF809010
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
VCFG15:13Voltage Reference Configuration bits
  • 0 VREFH is AVDD and VREFL is AVSS
  • 1 VREFH is Ext VREF + pin and VREFL is AVSS
  • 2 VREFH is AVDD and VREFL is External VREF- pin
  • 3 VREFH is External VREF+ pin and VREFL is External VREF- pin
  • 4 VREFH is AVDD and VREFL is AVSS
  • 5 VREFH is AVDD and VREFL is AVSS
  • 6 VREFH is AVDD and VREFL is AVSS
  • 7 VREFH is AVDD and VREFL is AVSS
OFFCAL12Input Offset Calibration Mode Select bit
  • 0 Disable Offset Calibration mode; The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL
  • 1 Enable Offset Calibration mode; Positive and negative inputs of the sample and hold amplifier are connected to VREFL
CSCNA10Input Scan Select bit
  • 0 Do not scan inputs
  • 1 Scan inputs
BUFS7Buffer Fill Status bit
  • 0 ADC is currently filling buffer 0x0-0x7; user should access data in 0x8-0xF
  • 1 ADC is currently filling buffer 0x8-0xF; user should access data in 0x0-0x7
SMPI5:2Sample/Convert Sequences Per Interrupt Selection bits
  • 0 Interrupts at the completion of conversion for each sample/convert sequence
  • 1 Interrupts at the completion of conversion for each 2nd sample/convert sequence
  • 2 Interrupts at the completion of conversion for each 3rd sample/convert sequence
  • 3 Interrupts at the completion of conversion for each 4th sample/convert sequence
  • 4 Interrupts at the completion of conversion for each 5th sample/convert sequence
  • 5 Interrupts at the completion of conversion for each 6th sample/convert sequence
  • 6 Interrupts at the completion of conversion for each 7th sample/convert sequence
  • 7 Interrupts at the completion of conversion for each 8th sample/convert sequence
  • 8 Interrupts at the completion of conversion for each 9th sample/convert sequence
  • 9 Interrupts at the completion of conversion for each 10th sample/convert sequence
  • 10 Interrupts at the completion of conversion for each 11th sample/convert sequence
  • 11 Interrupts at the completion of conversion for each 12th sample/convert sequence
  • 12 Interrupts at the completion of conversion for each 13th sample/convert sequence
  • 13 Interrupts at the completion of conversion for each 14th sample/convert sequence
  • 14 Interrupts at the completion of conversion for each 15th sample/convert sequence
  • 15 Interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM1ADC Result Buffer Mode Select bit
  • 0 Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
  • 1 Buffer configured as two 8-word buffers ADC1BUF7-ADC1BUF0 / ADC1BUFF-ADCBUF8
ALTS0Alternate Input Sample Mode Select bit
  • 0 Always use Sample A input multiplexer settings
  • 1 Uses Sample A input multiplexer settings for first sample then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples

AD1CON3ADC Control Register 3

Address
0xBF809020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ADRC15ADC Conversion Clock Source bit
  • 0 Clock derived from Peripheral Bus Clock (PBCLK)
  • 1 Clock derived from FRC
SAMC12:8Auto-Sample Time bits
  • 1 1 TAD
  • 2 2 TAD
  • 3 3 TAD
  • 4 4 TAD
  • 5 5 TAD
  • 6 6 TAD
  • 7 7 TAD
  • 8 8 TAD
  • 9 9 TAD
  • 10 10 TAD
  • 11 11 TAD
  • 12 12 TAD
  • 13 13 TAD
  • 14 14 TAD
  • 15 15 TAD
  • 16 16 TAD
  • 17 17 TAD
  • 18 18 TAD
  • 19 19 TAD
  • 20 20 TAD
  • 21 21 TAD
  • 22 22 TAD
  • 23 23 TAD
  • 24 24 TAD
  • 25 25 TAD
  • 26 26 TAD
  • 27 27 TAD
  • 28 28 TAD
  • 29 29 TAD
  • 30 30 TAD
  • 31 31 TAD
ADCS7:0ADC Conversion Clock Select bits
  • 0 2*TPB
  • 1 4*TPB
  • 2 6*TPB
  • 3 8*TPB
  • 4 10*TPB
  • 5 12*TPB
  • 6 14*TPB
  • 7 16*TPB
  • 8 18*TPB
  • 9 20*TPB
  • 10 22*TPB
  • 11 24*TPB
  • 12 26*TPB
  • 13 28*TPB
  • 14 30*TPB
  • 15 32*TPB
  • 16 34*TPB
  • 17 36*TPB
  • 18 38*TPB
  • 19 40*TPB
  • 20 42*TPB
  • 21 44*TPB
  • 22 46*TPB
  • 23 48*TPB
  • 24 50*TPB
  • 25 52*TPB
  • 26 54*TPB
  • 27 56*TPB
  • 28 58*TPB
  • 29 60*TPB
  • 30 62*TPB
  • 31 64*TPB
  • 32 66*TPB
  • 33 68*TPB
  • 34 70*TPB
  • 35 72*TPB
  • 36 74*TPB
  • 37 76*TPB
  • 38 78*TPB
  • 39 80*TPB
  • 40 82*TPB
  • 41 84*TPB
  • 42 86*TPB
  • 43 88*TPB
  • 44 90*TPB
  • 45 92*TPB
  • 46 94*TPB
  • 47 96*TPB
  • 48 98*TPB
  • 49 100*TPB
  • 50 102*TPB
  • 51 104*TPB
  • 52 106*TPB
  • 53 108*TPB
  • 54 110*TPB
  • 55 112*TPB
  • 56 114*TPB
  • 57 116*TPB
  • 58 118*TPB
  • 59 120*TPB
  • 60 122*TPB
  • 61 124*TPB
  • 62 126*TPB
  • 63 128*TPB
  • 64 130*TPB
  • 65 132*TPB
  • 66 134*TPB
  • 67 136*TPB
  • 68 138*TPB
  • 69 140*TPB
  • 70 142*TPB
  • 71 144*TPB
  • 72 146*TPB
  • 73 148*TPB
  • 74 150*TPB
  • 75 152*TPB
  • 76 154*TPB
  • 77 156*TPB
  • 78 158*TPB
  • 79 160*TPB
  • 80 162*TPB
  • 81 164*TPB
  • 82 166*TPB
  • 83 168*TPB
  • 84 170*TPB
  • 85 172*TPB
  • 86 174*TPB
  • 87 176*TPB
  • 88 178*TPB
  • 89 180*TPB
  • 90 182*TPB
  • 91 184*TPB
  • 92 186*TPB
  • 93 188*TPB
  • 94 190*TPB
  • 95 192*TPB
  • 96 194*TPB
  • 97 196*TPB
  • 98 198*TPB
  • 99 200*TPB
  • 100 202*TPB
  • 101 204*TPB
  • 102 206*TPB
  • 103 208*TPB
  • 104 210*TPB
  • 105 212*TPB
  • 106 214*TPB
  • 107 216*TPB
  • 108 218*TPB
  • 109 220*TPB
  • 110 222*TPB
  • 111 224*TPB
  • 112 226*TPB
  • 113 228*TPB
  • 114 230*TPB
  • 115 232*TPB
  • 116 234*TPB
  • 117 236*TPB
  • 118 238*TPB
  • 119 240*TPB
  • 120 242*TPB
  • 121 244*TPB
  • 122 246*TPB
  • 123 248*TPB
  • 124 250*TPB
  • 125 252*TPB
  • 126 254*TPB
  • 127 256*TPB
  • 128 258*TPB
  • 129 260*TPB
  • 130 262*TPB
  • 131 264*TPB
  • 132 266*TPB
  • 133 268*TPB
  • 134 270*TPB
  • 135 272*TPB
  • 136 274*TPB
  • 137 276*TPB
  • 138 278*TPB
  • 139 280*TPB
  • 140 282*TPB
  • 141 284*TPB
  • 142 286*TPB
  • 143 288*TPB
  • 144 290*TPB
  • 145 292*TPB
  • 146 294*TPB
  • 147 296*TPB
  • 148 298*TPB
  • 149 300*TPB
  • 150 302*TPB
  • 151 304*TPB
  • 152 306*TPB
  • 153 308*TPB
  • 154 310*TPB
  • 155 312*TPB
  • 156 314*TPB
  • 157 316*TPB
  • 158 318*TPB
  • 159 320*TPB
  • 160 322*TPB
  • 161 324*TPB
  • 162 326*TPB
  • 163 328*TPB
  • 164 330*TPB
  • 165 332*TPB
  • 166 334*TPB
  • 167 336*TPB
  • 168 338*TPB
  • 169 340*TPB
  • 170 342*TPB
  • 171 344*TPB
  • 172 346*TPB
  • 173 348*TPB
  • 174 350*TPB
  • 175 352*TPB
  • 176 354*TPB
  • 177 356*TPB
  • 178 358*TPB
  • 179 360*TPB
  • 180 362*TPB
  • 181 364*TPB
  • 182 366*TPB
  • 183 368*TPB
  • 184 370*TPB
  • 185 372*TPB
  • 186 374*TPB
  • 187 376*TPB
  • 188 378*TPB
  • 189 380*TPB
  • 190 382*TPB
  • 191 384*TPB
  • 192 386*TPB
  • 193 388*TPB
  • 194 390*TPB
  • 195 392*TPB
  • 196 394*TPB
  • 197 396*TPB
  • 198 398*TPB
  • 199 400*TPB
  • 200 402*TPB
  • 201 404*TPB
  • 202 406*TPB
  • 203 408*TPB
  • 204 410*TPB
  • 205 412*TPB
  • 206 414*TPB
  • 207 416*TPB
  • 208 418*TPB
  • 209 420*TPB
  • 210 422*TPB
  • 211 424*TPB
  • 212 426*TPB
  • 213 428*TPB
  • 214 430*TPB
  • 215 432*TPB
  • 216 434*TPB
  • 217 436*TPB
  • 218 438*TPB
  • 219 440*TPB
  • 220 442*TPB
  • 221 444*TPB
  • 222 446*TPB
  • 223 448*TPB
  • 224 450*TPB
  • 225 452*TPB
  • 226 454*TPB
  • 227 456*TPB
  • 228 458*TPB
  • 229 460*TPB
  • 230 462*TPB
  • 231 464*TPB
  • 232 466*TPB
  • 233 468*TPB
  • 234 470*TPB
  • 235 472*TPB
  • 236 474*TPB
  • 237 476*TPB
  • 238 478*TPB
  • 239 480*TPB
  • 240 482*TPB
  • 241 484*TPB
  • 242 486*TPB
  • 243 488*TPB
  • 244 490*TPB
  • 245 492*TPB
  • 246 494*TPB
  • 247 496*TPB
  • 248 498*TPB
  • 249 500*TPB
  • 250 502*TPB
  • 251 504*TPB
  • 252 506*TPB
  • 253 508*TPB
  • 254 510*TPB
  • 255 512*TPB

AD1CHSADC Input Select Register

Address
0xBF809040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
CH0SB27:24Positive Input Select bits for Sample B
  • 0 Channel 0 positive input is AN0
  • 1 Channel 0 positive input is AN1
  • 2 Channel 0 positive input is AN2
  • 3 Channel 0 positive input is AN3
  • 4 Channel 0 positive input is AN4
  • 5 Channel 0 positive input is AN5
  • 6 Reserved
  • 7 Reserved
  • 8 Reserved
  • 9 Channel 0 positive input is AN9
  • 10 Channel 0 positive input is AN10
  • 11 Channel 0 positive input is AN11
  • 12 Reserved
  • 13 Channel 0 positive input is CTMU temperature sensor (CTMUT)
  • 14 Channel 0 positive input is IVREF
  • 15 Channel 0 positive input is Open
CH0NA23Negative Input Select bit for Sample A Multiplexer Setting
  • 0 Channel 0 negative input is VREFL
  • 1 Channel 0 negative input is AN1
CH0SA19:16Positive Input Select bits for Sample A Multiplexer Setting
  • 0 Channel 0 positive input is AN0
  • 1 Channel 0 positive input is AN1
  • 2 Channel 0 positive input is AN2
  • 3 Channel 0 positive input is AN3
  • 4 Channel 0 positive input is AN4
  • 5 Channel 0 positive input is AN5
  • 6 Reserved
  • 7 Reserved
  • 8 Reserved
  • 9 Channel 0 positive input is AN9
  • 10 Channel 0 positive input is AN10
  • 11 Channel 0 positive input is AN11
  • 12 Reserved
  • 13 Channel 0 positive input is CTMU temperature sensor (CTMUT)
  • 14 Channel 0 positive input is IVREF
  • 15 Channel 0 positive input is Open
CH0NB31Negative Input Select bit for Sample B
  • 0 Channel 0 negative input is VREFL
  • 1 Channel 0 negative input is AN1

AD1CSSLADC Input Scan Select Register

Address
0xBF809050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CSSL15:0

ADC1BUF0

Address
0xBF809070
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF1

Address
0xBF809080
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF2

Address
0xBF809090
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF3

Address
0xBF8090A0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF4

Address
0xBF8090B0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF5

Address
0xBF8090C0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF6

Address
0xBF8090D0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF7

Address
0xBF8090E0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF8

Address
0xBF8090F0
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUF9

Address
0xBF809100
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFA

Address
0xBF809110
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFB

Address
0xBF809120
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFC

Address
0xBF809130
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFD

Address
0xBF809140
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFE

Address
0xBF809150
Reset
0x00000000
Access
read only
Size
32-bit

ADC1BUFF

Address
0xBF809160
Reset
0x00000000
Access
read only
Size
32-bit

CVR Comparator voltage reference

CVRCONComparator Voltage Reference Control Register

Address
0xBF809800
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ON15Comparator Voltage Reference On bit
  • 0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in the register.
  • 1 Module is enabled. Setting this bit does not affect other bits in the register.
CVROE6CVrefout Enable bit
  • 0 Voltage level is disconnected from CVrefout pin
  • 1 Voltage level is output on CVrefout pin
CVRR5CVref Range Selection bit
  • 0 0.25 CVrsrc to 0.75 CVrsrc with CVrsrc/32 step size
  • 1 0 to 0.67 CVrsrc with CVrsrc/24 step size
CVRSS4CVref Source Selection bit
  • 0 Comparator voltage reference source CVrsrc = AVdd - AVss
  • 1 Comparator voltage reference source CVrsrc = (Vref+) - (Vref-)
CVR3:0CVref Value Selection
  • 0 (When CVRR is 1) CVREF is (0/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (0/32)*CVRSRC
  • 1 (When CVRR is 1) CVREF is (1/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (1/32)*CVRSRC
  • 2 (When CVRR is 1) CVREF is (2/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (2/32)*CVRSRC
  • 3 (When CVRR is 1) CVREF is (3/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (3/32)*CVRSRC
  • 4 (When CVRR is 1) CVREF is (4/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (4/32)*CVRSRC
  • 5 (When CVRR is 1) CVREF is (5/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (5/32)*CVRSRC
  • 6 (When CVRR is 1) CVREF is (6/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (6/32)*CVRSRC
  • 7 (When CVRR is 1) CVREF is (7/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (7/32)*CVRSRC
  • 8 (When CVRR is 1) CVREF is (8/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (8/32)*CVRSRC
  • 9 (When CVRR is 1) CVREF is (9/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (9/32)*CVRSRC
  • 10 (When CVRR is 1) CVREF is (10/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (10/32)*CVRSRC
  • 11 (When CVRR is 1) CVREF is (11/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (11/32)*CVRSRC
  • 12 (When CVRR is 1) CVREF is (12/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (12/32)*CVRSRC
  • 13 (When CVRR is 1) CVREF is (13/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (13/32)*CVRSRC
  • 14 (When CVRR is 1) CVREF is (14/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (14/32)*CVRSRC
  • 15 (When CVRR is 1) CVREF is (15/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (15/32)*CVRSRC

CMP1 Comparator 1

CM1CONComparator Control Register

Address
0xBF80A000
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ON15Comparator ON bit
  • 0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
  • 1 Module is enabled. Setting this bit does not affect the other bits in this register
COE14Comparator Output Enable bit
  • 0 Comparator output is not driven on the output CxOUT pin
  • 1 Comparator output is driven on the output CxOUT pin
CPOL13Comparator Output Inversion bit
  • 0 Output is not inverted
  • 1 Output is inverted
COUT8Comparator Output bit
  • 0 Output of the Comparator is a 0
  • 1 Output of the Comparator is a 1
EVPOL7:6Interrupt Event Polarity Select bits
  • 0 Comparator interrupt generation is disabled
  • 1 Comparator interrupt is generated on a low-to-high transition of the comparator output
  • 2 Comparator interrupt is generated on a high-to-low transition of the comparator output
  • 3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF4Comparator Positive Input Configure bit
  • 0 Comparator non-inverting input is connected to the CxINA pin
  • 1 Comparator non-inverting input is connected to the internal CVref
CCH1:0Comparator Negative Input Select bits for Comparator
  • 0 Comparator inverting input is connected to the CxINB pin
  • 1 Comparator inverting input is connected to the CxINC pin
  • 2 Comparator inverting input is connected to the CxIND pin
  • 3 Comparator inverting input is connected to the IVREF

CMP2 Comparator 2

CM2CONComparator Control Register

Address
0xBF80A010
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ON15Comparator ON bit
  • 0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
  • 1 Module is enabled. Setting this bit does not affect the other bits in this register
COE14Comparator Output Enable bit
  • 0 Comparator output is not driven on the output CxOUT pin
  • 1 Comparator output is driven on the output CxOUT pin
CPOL13Comparator Output Inversion bit
  • 0 Output is not inverted
  • 1 Output is inverted
COUT8Comparator Output bit
  • 0 Output of the Comparator is a 0
  • 1 Output of the Comparator is a 1
EVPOL7:6Interrupt Event Polarity Select bits
  • 0 Comparator interrupt generation is disabled
  • 1 Comparator interrupt is generated on a low-to-high transition of the comparator output
  • 2 Comparator interrupt is generated on a high-to-low transition of the comparator output
  • 3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF4Comparator Positive Input Configure bit
  • 0 Comparator non-inverting input is connected to the CxINA pin
  • 1 Comparator non-inverting input is connected to the internal CVref
CCH1:0Comparator Negative Input Select bits for Comparator
  • 0 Comparator inverting input is connected to the CxINB pin
  • 1 Comparator inverting input is connected to the CxINC pin
  • 2 Comparator inverting input is connected to the CxIND pin
  • 3 Comparator inverting input is connected to the IVREF

CMP3 Comparator 3

CM3CONComparator Control Register

Address
0xBF80A020
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ON15Comparator ON bit
  • 0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
  • 1 Module is enabled. Setting this bit does not affect the other bits in this register
COE14Comparator Output Enable bit
  • 0 Comparator output is not driven on the output CxOUT pin
  • 1 Comparator output is driven on the output CxOUT pin
CPOL13Comparator Output Inversion bit
  • 0 Output is not inverted
  • 1 Output is inverted
COUT8Comparator Output bit
  • 0 Output of the Comparator is a 0
  • 1 Output of the Comparator is a 1
EVPOL7:6Interrupt Event Polarity Select bits
  • 0 Comparator interrupt generation is disabled
  • 1 Comparator interrupt is generated on a low-to-high transition of the comparator output
  • 2 Comparator interrupt is generated on a high-to-low transition of the comparator output
  • 3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF4Comparator Positive Input Configure bit
  • 0 Comparator non-inverting input is connected to the CxINA pin
  • 1 Comparator non-inverting input is connected to the internal CVref
CCH1:0Comparator Negative Input Select bits for Comparator
  • 0 Comparator inverting input is connected to the CxINB pin
  • 1 Comparator inverting input is connected to the CxINC pin
  • 2 Comparator inverting input is connected to the CxIND pin
  • 3 Comparator inverting input is connected to the IVREF

CMP Comparator

CMSTATComparator Status Register

Address
0xBF80A060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SIDL13Stop in Idle Control bit
  • 0 All Comparator modules continue to operate when the device enters Idle mode
  • 1 All Comparator modules are disabled when the device enters Idle mode
C3OUT2Comparator Output bit
  • 0 Output of Comparator 3 is a 0
  • 1 Output of Comparator 3 is a 1
C2OUT1Comparator Output bit
  • 0 Output of Comparator 2 is a 0
  • 1 Output of Comparator 2 is a 1
C1OUT0Comparator Output bit
  • 0 Output of Comparator 1 is a 0
  • 1 Output of Comparator 1 is a 1

CTMU Charge time measurement unit

CTMUCONCTMU Control Register

Address
0xBF80A200
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
EDG1POL30Edge 1 Polarity Select bit
  • 0 Edge1 programmed for a negative edge response
  • 1 Edge1 programmed for a positive edge response
EDG1SEL29:26Edge 1 Source Select bits
  • 0 Timer1 Event is selected
  • 1 OC1 Compare Event is selected
  • 2 CTED2 pin is selected
  • 3 CTED1 pin is selected
  • 4 CTED3 pin is selected
  • 5 CTED4 pin is selected
  • 6 CTED5 pin is selected
  • 7 CTED6 pin is selected
  • 8 CTED7 pin is selected
  • 9 CTED8 pin is selected
  • 10 IC1 Capture Event is selected
  • 11 IC2 Capture Event is selected
  • 12 IC3 Capture Event is selected
  • 13 C1OUT pin is selected
  • 14 C2OUT pin is selected
  • 15 C3OUT pin is selected
EDG2STAT25Edge2 Status bit
  • 0 Edge2 has not occurred
  • 1 Edge2 has occurred
EDG1STAT24Edge1 Status bit
  • 0 Edge1 has not occurred
  • 1 Edge1 has occurred
EDG2MOD23Edge2 Edge Sampling Select bit
  • 0 Input is level-sensitive
  • 1 Input is edge-sensitive
EDG2POL22Edge 2 Polarity Select bit
  • 0 Edge2 programmed for a negative edge response
  • 1 Edge2 programmed for a positive edge response
EDG2SEL21:18Edge 2 Source Select bits
  • 0 Timer1 Event is selected
  • 1 OC1 Compare Event is selected
  • 2 CTED2 pin is selected
  • 3 CTED1 pin is selected
  • 4 CTED9 pin is selected
  • 5 CTED10 pin is selected
  • 6 CTED11 pin is selected
  • 7 CTED12 pin is selected
  • 8 CTED13 pin is selected
  • 9 IC1 Capture Event is selected
  • 10 IC2 Capture Event is selected
  • 11 IC3 Capture Event is selected
  • 12 PBCLK clock is selected
  • 13 C1OUT pin is selected
  • 14 C2OUT pin is selected
  • 15 C3OUT pin is selected
ON15ON Enable bit
  • 0 Module is disabled
  • 1 Module is enabled
CTMUSIDL13Stop-in-Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
TGEN12Time Generation Enable bit
  • 0 Disables edge delay generation
  • 1 Enables edge delay generation
EDGEN11Edge Enable bit
  • 0 Edges are blocked
  • 1 Edges are not blocked
EDGSEQEN10Edge Sequence Enable bit
  • 0 No edge sequence is needed
  • 1 Edge1 must occur before Edge2 can occur
IDISSEN9Analog Current Source Control bit
  • 0 Analog current source output is not grounded
  • 1 Analog current source output is grounded
CTTRIG8Trigger Control bit
  • 0 Trigger output is disabled
  • 1 Trigger output is enabled
ITRIM7:2Current Source Trim bits
  • 0 Nominal current output specified by IRNG(1:0)
  • 1 Minimum positive change from nominal current
  • 31 Maximum positive change from nominal current
  • 33 Maximum negative change from nominal current
  • 63 Minimum negative change from nominal current
IRNG1:0Current Range Select bits
  • 0 1000 times base current
  • 1 Base current level
  • 2 10 times base current
  • 3 100 times base current
EDG1MOD31Edge1 Edge Sampling Select bit
  • 0 Input is level-sensitive
  • 1 Input is edge-sensitive

OSC Oscillator and clocks

OSCCONOscillator Control Register

Address
0xBF80F000
Reset
0x00200007
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
PLLODIV29:27Output Divider for PLL
  • 0 PLL output divided by 1
  • 1 PLL output divided by 2
  • 2 PLL output divided by 4
  • 3 PLL output divided by 8
  • 4 PLL output divided by 16
  • 5 PLL output divided by 32
  • 6 PLL output divided by 64
  • 7 PLL output divided by 256
FRCDIV26:24Internal Fast RC Oscillator Clock Divider bits
  • 0 FRC divided by 1
  • 1 FRC divided by 2 (default setting)
  • 2 FRC divided by 4
  • 3 FRC divided by 8
  • 4 FRC divided by 16
  • 5 FRC divided by 32
  • 6 FRC divided by 64
  • 7 FRC divided by 256
SOSCRDY22Secondary Oscillator (SOSC) Ready Indicator bit
  • 0 Secondary Oscillator is still warming up or is turned off
  • 1 Indicates that the Secondary Oscillator is running and is stable
PBDIVRDY21Peripheral Bus Clock Divisor Ready bit
  • 0 PBDIV(1:0) bits cannot be written
  • 1 PBDIV(1:0) bits can be written
PBDIV20:19Peripheral Bus Clock (PBCLK) Divisor bits
  • 0 PBCLK is SYSCLK divided by 1
  • 1 PBCLK is SYSCLK divided by 2
  • 2 PBCLK is SYSCLK divided by 4
  • 3 PBCLK is SYSCLK divided by 8 (default)
PLLMULT18:16Phase-Locked Loop (PLL) Multiplier bits
  • 0 Clock is multiplied by 15
  • 1 Clock is multiplied by 16
  • 2 Clock is multiplied by 17
  • 3 Clock is multiplied by 18
  • 4 Clock is multiplied by 19
  • 5 Clock is multiplied by 20
  • 6 Clock is multiplied by 21
  • 7 Clock is multiplied by 24
COSC14:12Current Oscillator Selection bits
  • 0 Internal Fast RC (FRC) Oscillator
  • 1 Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
  • 2 Primary Oscillator (POSC) (XT/HS/EC)
  • 3 Primary Oscillator (POSC) with PLL module (XTPLL/HSPLL/ECPLL)
  • 4 Secondary Oscillator (SOSC)
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Internal Fast RC (FRC) Oscillator divided by 16
  • 7 Internal Fast RC (FRC) Oscillator divided by OSCCON(FRCDIV) bits
NOSC10:8New Oscillator Selection bits
  • 0 Internal Fast Internal RC Oscillator (FRC)
  • 1 Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
  • 2 Primary Oscillator (XT/HS/EC)
  • 3 Primary Oscillator with PLL module (XTPLL/HSPLL/ECPLL)
  • 4 Secondary Oscillator (SOSC)
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Internal Fast RC Oscillator (FRC) divided by 16
  • 7 Internal Fast RC Oscillator (FRC) divided by OSCCON(FRCDIV) bits
CLKLOCK7Clock Selection Lock Enable bit
  • 0 (If FCKSM(1:0) is 1x) Clock and PLL selections are not locked and may be modified / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
  • 1 (If FCKSM(1:0) is 1x) Clock and PLL selections are locked / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
ULOCK6USB PLL Lock Status bit
  • 0 Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled
  • 1 Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
SLOCK5PLL Lock Status bit
  • 0 PLL module is out of lock
  • 1 PLL module is in lock or PLL module start-up timer is satisfied
SLPEN4Sleep Mode Enable bit
  • 0 Device will enter Idle mode when a WAIT instruction is executed
  • 1 Device will enter Sleep mode when a WAIT instruction is executed
CF3Clock Fail Detect bit
  • 0 No clock failure has been detected
  • 1 FSCM has detected a clock failure
UFRCEN2USB FRC Clock Enable bit
  • 0 Use the Primary Oscillator or USB PLL as the USB clock source
  • 1 Enable FRC as the clock source for the USB clock source
SOSCEN1Secondary Oscillator Enable bit
  • 0 Disable Secondary Oscillator
  • 1 Enable Secondary Oscillator
OSWEN0Oscillator Switch Enable bit
  • 0 Oscillator switch is complete
  • 1 Initiate an oscillator switch to selection specified by NOSC(2:0) bits

OSCTUNFRC Tuning Register

Address
0xBF80F010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TUN5:0FRC Oscillator Tuning bits
  • 0 Center frequency. Oscillator runs at minimal frequency (8 MHz)
  • 31 Center frequency + 12.5%
  • 32 Center frequency - 12.5%

REFOCONReference Oscillator Control Register

Address
0xBF80F020
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
RODIV30:16Reference Clock Divider bits
  • 0 Reference Clock output is same as source clock
  • 1 Reference Clock output is source clock divided by 2
  • 2 Reference Clock output is source clock divided by 4
  • 32767 Reference Clock output is source clock divided by 65534
ON15Output Enable bit
  • 0 Reference Oscillator Module is disabled
  • 1 Reference Oscillator Module is enabled
SIDL13Peripheral Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
OE12Reference Clock Output Enable bit
  • 0 Reference clock is not driven out on REFCLKO pin
  • 1 Reference clock is driven out on REFCLKO pin
RSLP11Reference Oscillator Module Run in Sleep bit
  • 0 Reference Oscillator Module output is disabled in Sleep
  • 1 Reference Oscillator Module output continues to run in Sleep
DIVSWEN9Divider Switch Enable bit
  • 0 Divider switch is complete
  • 1 Divider switch is in progress
ACTIVE8Reference Clock Request Status bit
  • 0 Reference clock request is not active
  • 1 Reference clock request is active
ROSEL3:0Reference Clock Source Select bits
  • 0 SYSCLK
  • 1 PBCLK
  • 2 POSC
  • 3 FRC
  • 4 LPRC
  • 5 SOSC
  • 6 USB PLL output
  • 7 Fvco Output
  • 8 REFCLKI
  • 9 Reserved; do not use
  • 10 Reserved; do not use
  • 11 Reserved; do not use
  • 12 Reserved; do not use
  • 13 Reserved; do not use
  • 14 Reserved; do not use
  • 15 Reserved; do not use

REFOTRIMReference Oscillator Trim Register

Address
0xBF80F030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ROTRIM31:23Reference Oscillator Trim bits
  • 0 0/512 divisor added to RODIV value
  • 1 1/512 divisor added to RODIV value
  • 2 2/512 divisor added to RODIV value
  • 256 256/512 divisor added to RODIV value
  • 510 510/512 divisor added to RODIV value
  • 511 511/512 divisor added to RODIV value

CFG Configuration and pin control

CFGCON

Address
0xBF80F200
Reset
0x00000008
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
IOLOCK13Peripheral Pin Select Lock bit
  • 0 Peripheral Pin Select is not locked. Writes to PPS registers is allowed
  • 1 Peripheral Pin Select is locked. Writes to PPS registers is not allowed
PMDLOCK12Peripheral Module Disable bit
  • 0 Peripheral module is not locked. Writes to PMD registers is allowed
  • 1 Peripheral module is locked. Writes to PMD registers is not allowed
JTAGEN3JTAG Port Enable bit
  • 0 Disable the JTAG port
  • 1 Enable the JTAG port
TDOEN0TDO Enable for 2-Wire JTAG bit
  • 0 2-wire JTAG protocol does not use TDO
  • 1 2-wire JTAG protocol uses TDO

DEVID

Address
0xBF80F220
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
VER28
DEVID27:0

SYSKEY

Address
0xBF80F230
Reset
0x00000000
Access
read only
Size
32-bit

PMD Peripheral module disable

PMD1

Address
0xBF80F240
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CVRMD12
CTMUMD8
AD1MD0

PMD2

Address
0xBF80F250
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CMP3MD2
CMP2MD1
CMP1MD0

PMD3

Address
0xBF80F260
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
OC5MD20
OC4MD19
OC3MD18
OC2MD17
OC1MD16
IC5MD4
IC4MD3
IC3MD2
IC2MD1
IC1MD0

PMD4

Address
0xBF80F270
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
T5MD4
T4MD3
T3MD2
T2MD1
T1MD0

PMD5

Address
0xBF80F280
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
USB1MD24
I2C2MD17
I2C1MD16
SPI2MD9
SPI1MD8
U2MD1
U1MD0

PMD6

Address
0xBF80F290
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PMPMD16
REFOMD1
RTCCMD0

NVM Flash controller (NVM)

NVMCONProgramming Control Register

Address
0xBF80F400
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
WR15Write Control bit
  • 0 Flash operation complete or inactive
  • 1 Initiate a Flash operation. Hardware clears this bit when the operation completes
WREN14Write Enable bit
  • 0 Disable writes to WR bit and disables LVD circuit
  • 1 Enable writes to WR bit and enables LVD circuit
WRERR13Write Error bit
  • 0 Program or erase sequence completed normally
  • 1 Program or erase sequence did not complete successfully
LVDERR12Low-Voltage Detect Error bit (LVD circuit must be enabled)
  • 0 Voltage level is acceptable for programming
  • 1 Low-voltage detected (possible data corruption if WRERR is set)
LVDSTAT11Low-Voltage Detect Status bit (LVD circuit must be enabled)
  • 0 Low-voltage event NOT active
  • 1 Low-voltage event active
NVMOP3:0NVM Operation bits
  • 0 No operation
  • 1 Word program operation: programs word selected by NVMADDR if it is not write-protected
  • 2 No operation
  • 3 Row program operation: programs row selected by NVMADDR if it is not write-protected
  • 4 Page erase operation: erases page selected by NVMADDR if it is not write-protected
  • 5 Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
  • 6 No operation
  • 7 Reserved
  • 8 Reserved
  • 9 Reserved
  • 10 Reserved
  • 11 Reserved
  • 12 Reserved
  • 13 Reserved
  • 14 Reserved
  • 15 Reserved

NVMKEYProgramming Unlock Register

Address
0xBF80F410
Reset
0x00000000
Access
write only
Size
32-bit

NVMADDRFlash Address Register

Address
0xBF80F420
Reset
0x00000000
Access
read/write
Size
32-bit

NVMDATA

Address
0xBF80F430
Reset
0x00000000
Access
read/write
Size
32-bit

NVMSRCADDRSource Data Address Register

Address
0xBF80F440
Reset
0x00000000
Access
read/write
Size
32-bit

RCON Reset control

RCONReset Control Register

Address
0xBF80F600
Reset
0x00000003
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
CMR9Configuration Mismatch Reset Flag bit
  • 0 Configuration mismatch Reset has not occurred
  • 1 Configuration mismatch Reset has occurred
VREGS8Voltage Regulator Standby Enable bit
  • 0 Regulator is set to standby tracking mode
  • 1 Regulator is enabled and is on during Sleep mode
EXTR7External Reset (MCLR) Pin Flag bit
  • 0 Master Clear (pin) Reset has not occurred
  • 1 Master Clear (pin) Reset has occurred
SWR6Software Reset Flag bit
  • 0 Software Reset as not executed
  • 1 Software Reset was executed
WDTO4Watchdog Timer Time-out Flag bit
  • 0 WDT Time-out has not occurred
  • 1 WDT Time-out has occurred
SLEEP3Wake From Sleep Flag bit
  • 0 Device was not in Sleep mode
  • 1 Device was in Sleep mode
IDLE2Wake From Idle Flag bit
  • 0 Device was not in Idle mode
  • 1 Device was in Idle mode
BOR1Brown-out Reset Flag bit
  • 0 Brown-out Reset has not occurred
  • 1 Brown-out Reset has occurred
POR0Power-on Reset Flag bit
  • 0 Power-on Reset has not occurred
  • 1 Power-on Reset has occurred

RSWRSTSoftware Reset Register

Address
0xBF80F610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SWRST0Software Reset Trigger bit
  • 0 No effect
  • 1 Enable Software Reset event

PPS Peripheral pin select

INT1R

Address
0xBF80FA04
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
INT1R3:0

INT2R

Address
0xBF80FA08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
INT2R3:0

INT3R

Address
0xBF80FA0C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
INT3R3:0

INT4R

Address
0xBF80FA10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
INT4R3:0

T2CKR

Address
0xBF80FA18
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
T2CKR3:0

T3CKR

Address
0xBF80FA1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
T3CKR3:0

T4CKR

Address
0xBF80FA20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
T4CKR3:0

T5CKR

Address
0xBF80FA24
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
T5CKR3:0

IC1R

Address
0xBF80FA28
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IC1R3:0

IC2R

Address
0xBF80FA2C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IC2R3:0

IC3R

Address
0xBF80FA30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IC3R3:0

IC4R

Address
0xBF80FA34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IC4R3:0

IC5R

Address
0xBF80FA38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
IC5R3:0

OCFAR

Address
0xBF80FA48
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
OCFAR3:0

OCFBR

Address
0xBF80FA4C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
OCFBR3:0

U1RXR

Address
0xBF80FA50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
U1RXR3:0

U1CTSR

Address
0xBF80FA54
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
U1CTSR3:0

U2RXR

Address
0xBF80FA58
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
U2RXR3:0

U2CTSR

Address
0xBF80FA5C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
U2CTSR3:0

SDI1R

Address
0xBF80FA84
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDI1R3:0

SS1R

Address
0xBF80FA88
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SS1R3:0

SDI2R

Address
0xBF80FA90
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDI2R3:0

SS2R

Address
0xBF80FA94
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SS2R3:0

REFCLKIR

Address
0xBF80FAB8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
REFCLKIR3:0

RPA0R

Address
0xBF80FB00
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA0R3:0

RPA1R

Address
0xBF80FB04
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA1R3:0

RPA2R

Address
0xBF80FB08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA2R3:0

RPA3R

Address
0xBF80FB0C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA3R3:0

RPA4R

Address
0xBF80FB10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA4R3:0

RPA8R

Address
0xBF80FB20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA8R3:0

RPA9R

Address
0xBF80FB24
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPA9R3:0

RPB0R

Address
0xBF80FB2C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB0R3:0

RPB1R

Address
0xBF80FB30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB1R3:0

RPB2R

Address
0xBF80FB34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB2R3:0

RPB3R

Address
0xBF80FB38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB3R3:0

RPB4R

Address
0xBF80FB3C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB4R3:0

RPB5R

Address
0xBF80FB40
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB5R3:0

RPB7R

Address
0xBF80FB48
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB7R3:0

RPB8R

Address
0xBF80FB4C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB8R3:0

RPB9R

Address
0xBF80FB50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB9R3:0

RPB10R

Address
0xBF80FB54
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB10R3:0

RPB11R

Address
0xBF80FB58
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB11R3:0

RPB13R

Address
0xBF80FB60
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB13R3:0

RPB14R

Address
0xBF80FB64
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB14R3:0

RPB15R

Address
0xBF80FB68
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPB15R3:0

RPC0R

Address
0xBF80FB6C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC0R3:0

RPC1R

Address
0xBF80FB70
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC1R3:0

RPC2R

Address
0xBF80FB74
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC2R3:0

RPC3R

Address
0xBF80FB78
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC3R3:0

RPC4R

Address
0xBF80FB7C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC4R3:0

RPC5R

Address
0xBF80FB80
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC5R3:0

RPC6R

Address
0xBF80FB84
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC6R3:0

RPC7R

Address
0xBF80FB88
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC7R3:0

RPC8R

Address
0xBF80FB8C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC8R3:0

RPC9R

Address
0xBF80FB90
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RPC9R3:0

INT Interrupt controller

INTCONInterrupt Control Register

Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
SS016
MVEC12Multi Vector Configuration bit
  • 0 Interrupt controller configured for Single-vectored mode
  • 1 Interrupt controller configured for Multi-vectored mode
TPC10:8Interrupt Proximity Timer Control bits
  • 0 Disables Interrupt Proximity timer
  • 1 Interrupts of group priority 1 start the Interrupt Proximity timer
  • 2 Interrupts of group priority 2 or lower start the Interrupt Proximity timer
  • 3 Interrupts of group priority 3 or lower start the Interrupt Proximity timer
  • 4 Interrupts of group priority 4 or lower start the Interrupt Proximity timer
  • 5 Interrupts of group priority 5 or lower start the Interrupt Proximity timer
  • 6 Interrupts of group priority 6 or lower start the Interrupt Proximity timer
  • 7 Interrupts of group priority 7 or lower start the Interrupt Proximity timer
INT4EP4External Interrupt 4 Edge
  • 0 Falling edge
  • 1 Rising edge
INT3EP3External Interrupt 3 Edge
  • 0 Falling edge
  • 1 Rising edge
INT2EP2External Interrupt 2 Edge
  • 0 Falling edge
  • 1 Rising edge
INT1EP1External Interrupt 1 Edge
  • 0 Falling edge
  • 1 Rising edge
INT0EP0External Interrupt 0 Edge
  • 0 Falling edge
  • 1 Rising edge

INTSTATInterrupt Status Register

Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
SRIPL10:8Requested Priority Level bits
  • 0 Priority level 0 of the latest interrupt presented to the CPU
  • 1 Priority level 1 of the latest interrupt presented to the CPU
  • 2 Priority level 2 of the latest interrupt presented to the CPU
  • 3 Priority level 3 of the latest interrupt presented to the CPU
  • 4 Priority level 4 of the latest interrupt presented to the CPU
  • 5 Priority level 5 of the latest interrupt presented to the CPU
  • 6 Priority level 6 of the latest interrupt presented to the CPU
  • 7 Priority level 7 of the latest interrupt presented to the CPU
VEC5:0Interrupt Vector bits
  • 0 The interrupt vector 0 is presented to the CPU
  • 1 The interrupt vector 1 is presented to the CPU
  • 2 The interrupt vector 2 is presented to the CPU
  • 3 The interrupt vector 3 is presented to the CPU
  • 4 The interrupt vector 4 is presented to the CPU
  • 5 The interrupt vector 5 is presented to the CPU
  • 6 The interrupt vector 6 is presented to the CPU
  • 7 The interrupt vector 7 is presented to the CPU
  • 8 The interrupt vector 8 is presented to the CPU
  • 9 The interrupt vector 9 is presented to the CPU
  • 10 The interrupt vector 10 is presented to the CPU
  • 11 The interrupt vector 11 is presented to the CPU
  • 12 The interrupt vector 12 is presented to the CPU
  • 13 The interrupt vector 13 is presented to the CPU
  • 14 The interrupt vector 14 is presented to the CPU
  • 15 The interrupt vector 15 is presented to the CPU
  • 16 The interrupt vector 16 is presented to the CPU
  • 17 The interrupt vector 17 is presented to the CPU
  • 18 The interrupt vector 18 is presented to the CPU
  • 19 The interrupt vector 19 is presented to the CPU
  • 20 The interrupt vector 20 is presented to the CPU
  • 21 The interrupt vector 21 is presented to the CPU
  • 22 The interrupt vector 22 is presented to the CPU
  • 23 The interrupt vector 23 is presented to the CPU
  • 24 The interrupt vector 24 is presented to the CPU
  • 25 The interrupt vector 25 is presented to the CPU
  • 26 The interrupt vector 26 is presented to the CPU
  • 27 The interrupt vector 27 is presented to the CPU
  • 28 The interrupt vector 28 is presented to the CPU
  • 29 The interrupt vector 29 is presented to the CPU
  • 30 The interrupt vector 30 is presented to the CPU
  • 31 The interrupt vector 31 is presented to the CPU
  • 32 The interrupt vector 32 is presented to the CPU
  • 33 The interrupt vector 33 is presented to the CPU
  • 34 The interrupt vector 34 is presented to the CPU
  • 35 The interrupt vector 35 is presented to the CPU
  • 36 The interrupt vector 36 is presented to the CPU
  • 37 The interrupt vector 37 is presented to the CPU
  • 38 The interrupt vector 38 is presented to the CPU
  • 39 The interrupt vector 39 is presented to the CPU
  • 40 The interrupt vector 40 is presented to the CPU
  • 41 The interrupt vector 41 is presented to the CPU
  • 42 The interrupt vector 42 is presented to the CPU
  • 43 The interrupt vector 43 is presented to the CPU
  • 44 The interrupt vector 44 is presented to the CPU
  • 45 The interrupt vector 45 is presented to the CPU
  • 46 The interrupt vector 46 is presented to the CPU
  • 47 The interrupt vector 47 is presented to the CPU
  • 48 The interrupt vector 48 is presented to the CPU
  • 49 The interrupt vector 49 is presented to the CPU
  • 50 The interrupt vector 50 is presented to the CPU
  • 51 The interrupt vector 51 is presented to the CPU
  • 52 The interrupt vector 52 is presented to the CPU
  • 53 The interrupt vector 53 is presented to the CPU
  • 54 The interrupt vector 54 is presented to the CPU
  • 55 The interrupt vector 55 is presented to the CPU
  • 56 The interrupt vector 56 is presented to the CPU
  • 57 The interrupt vector 57 is presented to the CPU
  • 58 The interrupt vector 58 is presented to the CPU
  • 59 The interrupt vector 59 is presented to the CPU
  • 60 The interrupt vector 60 is presented to the CPU
  • 61 The interrupt vector 61 is presented to the CPU
  • 62 The interrupt vector 62 is presented to the CPU
  • 63 The interrupt vector 63 is presented to the CPU

IPTMR

Address
0xBF881020
Reset
0x00000000
Access
read/write
Size
32-bit

IFS0Interrupt Flag Status Register

Address
0xBF881030
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
RTCCIF30
FSCMIF29
AD1IF28
OC5IF27
IC5IF26
IC5EIF25
T5IF24
INT4IF23
OC4IF22
IC4IF21
IC4EIF20
T4IF19
INT3IF18
OC3IF17
IC3IF16
IC3EIF15
T3IF14
INT2IF13
OC2IF12
IC2IF11
IC2EIF10
T2IF9
INT1IF8
OC1IF7
IC1IF6
IC1EIF5
T1IF4
INT0IF3
CS1IF2
CS0IF1
CTIF0
FCEIF31

IFS1Interrupt Flag Status Register

Address
0xBF881040
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
DMA2IF30
DMA1IF29
DMA0IF28
CTMUIF27
I2C2MIF26
I2C2SIF25
I2C2BIF24
U2TXIF23
U2RXIF22
U2EIF21
SPI2TXIF20
SPI2RXIF19
SPI2EIF18
PMPEIF17
PMPIF16
CNCIF15
CNBIF14
CNAIF13
I2C1MIF12
I2C1SIF11
I2C1BIF10
U1TXIF9
U1RXIF8
U1EIF7
SPI1TXIF6
SPI1RXIF5
SPI1EIF4
USBIF3
CMP3IF2
CMP2IF1
CMP1IF0
DMA3IF31

IEC0Interrupt Enable Control Register

Address
0xBF881060
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
RTCCIE30
FSCMIE29
AD1IE28
OC5IE27
IC5IE26
IC5EIE25
T5IE24
INT4IE23
OC4IE22
IC4IE21
IC4EIE20
T4IE19
INT3IE18
OC3IE17
IC3IE16
IC3EIE15
T3IE14
INT2IE13
OC2IE12
IC2IE11
IC2EIE10
T2IE9
INT1IE8
OC1IE7
IC1IE6
IC1EIE5
T1IE4
INT0IE3
CS1IE2
CS0IE1
CTIE0
FCEIE31

IEC1Interrupt Enable Control Register

Address
0xBF881070
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
DMA2IE30
DMA1IE29
DMA0IE28
CTMUIE27
I2C2MIE26
I2C2SIE25
I2C2BIE24
U2TXIE23
U2RXIE22
U2EIE21
SPI2TXIE20
SPI2RXIE19
SPI2EIE18
PMPEIE17
PMPIE16
CNCIE15
CNBIE14
CNAIE13
I2C1MIE12
I2C1SIE11
I2C1BIE10
U1TXIE9
U1RXIE8
U1EIE7
SPI1TXIE6
SPI1RXIE5
SPI1EIE4
USBIE3
CMP3IE2
CMP2IE1
CMP1IE0
DMA3IE31

IPC0Interrupt Priority Control Register

Address
0xBF881090
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
INT0IP28:26
INT0IS25:24
CS1IP20:18
CS1IS17:16
CS0IP12:10
CS0IS9:8
CTIP4:2
CTIS1:0

IPC1Interrupt Priority Control Register

Address
0xBF8810A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
INT1IP28:26
INT1IS25:24
OC1IP20:18
OC1IS17:16
IC1IP12:10
IC1IS9:8
T1IP4:2
T1IS1:0

IPC2Interrupt Priority Control Register

Address
0xBF8810B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
INT2IP28:26
INT2IS25:24
OC2IP20:18
OC2IS17:16
IC2IP12:10
IC2IS9:8
T2IP4:2
T2IS1:0

IPC3Interrupt Priority Control Register

Address
0xBF8810C0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
INT3IP28:26
INT3IS25:24
OC3IP20:18
OC3IS17:16
IC3IP12:10
IC3IS9:8
T3IP4:2
T3IS1:0

IPC4Interrupt Priority Control Register

Address
0xBF8810D0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
INT4IP28:26
INT4IS25:24
OC4IP20:18
OC4IS17:16
IC4IP12:10
IC4IS9:8
T4IP4:2
T4IS1:0

IPC5Interrupt Priority Control Register

Address
0xBF8810E0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
AD1IP28:26
AD1IS25:24
OC5IP20:18
OC5IS17:16
IC5IP12:10
IC5IS9:8
T5IP4:2
T5IS1:0

IPC6Interrupt Priority Control Register

Address
0xBF8810F0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CMP1IP28:26
CMP1IS25:24
FCEIP20:18
FCEIS17:16
RTCCIP12:10
RTCCIS9:8
FSCMIP4:2
FSCMIS1:0

IPC7Interrupt Priority Control Register

Address
0xBF881100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
SPI1IP28:26
SPI1IS25:24
USBIP20:18
USBIS17:16
CMP3IP12:10
CMP3IS9:8
CMP2IP4:2
CMP2IS1:0

IPC8Interrupt Priority Control Register

Address
0xBF881110
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
PMPIP28:26
PMPIS25:24
CNIP20:18
CNIS17:16
I2C1IP12:10
I2C1IS9:8
U1IP4:2
U1IS1:0

IPC9Interrupt Priority Control Register

Address
0xBF881120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CTMUIP28:26
CTMUIS25:24
I2C2IP20:18
I2C2IS17:16
U2IP12:10
U2IS9:8
SPI2IP4:2
SPI2IS1:0

IPC10Interrupt Priority Control Register

Address
0xBF881130
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DMA3IP28:26
DMA3IS25:24
DMA2IP20:18
DMA2IS17:16
DMA1IP12:10
DMA1IS9:8
DMA0IP4:2
DMA0IS1:0

BMX Bus matrix

BMXCONBus Matrix Configuration Register

Address
0xBF882000
Reset
0x001F0041
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BMXCHEDMA26
BMXERRIXI20Enable Bus Error from IXI bit
  • 0 Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
  • 1 Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD19Enable Bus Error from ICD Debug Unit bit
  • 0 Disable bus error exceptions for unmapped address accesses initiated from ICD
  • 1 Enable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA18Bus Error from DMA bit
  • 0 Disable bus error exceptions for unmapped address accesses initiated from DMA
  • 1 Enable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS17Bus Error from CPU Data Access bit
  • 0 Disable bus error exceptions for unmapped address accesses initiated from CPU data access
  • 1 Enable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS16Bus Error from CPU Instruction Access bit
  • 0 Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
  • 1 Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
BMXWSDRM6CPU Instruction or Data Access from Data RAM Wait State bit
  • 0 Data RAM accesses from CPU have zero wait states for address setup
  • 1 Data RAM accesses from CPU have one wait state for address setup
BMXARB2:0Bus Matrix Arbitration Mode bits
  • 0 Arbitration Mode 0
  • 1 Arbitration Mode 1 (default)
  • 2 Arbitration Mode 2
  • 3 Reserved (using these configuration modes will produce undefined behavior)
  • 4 Reserved (using these configuration modes will produce undefined behavior)
  • 5 Reserved (using these configuration modes will produce undefined behavior)
  • 6 Reserved (using these configuration modes will produce undefined behavior)
  • 7 Reserved (using these configuration modes will produce undefined behavior)

BMXDKPBAData RAM Kernel Program Base Address Register

Address
0xBF882010
Reset
0x00000000
Access
read/write
Size
32-bit

BMXDUDBAData RAM User Data Base Address Register

Address
0xBF882020
Reset
0x00000000
Access
read/write
Size
32-bit

BMXDUPBAData RAM User Program Base Address Register

Address
0xBF882030
Reset
0x00000000
Access
read/write
Size
32-bit

BMXDRMSZData RAM Size Register

Address
0xBF882040
Reset
0x00020000
Access
read only
Size
32-bit

BMXPUPBAProgram Flash (PFM) User Program Base Address Register

Address
0xBF882050
Reset
0x00000000
Access
read/write
Size
32-bit

BMXPFMSZProgram Flash (PFM) Size Register

Address
0xBF882060
Reset
0x00080000
Access
read only
Size
32-bit

BMXBOOTSZBoot Flash (IFM) Size Register

Address
0xBF882070
Reset
0x00003000
Access
read only
Size
32-bit

DMAC DMA controller

DMACONDMA Controller Control Register

Address
0xBF883000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15DMA On bit
  • 0 DMA module is disabled
  • 1 DMA module is enabled
SUSPEND12DMA Suspend bit
  • 0 DMA operates normally
  • 1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY11DMA Module Busy bit
  • 0 DMA module is disabled and not actively transferring data
  • 1 DMA module is active

DMASTATDMA Status Register

Address
0xBF883010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RDWR3Read/Write Status bit
  • 0 Last DMA bus access was a write
  • 1 Last DMA bus access was a read
DMACH1:0

DMAADDRDMA Address Register

Address
0xBF883020
Reset
0x00000000
Access
read only
Size
32-bit

DCRCCONDMA CRC Control Register

Address
0xBF883030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BYTO29:28CRC Byte Order Selection bits
  • 0 No swapping (i.e. source byte order)
  • 1 Endian byte swap on word boundaries (i.e. reverse source byte order)
  • 2 Swap half-words on word boundaries (i.e. reverse source half-word order with source byte order per half-word)
  • 3 Endian byte swap on half-word boundaries (i.e. source half-word order with reverse source byte order per half-word)
WBO27CRC Write Byte Order Selection bit
  • 0 Source data is written to the destination unaltered
  • 1 Source data is written to the destination re-ordered as defined by BYTO
BITO24CRC Bit Order Selection bit
  • 0 (When CRCTYP is 1) The IP header checksum is calculated Most Significant bit (MSb) first (i.e. not reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Most Significant bit first (i.e. not reflected)
  • 1 (When CRCTYP is 1) The IP header checksum is calculated Least Significant bit (LSb) first (i.e. reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Least Significant bit first (i.e. reflected)
PLEN12:8Polynomial Length bits
  • 1 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 0
  • 2 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 1
  • 3 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 2
  • 4 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 3
  • 5 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 4
  • 6 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 5
  • 7 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 6
  • 8 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 7
  • 9 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 8
  • 10 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 9
  • 11 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 10
  • 12 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 11
  • 13 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 12
  • 14 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 13
  • 15 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 14
  • 16 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 15
  • 17 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 16
  • 18 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 17
  • 19 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 18
  • 20 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 19
  • 21 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 20
  • 22 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 21
  • 23 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 22
  • 24 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 23
  • 25 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 24
  • 26 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 25
  • 27 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 26
  • 28 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 27
  • 29 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 28
  • 30 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 29
  • 31 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 30
CRCEN7CRC Enable bit
  • 0 CRC module is disabled and channel transfers proceed normally
  • 1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP6CRC Append Mode bit
  • 0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
  • 1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP5CRC Type Selection bit
  • 0 The CRC module will calculate a LFSR CRC
  • 1 The CRC module will calculate an IP header checksum
CRCCH2:0CRC Channel Select bits
  • 0 CRC is assigned to Channel 0
  • 1 CRC is assigned to Channel 1
  • 2 CRC is assigned to Channel 2
  • 3 CRC is assigned to Channel 3
  • 4 CRC is assigned to Channel 4
  • 5 CRC is assigned to Channel 5
  • 6 CRC is assigned to Channel 6
  • 7 CRC is assigned to Channel 7

DCRCDATADMA CRC Data Register

Address
0xBF883040
Reset
0x00000000
Access
read/write
Size
32-bit

DCRCXORDMA CRCXOR Enable Register

Address
0xBF883050
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0 DMA channel 0

DCH0CONDMA Channel x Control Register

Address
0xBF883060
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CHBUSY15Channel Busy bit
  • 0 Channel is inactive or has been disabled
  • 1 Channel is active or has been enabled
CHCHNS8Chain Channel Selection bit
  • 0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
  • 1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN7Channel Enable bit
  • 0 Channel is disabled
  • 1 Channel is enabled
CHAED6Channel Allow Events If Disabled bit
  • 0 Channel start/abort events will be ignored if the channel is disabled
  • 1 Channel start/abort events will be registered even if the channel is disabled
CHCHN5Channel Chain Enable bit
  • 0 Do not allow channel to be chained
  • 1 Allow channel to be chained
CHAEN4Channel Automatic Enable bit
  • 0 Channel is disabled on block transfer complete
  • 1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET2Channel Event Detected bit
  • 0 No events have been detected
  • 1 An event has been detected
CHPRI1:0Channel Priority bits
  • 0 Channel has priority 0
  • 1 Channel has priority 1
  • 2 Channel has priority 2
  • 3 Channel has priority 3 (highest)

DCH0ECONDMA Channel x Event Control Register

Address
0xBF883070
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
CHAIRQ23:16Channel Transfer Abort IRQ bits
  • 0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
  • 1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
  • 2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
  • 3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
  • 4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
  • 5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
  • 6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
  • 7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
  • 8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
  • 9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
  • 10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
  • 11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
  • 12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
  • 13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
  • 14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
  • 15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
  • 16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
  • 17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
  • 18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
  • 19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
  • 20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
  • 21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
  • 22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
  • 23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
  • 24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
  • 25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
  • 26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
  • 27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
  • 28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
  • 29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
  • 30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
  • 31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
  • 32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
  • 33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
  • 34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
  • 35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
  • 36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
  • 37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
  • 38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
  • 39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
  • 40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
  • 41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
  • 42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
  • 43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
  • 44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
  • 45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
  • 46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
  • 47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
  • 48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
  • 49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
  • 50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
  • 51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
  • 52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
  • 53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
  • 54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
  • 55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
  • 56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
  • 57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
  • 58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
  • 59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
  • 60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
  • 61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
  • 62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
  • 63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
  • 64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
  • 65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
  • 66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
  • 67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
  • 68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
  • 69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
  • 70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
  • 71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
  • 72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
  • 73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
  • 74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
  • 75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
  • 76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
  • 77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
  • 78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
  • 79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
  • 80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
  • 81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
  • 82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
  • 83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
  • 84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
  • 85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
  • 86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
  • 87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
  • 88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
  • 89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
  • 90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
  • 91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
  • 92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
  • 93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
  • 94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
  • 95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
  • 96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
  • 97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
  • 98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
  • 99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
  • 100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
  • 101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
  • 102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
  • 103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
  • 104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
  • 105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
  • 106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
  • 107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
  • 108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
  • 109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
  • 110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
  • 111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
  • 112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
  • 113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
  • 114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
  • 115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
  • 116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
  • 117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
  • 118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
  • 119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
  • 120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
  • 121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
  • 122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
  • 123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
  • 124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
  • 125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
  • 126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
  • 127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
  • 128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
  • 129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
  • 130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
  • 131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
  • 132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
  • 133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
  • 134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
  • 135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
  • 136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
  • 137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
  • 138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
  • 139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
  • 140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
  • 141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
  • 142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
  • 143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
  • 144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
  • 145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
  • 146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
  • 147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
  • 148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
  • 149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
  • 150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
  • 151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
  • 152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
  • 153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
  • 154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
  • 155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
  • 156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
  • 157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
  • 158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
  • 159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
  • 160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
  • 161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
  • 162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
  • 163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
  • 164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
  • 165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
  • 166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
  • 167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
  • 168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
  • 169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
  • 170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
  • 171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
  • 172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
  • 173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
  • 174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
  • 175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
  • 176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
  • 177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
  • 178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
  • 179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
  • 180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
  • 181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
  • 182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
  • 183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
  • 184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
  • 185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
  • 186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
  • 187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
  • 188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
  • 189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
  • 190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
  • 191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
  • 192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
  • 193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
  • 194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
  • 195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
  • 196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
  • 197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
  • 198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
  • 199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
  • 200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
  • 201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
  • 202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
  • 203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
  • 204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
  • 205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
  • 206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
  • 207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
  • 208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
  • 209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
  • 210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
  • 211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
  • 212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
  • 213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
  • 214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
  • 215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
  • 216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
  • 217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
  • 218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
  • 219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
  • 220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
  • 221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
  • 222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
  • 223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
  • 224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
  • 225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
  • 226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
  • 227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
  • 228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
  • 229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
  • 230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
  • 231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
  • 232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
  • 233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
  • 234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
  • 235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
  • 236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
  • 237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
  • 238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
  • 239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
  • 240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
  • 241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
  • 242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
  • 243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
  • 244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
  • 245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
  • 246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
  • 247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
  • 248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
  • 249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
  • 250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
  • 251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
  • 252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
  • 253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
  • 254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
  • 255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ15:8Channel Transfer Start IRQ bits
  • 0 Interrupt 0 will initiate a DMA transfer
  • 1 Interrupt 1 will initiate a DMA transfer
  • 2 Interrupt 2 will initiate a DMA transfer
  • 3 Interrupt 3 will initiate a DMA transfer
  • 4 Interrupt 4 will initiate a DMA transfer
  • 5 Interrupt 5 will initiate a DMA transfer
  • 6 Interrupt 6 will initiate a DMA transfer
  • 7 Interrupt 7 will initiate a DMA transfer
  • 8 Interrupt 8 will initiate a DMA transfer
  • 9 Interrupt 9 will initiate a DMA transfer
  • 10 Interrupt 10 will initiate a DMA transfer
  • 11 Interrupt 11 will initiate a DMA transfer
  • 12 Interrupt 12 will initiate a DMA transfer
  • 13 Interrupt 13 will initiate a DMA transfer
  • 14 Interrupt 14 will initiate a DMA transfer
  • 15 Interrupt 15 will initiate a DMA transfer
  • 16 Interrupt 16 will initiate a DMA transfer
  • 17 Interrupt 17 will initiate a DMA transfer
  • 18 Interrupt 18 will initiate a DMA transfer
  • 19 Interrupt 19 will initiate a DMA transfer
  • 20 Interrupt 20 will initiate a DMA transfer
  • 21 Interrupt 21 will initiate a DMA transfer
  • 22 Interrupt 22 will initiate a DMA transfer
  • 23 Interrupt 23 will initiate a DMA transfer
  • 24 Interrupt 24 will initiate a DMA transfer
  • 25 Interrupt 25 will initiate a DMA transfer
  • 26 Interrupt 26 will initiate a DMA transfer
  • 27 Interrupt 27 will initiate a DMA transfer
  • 28 Interrupt 28 will initiate a DMA transfer
  • 29 Interrupt 29 will initiate a DMA transfer
  • 30 Interrupt 30 will initiate a DMA transfer
  • 31 Interrupt 31 will initiate a DMA transfer
  • 32 Interrupt 32 will initiate a DMA transfer
  • 33 Interrupt 33 will initiate a DMA transfer
  • 34 Interrupt 34 will initiate a DMA transfer
  • 35 Interrupt 35 will initiate a DMA transfer
  • 36 Interrupt 36 will initiate a DMA transfer
  • 37 Interrupt 37 will initiate a DMA transfer
  • 38 Interrupt 38 will initiate a DMA transfer
  • 39 Interrupt 39 will initiate a DMA transfer
  • 40 Interrupt 40 will initiate a DMA transfer
  • 41 Interrupt 41 will initiate a DMA transfer
  • 42 Interrupt 42 will initiate a DMA transfer
  • 43 Interrupt 43 will initiate a DMA transfer
  • 44 Interrupt 44 will initiate a DMA transfer
  • 45 Interrupt 45 will initiate a DMA transfer
  • 46 Interrupt 46 will initiate a DMA transfer
  • 47 Interrupt 47 will initiate a DMA transfer
  • 48 Interrupt 48 will initiate a DMA transfer
  • 49 Interrupt 49 will initiate a DMA transfer
  • 50 Interrupt 50 will initiate a DMA transfer
  • 51 Interrupt 51 will initiate a DMA transfer
  • 52 Interrupt 52 will initiate a DMA transfer
  • 53 Interrupt 53 will initiate a DMA transfer
  • 54 Interrupt 54 will initiate a DMA transfer
  • 55 Interrupt 55 will initiate a DMA transfer
  • 56 Interrupt 56 will initiate a DMA transfer
  • 57 Interrupt 57 will initiate a DMA transfer
  • 58 Interrupt 58 will initiate a DMA transfer
  • 59 Interrupt 59 will initiate a DMA transfer
  • 60 Interrupt 60 will initiate a DMA transfer
  • 61 Interrupt 61 will initiate a DMA transfer
  • 62 Interrupt 62 will initiate a DMA transfer
  • 63 Interrupt 63 will initiate a DMA transfer
  • 64 Interrupt 64 will initiate a DMA transfer
  • 65 Interrupt 65 will initiate a DMA transfer
  • 66 Interrupt 66 will initiate a DMA transfer
  • 67 Interrupt 67 will initiate a DMA transfer
  • 68 Interrupt 68 will initiate a DMA transfer
  • 69 Interrupt 69 will initiate a DMA transfer
  • 70 Interrupt 70 will initiate a DMA transfer
  • 71 Interrupt 71 will initiate a DMA transfer
  • 72 Interrupt 72 will initiate a DMA transfer
  • 73 Interrupt 73 will initiate a DMA transfer
  • 74 Interrupt 74 will initiate a DMA transfer
  • 75 Interrupt 75 will initiate a DMA transfer
  • 76 Interrupt 76 will initiate a DMA transfer
  • 77 Interrupt 77 will initiate a DMA transfer
  • 78 Interrupt 78 will initiate a DMA transfer
  • 79 Interrupt 79 will initiate a DMA transfer
  • 80 Interrupt 80 will initiate a DMA transfer
  • 81 Interrupt 81 will initiate a DMA transfer
  • 82 Interrupt 82 will initiate a DMA transfer
  • 83 Interrupt 83 will initiate a DMA transfer
  • 84 Interrupt 84 will initiate a DMA transfer
  • 85 Interrupt 85 will initiate a DMA transfer
  • 86 Interrupt 86 will initiate a DMA transfer
  • 87 Interrupt 87 will initiate a DMA transfer
  • 88 Interrupt 88 will initiate a DMA transfer
  • 89 Interrupt 89 will initiate a DMA transfer
  • 90 Interrupt 90 will initiate a DMA transfer
  • 91 Interrupt 91 will initiate a DMA transfer
  • 92 Interrupt 92 will initiate a DMA transfer
  • 93 Interrupt 93 will initiate a DMA transfer
  • 94 Interrupt 94 will initiate a DMA transfer
  • 95 Interrupt 95 will initiate a DMA transfer
  • 96 Interrupt 96 will initiate a DMA transfer
  • 97 Interrupt 97 will initiate a DMA transfer
  • 98 Interrupt 98 will initiate a DMA transfer
  • 99 Interrupt 99 will initiate a DMA transfer
  • 100 Interrupt 100 will initiate a DMA transfer
  • 101 Interrupt 101 will initiate a DMA transfer
  • 102 Interrupt 102 will initiate a DMA transfer
  • 103 Interrupt 103 will initiate a DMA transfer
  • 104 Interrupt 104 will initiate a DMA transfer
  • 105 Interrupt 105 will initiate a DMA transfer
  • 106 Interrupt 106 will initiate a DMA transfer
  • 107 Interrupt 107 will initiate a DMA transfer
  • 108 Interrupt 108 will initiate a DMA transfer
  • 109 Interrupt 109 will initiate a DMA transfer
  • 110 Interrupt 110 will initiate a DMA transfer
  • 111 Interrupt 111 will initiate a DMA transfer
  • 112 Interrupt 112 will initiate a DMA transfer
  • 113 Interrupt 113 will initiate a DMA transfer
  • 114 Interrupt 114 will initiate a DMA transfer
  • 115 Interrupt 115 will initiate a DMA transfer
  • 116 Interrupt 116 will initiate a DMA transfer
  • 117 Interrupt 117 will initiate a DMA transfer
  • 118 Interrupt 118 will initiate a DMA transfer
  • 119 Interrupt 119 will initiate a DMA transfer
  • 120 Interrupt 120 will initiate a DMA transfer
  • 121 Interrupt 121 will initiate a DMA transfer
  • 122 Interrupt 122 will initiate a DMA transfer
  • 123 Interrupt 123 will initiate a DMA transfer
  • 124 Interrupt 124 will initiate a DMA transfer
  • 125 Interrupt 125 will initiate a DMA transfer
  • 126 Interrupt 126 will initiate a DMA transfer
  • 127 Interrupt 127 will initiate a DMA transfer
  • 128 Interrupt 128 will initiate a DMA transfer
  • 129 Interrupt 129 will initiate a DMA transfer
  • 130 Interrupt 130 will initiate a DMA transfer
  • 131 Interrupt 131 will initiate a DMA transfer
  • 132 Interrupt 132 will initiate a DMA transfer
  • 133 Interrupt 133 will initiate a DMA transfer
  • 134 Interrupt 134 will initiate a DMA transfer
  • 135 Interrupt 135 will initiate a DMA transfer
  • 136 Interrupt 136 will initiate a DMA transfer
  • 137 Interrupt 137 will initiate a DMA transfer
  • 138 Interrupt 138 will initiate a DMA transfer
  • 139 Interrupt 139 will initiate a DMA transfer
  • 140 Interrupt 140 will initiate a DMA transfer
  • 141 Interrupt 141 will initiate a DMA transfer
  • 142 Interrupt 142 will initiate a DMA transfer
  • 143 Interrupt 143 will initiate a DMA transfer
  • 144 Interrupt 144 will initiate a DMA transfer
  • 145 Interrupt 145 will initiate a DMA transfer
  • 146 Interrupt 146 will initiate a DMA transfer
  • 147 Interrupt 147 will initiate a DMA transfer
  • 148 Interrupt 148 will initiate a DMA transfer
  • 149 Interrupt 149 will initiate a DMA transfer
  • 150 Interrupt 150 will initiate a DMA transfer
  • 151 Interrupt 151 will initiate a DMA transfer
  • 152 Interrupt 152 will initiate a DMA transfer
  • 153 Interrupt 153 will initiate a DMA transfer
  • 154 Interrupt 154 will initiate a DMA transfer
  • 155 Interrupt 155 will initiate a DMA transfer
  • 156 Interrupt 156 will initiate a DMA transfer
  • 157 Interrupt 157 will initiate a DMA transfer
  • 158 Interrupt 158 will initiate a DMA transfer
  • 159 Interrupt 159 will initiate a DMA transfer
  • 160 Interrupt 160 will initiate a DMA transfer
  • 161 Interrupt 161 will initiate a DMA transfer
  • 162 Interrupt 162 will initiate a DMA transfer
  • 163 Interrupt 163 will initiate a DMA transfer
  • 164 Interrupt 164 will initiate a DMA transfer
  • 165 Interrupt 165 will initiate a DMA transfer
  • 166 Interrupt 166 will initiate a DMA transfer
  • 167 Interrupt 167 will initiate a DMA transfer
  • 168 Interrupt 168 will initiate a DMA transfer
  • 169 Interrupt 169 will initiate a DMA transfer
  • 170 Interrupt 170 will initiate a DMA transfer
  • 171 Interrupt 171 will initiate a DMA transfer
  • 172 Interrupt 172 will initiate a DMA transfer
  • 173 Interrupt 173 will initiate a DMA transfer
  • 174 Interrupt 174 will initiate a DMA transfer
  • 175 Interrupt 175 will initiate a DMA transfer
  • 176 Interrupt 176 will initiate a DMA transfer
  • 177 Interrupt 177 will initiate a DMA transfer
  • 178 Interrupt 178 will initiate a DMA transfer
  • 179 Interrupt 179 will initiate a DMA transfer
  • 180 Interrupt 180 will initiate a DMA transfer
  • 181 Interrupt 181 will initiate a DMA transfer
  • 182 Interrupt 182 will initiate a DMA transfer
  • 183 Interrupt 183 will initiate a DMA transfer
  • 184 Interrupt 184 will initiate a DMA transfer
  • 185 Interrupt 185 will initiate a DMA transfer
  • 186 Interrupt 186 will initiate a DMA transfer
  • 187 Interrupt 187 will initiate a DMA transfer
  • 188 Interrupt 188 will initiate a DMA transfer
  • 189 Interrupt 189 will initiate a DMA transfer
  • 190 Interrupt 190 will initiate a DMA transfer
  • 191 Interrupt 191 will initiate a DMA transfer
  • 192 Interrupt 192 will initiate a DMA transfer
  • 193 Interrupt 193 will initiate a DMA transfer
  • 194 Interrupt 194 will initiate a DMA transfer
  • 195 Interrupt 195 will initiate a DMA transfer
  • 196 Interrupt 196 will initiate a DMA transfer
  • 197 Interrupt 197 will initiate a DMA transfer
  • 198 Interrupt 198 will initiate a DMA transfer
  • 199 Interrupt 199 will initiate a DMA transfer
  • 200 Interrupt 200 will initiate a DMA transfer
  • 201 Interrupt 201 will initiate a DMA transfer
  • 202 Interrupt 202 will initiate a DMA transfer
  • 203 Interrupt 203 will initiate a DMA transfer
  • 204 Interrupt 204 will initiate a DMA transfer
  • 205 Interrupt 205 will initiate a DMA transfer
  • 206 Interrupt 206 will initiate a DMA transfer
  • 207 Interrupt 207 will initiate a DMA transfer
  • 208 Interrupt 208 will initiate a DMA transfer
  • 209 Interrupt 209 will initiate a DMA transfer
  • 210 Interrupt 210 will initiate a DMA transfer
  • 211 Interrupt 211 will initiate a DMA transfer
  • 212 Interrupt 212 will initiate a DMA transfer
  • 213 Interrupt 213 will initiate a DMA transfer
  • 214 Interrupt 214 will initiate a DMA transfer
  • 215 Interrupt 215 will initiate a DMA transfer
  • 216 Interrupt 216 will initiate a DMA transfer
  • 217 Interrupt 217 will initiate a DMA transfer
  • 218 Interrupt 218 will initiate a DMA transfer
  • 219 Interrupt 219 will initiate a DMA transfer
  • 220 Interrupt 220 will initiate a DMA transfer
  • 221 Interrupt 221 will initiate a DMA transfer
  • 222 Interrupt 222 will initiate a DMA transfer
  • 223 Interrupt 223 will initiate a DMA transfer
  • 224 Interrupt 224 will initiate a DMA transfer
  • 225 Interrupt 225 will initiate a DMA transfer
  • 226 Interrupt 226 will initiate a DMA transfer
  • 227 Interrupt 227 will initiate a DMA transfer
  • 228 Interrupt 228 will initiate a DMA transfer
  • 229 Interrupt 229 will initiate a DMA transfer
  • 230 Interrupt 230 will initiate a DMA transfer
  • 231 Interrupt 231 will initiate a DMA transfer
  • 232 Interrupt 232 will initiate a DMA transfer
  • 233 Interrupt 233 will initiate a DMA transfer
  • 234 Interrupt 234 will initiate a DMA transfer
  • 235 Interrupt 235 will initiate a DMA transfer
  • 236 Interrupt 236 will initiate a DMA transfer
  • 237 Interrupt 237 will initiate a DMA transfer
  • 238 Interrupt 238 will initiate a DMA transfer
  • 239 Interrupt 239 will initiate a DMA transfer
  • 240 Interrupt 240 will initiate a DMA transfer
  • 241 Interrupt 241 will initiate a DMA transfer
  • 242 Interrupt 242 will initiate a DMA transfer
  • 243 Interrupt 243 will initiate a DMA transfer
  • 244 Interrupt 244 will initiate a DMA transfer
  • 245 Interrupt 245 will initiate a DMA transfer
  • 246 Interrupt 246 will initiate a DMA transfer
  • 247 Interrupt 247 will initiate a DMA transfer
  • 248 Interrupt 248 will initiate a DMA transfer
  • 249 Interrupt 249 will initiate a DMA transfer
  • 250 Interrupt 250 will initiate a DMA transfer
  • 251 Interrupt 251 will initiate a DMA transfer
  • 252 Interrupt 252 will initiate a DMA transfer
  • 253 Interrupt 253 will initiate a DMA transfer
  • 254 Interrupt 254 will initiate a DMA transfer
  • 255 Interrupt 255 will initiate a DMA transfer
CFORCE7DMA Forced Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT6DMA Abort Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is aborted when this bit is written to a 1
PATEN5Channel Pattern Match Abort Enable bit
  • 0 Pattern match is disabled
  • 1 Abort transfer and clear CHEN on pattern match
SIRQEN4Channel Start IRQ Enable bit
  • 0 Interrupt number CHSIRQ is ignored and does not start a transfer
  • 1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN3Channel Abort IRQ Enable bit
  • 0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
  • 1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs

DCH0INTDMA Channel x Interrupt Control Register

Address
0xBF883080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CHSDIE23Channel Source Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSHIE22Channel Source Half Empty Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDDIE21Channel Destination Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDHIE20Channel Destination Half Full Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHBCIE19Channel Block Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHCCIE18Channel Cell Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHTAIE17Channel Transfer Abort Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHERIE16Channel Address Error Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSDIF7Channel Source Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF6Channel Source Half Empty Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF5Channel Destination Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF4Channel Destination Half Full Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF3Channel Block Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF2Channel Cell Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF1Channel Transfer Abort Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF0Channel Address Error Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A channel address error has been detected. Either the source or the destination address is invalid.

DCH0SSADMA Channel x Source Start Address Register

Address
0xBF883090
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0DSADMA Channel x Destination Start Address Register

Address
0xBF8830A0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0SSIZDMA Channel x Source Size Register

Address
0xBF8830B0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0DSIZDMA Channel x Destination Size Register

Address
0xBF8830C0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0SPTRDMA Channel x Source Pointer Register

Address
0xBF8830D0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0DPTRDMA Channel x Destination Pointer Register

Address
0xBF8830E0
Reset
0x00000000
Access
read only
Size
32-bit

DCH0CSIZDMA Channel x Cell-Size Register

Address
0xBF8830F0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0CPTRDMA Channel x Cell Pointer Register

Address
0xBF883100
Reset
0x00000000
Access
read/write
Size
32-bit

DCH0DATDMA Channel x Pattern Data Register

Address
0xBF883110
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1 DMA channel 1

DCH1CONDMA Channel x Control Register

Address
0xBF883120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CHBUSY15Channel Busy bit
  • 0 Channel is inactive or has been disabled
  • 1 Channel is active or has been enabled
CHCHNS8Chain Channel Selection bit
  • 0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
  • 1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN7Channel Enable bit
  • 0 Channel is disabled
  • 1 Channel is enabled
CHAED6Channel Allow Events If Disabled bit
  • 0 Channel start/abort events will be ignored if the channel is disabled
  • 1 Channel start/abort events will be registered even if the channel is disabled
CHCHN5Channel Chain Enable bit
  • 0 Do not allow channel to be chained
  • 1 Allow channel to be chained
CHAEN4Channel Automatic Enable bit
  • 0 Channel is disabled on block transfer complete
  • 1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET2Channel Event Detected bit
  • 0 No events have been detected
  • 1 An event has been detected
CHPRI1:0Channel Priority bits
  • 0 Channel has priority 0
  • 1 Channel has priority 1
  • 2 Channel has priority 2
  • 3 Channel has priority 3 (highest)

DCH1ECONDMA Channel x Event Control Register

Address
0xBF883130
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
CHAIRQ23:16Channel Transfer Abort IRQ bits
  • 0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
  • 1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
  • 2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
  • 3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
  • 4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
  • 5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
  • 6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
  • 7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
  • 8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
  • 9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
  • 10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
  • 11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
  • 12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
  • 13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
  • 14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
  • 15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
  • 16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
  • 17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
  • 18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
  • 19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
  • 20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
  • 21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
  • 22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
  • 23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
  • 24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
  • 25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
  • 26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
  • 27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
  • 28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
  • 29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
  • 30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
  • 31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
  • 32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
  • 33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
  • 34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
  • 35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
  • 36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
  • 37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
  • 38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
  • 39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
  • 40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
  • 41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
  • 42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
  • 43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
  • 44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
  • 45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
  • 46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
  • 47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
  • 48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
  • 49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
  • 50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
  • 51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
  • 52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
  • 53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
  • 54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
  • 55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
  • 56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
  • 57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
  • 58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
  • 59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
  • 60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
  • 61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
  • 62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
  • 63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
  • 64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
  • 65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
  • 66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
  • 67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
  • 68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
  • 69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
  • 70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
  • 71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
  • 72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
  • 73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
  • 74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
  • 75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
  • 76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
  • 77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
  • 78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
  • 79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
  • 80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
  • 81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
  • 82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
  • 83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
  • 84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
  • 85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
  • 86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
  • 87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
  • 88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
  • 89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
  • 90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
  • 91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
  • 92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
  • 93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
  • 94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
  • 95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
  • 96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
  • 97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
  • 98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
  • 99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
  • 100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
  • 101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
  • 102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
  • 103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
  • 104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
  • 105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
  • 106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
  • 107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
  • 108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
  • 109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
  • 110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
  • 111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
  • 112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
  • 113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
  • 114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
  • 115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
  • 116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
  • 117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
  • 118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
  • 119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
  • 120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
  • 121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
  • 122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
  • 123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
  • 124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
  • 125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
  • 126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
  • 127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
  • 128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
  • 129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
  • 130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
  • 131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
  • 132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
  • 133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
  • 134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
  • 135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
  • 136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
  • 137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
  • 138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
  • 139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
  • 140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
  • 141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
  • 142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
  • 143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
  • 144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
  • 145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
  • 146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
  • 147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
  • 148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
  • 149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
  • 150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
  • 151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
  • 152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
  • 153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
  • 154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
  • 155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
  • 156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
  • 157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
  • 158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
  • 159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
  • 160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
  • 161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
  • 162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
  • 163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
  • 164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
  • 165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
  • 166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
  • 167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
  • 168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
  • 169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
  • 170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
  • 171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
  • 172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
  • 173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
  • 174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
  • 175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
  • 176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
  • 177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
  • 178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
  • 179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
  • 180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
  • 181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
  • 182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
  • 183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
  • 184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
  • 185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
  • 186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
  • 187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
  • 188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
  • 189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
  • 190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
  • 191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
  • 192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
  • 193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
  • 194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
  • 195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
  • 196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
  • 197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
  • 198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
  • 199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
  • 200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
  • 201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
  • 202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
  • 203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
  • 204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
  • 205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
  • 206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
  • 207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
  • 208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
  • 209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
  • 210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
  • 211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
  • 212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
  • 213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
  • 214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
  • 215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
  • 216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
  • 217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
  • 218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
  • 219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
  • 220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
  • 221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
  • 222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
  • 223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
  • 224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
  • 225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
  • 226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
  • 227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
  • 228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
  • 229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
  • 230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
  • 231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
  • 232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
  • 233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
  • 234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
  • 235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
  • 236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
  • 237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
  • 238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
  • 239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
  • 240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
  • 241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
  • 242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
  • 243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
  • 244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
  • 245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
  • 246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
  • 247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
  • 248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
  • 249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
  • 250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
  • 251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
  • 252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
  • 253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
  • 254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
  • 255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ15:8Channel Transfer Start IRQ bits
  • 0 Interrupt 0 will initiate a DMA transfer
  • 1 Interrupt 1 will initiate a DMA transfer
  • 2 Interrupt 2 will initiate a DMA transfer
  • 3 Interrupt 3 will initiate a DMA transfer
  • 4 Interrupt 4 will initiate a DMA transfer
  • 5 Interrupt 5 will initiate a DMA transfer
  • 6 Interrupt 6 will initiate a DMA transfer
  • 7 Interrupt 7 will initiate a DMA transfer
  • 8 Interrupt 8 will initiate a DMA transfer
  • 9 Interrupt 9 will initiate a DMA transfer
  • 10 Interrupt 10 will initiate a DMA transfer
  • 11 Interrupt 11 will initiate a DMA transfer
  • 12 Interrupt 12 will initiate a DMA transfer
  • 13 Interrupt 13 will initiate a DMA transfer
  • 14 Interrupt 14 will initiate a DMA transfer
  • 15 Interrupt 15 will initiate a DMA transfer
  • 16 Interrupt 16 will initiate a DMA transfer
  • 17 Interrupt 17 will initiate a DMA transfer
  • 18 Interrupt 18 will initiate a DMA transfer
  • 19 Interrupt 19 will initiate a DMA transfer
  • 20 Interrupt 20 will initiate a DMA transfer
  • 21 Interrupt 21 will initiate a DMA transfer
  • 22 Interrupt 22 will initiate a DMA transfer
  • 23 Interrupt 23 will initiate a DMA transfer
  • 24 Interrupt 24 will initiate a DMA transfer
  • 25 Interrupt 25 will initiate a DMA transfer
  • 26 Interrupt 26 will initiate a DMA transfer
  • 27 Interrupt 27 will initiate a DMA transfer
  • 28 Interrupt 28 will initiate a DMA transfer
  • 29 Interrupt 29 will initiate a DMA transfer
  • 30 Interrupt 30 will initiate a DMA transfer
  • 31 Interrupt 31 will initiate a DMA transfer
  • 32 Interrupt 32 will initiate a DMA transfer
  • 33 Interrupt 33 will initiate a DMA transfer
  • 34 Interrupt 34 will initiate a DMA transfer
  • 35 Interrupt 35 will initiate a DMA transfer
  • 36 Interrupt 36 will initiate a DMA transfer
  • 37 Interrupt 37 will initiate a DMA transfer
  • 38 Interrupt 38 will initiate a DMA transfer
  • 39 Interrupt 39 will initiate a DMA transfer
  • 40 Interrupt 40 will initiate a DMA transfer
  • 41 Interrupt 41 will initiate a DMA transfer
  • 42 Interrupt 42 will initiate a DMA transfer
  • 43 Interrupt 43 will initiate a DMA transfer
  • 44 Interrupt 44 will initiate a DMA transfer
  • 45 Interrupt 45 will initiate a DMA transfer
  • 46 Interrupt 46 will initiate a DMA transfer
  • 47 Interrupt 47 will initiate a DMA transfer
  • 48 Interrupt 48 will initiate a DMA transfer
  • 49 Interrupt 49 will initiate a DMA transfer
  • 50 Interrupt 50 will initiate a DMA transfer
  • 51 Interrupt 51 will initiate a DMA transfer
  • 52 Interrupt 52 will initiate a DMA transfer
  • 53 Interrupt 53 will initiate a DMA transfer
  • 54 Interrupt 54 will initiate a DMA transfer
  • 55 Interrupt 55 will initiate a DMA transfer
  • 56 Interrupt 56 will initiate a DMA transfer
  • 57 Interrupt 57 will initiate a DMA transfer
  • 58 Interrupt 58 will initiate a DMA transfer
  • 59 Interrupt 59 will initiate a DMA transfer
  • 60 Interrupt 60 will initiate a DMA transfer
  • 61 Interrupt 61 will initiate a DMA transfer
  • 62 Interrupt 62 will initiate a DMA transfer
  • 63 Interrupt 63 will initiate a DMA transfer
  • 64 Interrupt 64 will initiate a DMA transfer
  • 65 Interrupt 65 will initiate a DMA transfer
  • 66 Interrupt 66 will initiate a DMA transfer
  • 67 Interrupt 67 will initiate a DMA transfer
  • 68 Interrupt 68 will initiate a DMA transfer
  • 69 Interrupt 69 will initiate a DMA transfer
  • 70 Interrupt 70 will initiate a DMA transfer
  • 71 Interrupt 71 will initiate a DMA transfer
  • 72 Interrupt 72 will initiate a DMA transfer
  • 73 Interrupt 73 will initiate a DMA transfer
  • 74 Interrupt 74 will initiate a DMA transfer
  • 75 Interrupt 75 will initiate a DMA transfer
  • 76 Interrupt 76 will initiate a DMA transfer
  • 77 Interrupt 77 will initiate a DMA transfer
  • 78 Interrupt 78 will initiate a DMA transfer
  • 79 Interrupt 79 will initiate a DMA transfer
  • 80 Interrupt 80 will initiate a DMA transfer
  • 81 Interrupt 81 will initiate a DMA transfer
  • 82 Interrupt 82 will initiate a DMA transfer
  • 83 Interrupt 83 will initiate a DMA transfer
  • 84 Interrupt 84 will initiate a DMA transfer
  • 85 Interrupt 85 will initiate a DMA transfer
  • 86 Interrupt 86 will initiate a DMA transfer
  • 87 Interrupt 87 will initiate a DMA transfer
  • 88 Interrupt 88 will initiate a DMA transfer
  • 89 Interrupt 89 will initiate a DMA transfer
  • 90 Interrupt 90 will initiate a DMA transfer
  • 91 Interrupt 91 will initiate a DMA transfer
  • 92 Interrupt 92 will initiate a DMA transfer
  • 93 Interrupt 93 will initiate a DMA transfer
  • 94 Interrupt 94 will initiate a DMA transfer
  • 95 Interrupt 95 will initiate a DMA transfer
  • 96 Interrupt 96 will initiate a DMA transfer
  • 97 Interrupt 97 will initiate a DMA transfer
  • 98 Interrupt 98 will initiate a DMA transfer
  • 99 Interrupt 99 will initiate a DMA transfer
  • 100 Interrupt 100 will initiate a DMA transfer
  • 101 Interrupt 101 will initiate a DMA transfer
  • 102 Interrupt 102 will initiate a DMA transfer
  • 103 Interrupt 103 will initiate a DMA transfer
  • 104 Interrupt 104 will initiate a DMA transfer
  • 105 Interrupt 105 will initiate a DMA transfer
  • 106 Interrupt 106 will initiate a DMA transfer
  • 107 Interrupt 107 will initiate a DMA transfer
  • 108 Interrupt 108 will initiate a DMA transfer
  • 109 Interrupt 109 will initiate a DMA transfer
  • 110 Interrupt 110 will initiate a DMA transfer
  • 111 Interrupt 111 will initiate a DMA transfer
  • 112 Interrupt 112 will initiate a DMA transfer
  • 113 Interrupt 113 will initiate a DMA transfer
  • 114 Interrupt 114 will initiate a DMA transfer
  • 115 Interrupt 115 will initiate a DMA transfer
  • 116 Interrupt 116 will initiate a DMA transfer
  • 117 Interrupt 117 will initiate a DMA transfer
  • 118 Interrupt 118 will initiate a DMA transfer
  • 119 Interrupt 119 will initiate a DMA transfer
  • 120 Interrupt 120 will initiate a DMA transfer
  • 121 Interrupt 121 will initiate a DMA transfer
  • 122 Interrupt 122 will initiate a DMA transfer
  • 123 Interrupt 123 will initiate a DMA transfer
  • 124 Interrupt 124 will initiate a DMA transfer
  • 125 Interrupt 125 will initiate a DMA transfer
  • 126 Interrupt 126 will initiate a DMA transfer
  • 127 Interrupt 127 will initiate a DMA transfer
  • 128 Interrupt 128 will initiate a DMA transfer
  • 129 Interrupt 129 will initiate a DMA transfer
  • 130 Interrupt 130 will initiate a DMA transfer
  • 131 Interrupt 131 will initiate a DMA transfer
  • 132 Interrupt 132 will initiate a DMA transfer
  • 133 Interrupt 133 will initiate a DMA transfer
  • 134 Interrupt 134 will initiate a DMA transfer
  • 135 Interrupt 135 will initiate a DMA transfer
  • 136 Interrupt 136 will initiate a DMA transfer
  • 137 Interrupt 137 will initiate a DMA transfer
  • 138 Interrupt 138 will initiate a DMA transfer
  • 139 Interrupt 139 will initiate a DMA transfer
  • 140 Interrupt 140 will initiate a DMA transfer
  • 141 Interrupt 141 will initiate a DMA transfer
  • 142 Interrupt 142 will initiate a DMA transfer
  • 143 Interrupt 143 will initiate a DMA transfer
  • 144 Interrupt 144 will initiate a DMA transfer
  • 145 Interrupt 145 will initiate a DMA transfer
  • 146 Interrupt 146 will initiate a DMA transfer
  • 147 Interrupt 147 will initiate a DMA transfer
  • 148 Interrupt 148 will initiate a DMA transfer
  • 149 Interrupt 149 will initiate a DMA transfer
  • 150 Interrupt 150 will initiate a DMA transfer
  • 151 Interrupt 151 will initiate a DMA transfer
  • 152 Interrupt 152 will initiate a DMA transfer
  • 153 Interrupt 153 will initiate a DMA transfer
  • 154 Interrupt 154 will initiate a DMA transfer
  • 155 Interrupt 155 will initiate a DMA transfer
  • 156 Interrupt 156 will initiate a DMA transfer
  • 157 Interrupt 157 will initiate a DMA transfer
  • 158 Interrupt 158 will initiate a DMA transfer
  • 159 Interrupt 159 will initiate a DMA transfer
  • 160 Interrupt 160 will initiate a DMA transfer
  • 161 Interrupt 161 will initiate a DMA transfer
  • 162 Interrupt 162 will initiate a DMA transfer
  • 163 Interrupt 163 will initiate a DMA transfer
  • 164 Interrupt 164 will initiate a DMA transfer
  • 165 Interrupt 165 will initiate a DMA transfer
  • 166 Interrupt 166 will initiate a DMA transfer
  • 167 Interrupt 167 will initiate a DMA transfer
  • 168 Interrupt 168 will initiate a DMA transfer
  • 169 Interrupt 169 will initiate a DMA transfer
  • 170 Interrupt 170 will initiate a DMA transfer
  • 171 Interrupt 171 will initiate a DMA transfer
  • 172 Interrupt 172 will initiate a DMA transfer
  • 173 Interrupt 173 will initiate a DMA transfer
  • 174 Interrupt 174 will initiate a DMA transfer
  • 175 Interrupt 175 will initiate a DMA transfer
  • 176 Interrupt 176 will initiate a DMA transfer
  • 177 Interrupt 177 will initiate a DMA transfer
  • 178 Interrupt 178 will initiate a DMA transfer
  • 179 Interrupt 179 will initiate a DMA transfer
  • 180 Interrupt 180 will initiate a DMA transfer
  • 181 Interrupt 181 will initiate a DMA transfer
  • 182 Interrupt 182 will initiate a DMA transfer
  • 183 Interrupt 183 will initiate a DMA transfer
  • 184 Interrupt 184 will initiate a DMA transfer
  • 185 Interrupt 185 will initiate a DMA transfer
  • 186 Interrupt 186 will initiate a DMA transfer
  • 187 Interrupt 187 will initiate a DMA transfer
  • 188 Interrupt 188 will initiate a DMA transfer
  • 189 Interrupt 189 will initiate a DMA transfer
  • 190 Interrupt 190 will initiate a DMA transfer
  • 191 Interrupt 191 will initiate a DMA transfer
  • 192 Interrupt 192 will initiate a DMA transfer
  • 193 Interrupt 193 will initiate a DMA transfer
  • 194 Interrupt 194 will initiate a DMA transfer
  • 195 Interrupt 195 will initiate a DMA transfer
  • 196 Interrupt 196 will initiate a DMA transfer
  • 197 Interrupt 197 will initiate a DMA transfer
  • 198 Interrupt 198 will initiate a DMA transfer
  • 199 Interrupt 199 will initiate a DMA transfer
  • 200 Interrupt 200 will initiate a DMA transfer
  • 201 Interrupt 201 will initiate a DMA transfer
  • 202 Interrupt 202 will initiate a DMA transfer
  • 203 Interrupt 203 will initiate a DMA transfer
  • 204 Interrupt 204 will initiate a DMA transfer
  • 205 Interrupt 205 will initiate a DMA transfer
  • 206 Interrupt 206 will initiate a DMA transfer
  • 207 Interrupt 207 will initiate a DMA transfer
  • 208 Interrupt 208 will initiate a DMA transfer
  • 209 Interrupt 209 will initiate a DMA transfer
  • 210 Interrupt 210 will initiate a DMA transfer
  • 211 Interrupt 211 will initiate a DMA transfer
  • 212 Interrupt 212 will initiate a DMA transfer
  • 213 Interrupt 213 will initiate a DMA transfer
  • 214 Interrupt 214 will initiate a DMA transfer
  • 215 Interrupt 215 will initiate a DMA transfer
  • 216 Interrupt 216 will initiate a DMA transfer
  • 217 Interrupt 217 will initiate a DMA transfer
  • 218 Interrupt 218 will initiate a DMA transfer
  • 219 Interrupt 219 will initiate a DMA transfer
  • 220 Interrupt 220 will initiate a DMA transfer
  • 221 Interrupt 221 will initiate a DMA transfer
  • 222 Interrupt 222 will initiate a DMA transfer
  • 223 Interrupt 223 will initiate a DMA transfer
  • 224 Interrupt 224 will initiate a DMA transfer
  • 225 Interrupt 225 will initiate a DMA transfer
  • 226 Interrupt 226 will initiate a DMA transfer
  • 227 Interrupt 227 will initiate a DMA transfer
  • 228 Interrupt 228 will initiate a DMA transfer
  • 229 Interrupt 229 will initiate a DMA transfer
  • 230 Interrupt 230 will initiate a DMA transfer
  • 231 Interrupt 231 will initiate a DMA transfer
  • 232 Interrupt 232 will initiate a DMA transfer
  • 233 Interrupt 233 will initiate a DMA transfer
  • 234 Interrupt 234 will initiate a DMA transfer
  • 235 Interrupt 235 will initiate a DMA transfer
  • 236 Interrupt 236 will initiate a DMA transfer
  • 237 Interrupt 237 will initiate a DMA transfer
  • 238 Interrupt 238 will initiate a DMA transfer
  • 239 Interrupt 239 will initiate a DMA transfer
  • 240 Interrupt 240 will initiate a DMA transfer
  • 241 Interrupt 241 will initiate a DMA transfer
  • 242 Interrupt 242 will initiate a DMA transfer
  • 243 Interrupt 243 will initiate a DMA transfer
  • 244 Interrupt 244 will initiate a DMA transfer
  • 245 Interrupt 245 will initiate a DMA transfer
  • 246 Interrupt 246 will initiate a DMA transfer
  • 247 Interrupt 247 will initiate a DMA transfer
  • 248 Interrupt 248 will initiate a DMA transfer
  • 249 Interrupt 249 will initiate a DMA transfer
  • 250 Interrupt 250 will initiate a DMA transfer
  • 251 Interrupt 251 will initiate a DMA transfer
  • 252 Interrupt 252 will initiate a DMA transfer
  • 253 Interrupt 253 will initiate a DMA transfer
  • 254 Interrupt 254 will initiate a DMA transfer
  • 255 Interrupt 255 will initiate a DMA transfer
CFORCE7DMA Forced Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT6DMA Abort Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is aborted when this bit is written to a 1
PATEN5Channel Pattern Match Abort Enable bit
  • 0 Pattern match is disabled
  • 1 Abort transfer and clear CHEN on pattern match
SIRQEN4Channel Start IRQ Enable bit
  • 0 Interrupt number CHSIRQ is ignored and does not start a transfer
  • 1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN3Channel Abort IRQ Enable bit
  • 0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
  • 1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs

DCH1INTDMA Channel x Interrupt Control Register

Address
0xBF883140
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CHSDIE23Channel Source Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSHIE22Channel Source Half Empty Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDDIE21Channel Destination Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDHIE20Channel Destination Half Full Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHBCIE19Channel Block Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHCCIE18Channel Cell Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHTAIE17Channel Transfer Abort Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHERIE16Channel Address Error Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSDIF7Channel Source Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF6Channel Source Half Empty Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF5Channel Destination Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF4Channel Destination Half Full Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF3Channel Block Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF2Channel Cell Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF1Channel Transfer Abort Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF0Channel Address Error Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A channel address error has been detected. Either the source or the destination address is invalid.

DCH1SSADMA Channel x Source Start Address Register

Address
0xBF883150
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1DSADMA Channel x Destination Start Address Register

Address
0xBF883160
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1SSIZDMA Channel x Source Size Register

Address
0xBF883170
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1DSIZDMA Channel x Destination Size Register

Address
0xBF883180
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1SPTRDMA Channel x Source Pointer Register

Address
0xBF883190
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1DPTRDMA Channel x Destination Pointer Register

Address
0xBF8831A0
Reset
0x00000000
Access
read only
Size
32-bit

DCH1CSIZDMA Channel x Cell-Size Register

Address
0xBF8831B0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1CPTRDMA Channel x Cell Pointer Register

Address
0xBF8831C0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH1DATDMA Channel x Pattern Data Register

Address
0xBF8831D0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2 DMA channel 2

DCH2CONDMA Channel x Control Register

Address
0xBF8831E0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CHBUSY15Channel Busy bit
  • 0 Channel is inactive or has been disabled
  • 1 Channel is active or has been enabled
CHCHNS8Chain Channel Selection bit
  • 0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
  • 1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN7Channel Enable bit
  • 0 Channel is disabled
  • 1 Channel is enabled
CHAED6Channel Allow Events If Disabled bit
  • 0 Channel start/abort events will be ignored if the channel is disabled
  • 1 Channel start/abort events will be registered even if the channel is disabled
CHCHN5Channel Chain Enable bit
  • 0 Do not allow channel to be chained
  • 1 Allow channel to be chained
CHAEN4Channel Automatic Enable bit
  • 0 Channel is disabled on block transfer complete
  • 1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET2Channel Event Detected bit
  • 0 No events have been detected
  • 1 An event has been detected
CHPRI1:0Channel Priority bits
  • 0 Channel has priority 0
  • 1 Channel has priority 1
  • 2 Channel has priority 2
  • 3 Channel has priority 3 (highest)

DCH2ECONDMA Channel x Event Control Register

Address
0xBF8831F0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
CHAIRQ23:16Channel Transfer Abort IRQ bits
  • 0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
  • 1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
  • 2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
  • 3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
  • 4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
  • 5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
  • 6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
  • 7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
  • 8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
  • 9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
  • 10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
  • 11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
  • 12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
  • 13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
  • 14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
  • 15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
  • 16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
  • 17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
  • 18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
  • 19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
  • 20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
  • 21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
  • 22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
  • 23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
  • 24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
  • 25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
  • 26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
  • 27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
  • 28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
  • 29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
  • 30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
  • 31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
  • 32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
  • 33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
  • 34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
  • 35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
  • 36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
  • 37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
  • 38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
  • 39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
  • 40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
  • 41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
  • 42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
  • 43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
  • 44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
  • 45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
  • 46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
  • 47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
  • 48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
  • 49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
  • 50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
  • 51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
  • 52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
  • 53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
  • 54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
  • 55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
  • 56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
  • 57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
  • 58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
  • 59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
  • 60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
  • 61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
  • 62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
  • 63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
  • 64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
  • 65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
  • 66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
  • 67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
  • 68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
  • 69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
  • 70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
  • 71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
  • 72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
  • 73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
  • 74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
  • 75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
  • 76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
  • 77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
  • 78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
  • 79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
  • 80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
  • 81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
  • 82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
  • 83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
  • 84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
  • 85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
  • 86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
  • 87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
  • 88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
  • 89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
  • 90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
  • 91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
  • 92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
  • 93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
  • 94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
  • 95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
  • 96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
  • 97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
  • 98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
  • 99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
  • 100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
  • 101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
  • 102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
  • 103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
  • 104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
  • 105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
  • 106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
  • 107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
  • 108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
  • 109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
  • 110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
  • 111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
  • 112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
  • 113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
  • 114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
  • 115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
  • 116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
  • 117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
  • 118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
  • 119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
  • 120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
  • 121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
  • 122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
  • 123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
  • 124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
  • 125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
  • 126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
  • 127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
  • 128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
  • 129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
  • 130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
  • 131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
  • 132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
  • 133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
  • 134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
  • 135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
  • 136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
  • 137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
  • 138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
  • 139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
  • 140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
  • 141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
  • 142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
  • 143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
  • 144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
  • 145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
  • 146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
  • 147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
  • 148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
  • 149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
  • 150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
  • 151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
  • 152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
  • 153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
  • 154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
  • 155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
  • 156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
  • 157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
  • 158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
  • 159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
  • 160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
  • 161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
  • 162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
  • 163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
  • 164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
  • 165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
  • 166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
  • 167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
  • 168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
  • 169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
  • 170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
  • 171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
  • 172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
  • 173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
  • 174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
  • 175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
  • 176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
  • 177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
  • 178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
  • 179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
  • 180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
  • 181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
  • 182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
  • 183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
  • 184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
  • 185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
  • 186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
  • 187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
  • 188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
  • 189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
  • 190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
  • 191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
  • 192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
  • 193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
  • 194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
  • 195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
  • 196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
  • 197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
  • 198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
  • 199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
  • 200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
  • 201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
  • 202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
  • 203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
  • 204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
  • 205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
  • 206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
  • 207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
  • 208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
  • 209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
  • 210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
  • 211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
  • 212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
  • 213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
  • 214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
  • 215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
  • 216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
  • 217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
  • 218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
  • 219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
  • 220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
  • 221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
  • 222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
  • 223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
  • 224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
  • 225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
  • 226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
  • 227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
  • 228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
  • 229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
  • 230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
  • 231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
  • 232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
  • 233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
  • 234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
  • 235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
  • 236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
  • 237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
  • 238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
  • 239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
  • 240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
  • 241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
  • 242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
  • 243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
  • 244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
  • 245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
  • 246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
  • 247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
  • 248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
  • 249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
  • 250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
  • 251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
  • 252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
  • 253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
  • 254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
  • 255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ15:8Channel Transfer Start IRQ bits
  • 0 Interrupt 0 will initiate a DMA transfer
  • 1 Interrupt 1 will initiate a DMA transfer
  • 2 Interrupt 2 will initiate a DMA transfer
  • 3 Interrupt 3 will initiate a DMA transfer
  • 4 Interrupt 4 will initiate a DMA transfer
  • 5 Interrupt 5 will initiate a DMA transfer
  • 6 Interrupt 6 will initiate a DMA transfer
  • 7 Interrupt 7 will initiate a DMA transfer
  • 8 Interrupt 8 will initiate a DMA transfer
  • 9 Interrupt 9 will initiate a DMA transfer
  • 10 Interrupt 10 will initiate a DMA transfer
  • 11 Interrupt 11 will initiate a DMA transfer
  • 12 Interrupt 12 will initiate a DMA transfer
  • 13 Interrupt 13 will initiate a DMA transfer
  • 14 Interrupt 14 will initiate a DMA transfer
  • 15 Interrupt 15 will initiate a DMA transfer
  • 16 Interrupt 16 will initiate a DMA transfer
  • 17 Interrupt 17 will initiate a DMA transfer
  • 18 Interrupt 18 will initiate a DMA transfer
  • 19 Interrupt 19 will initiate a DMA transfer
  • 20 Interrupt 20 will initiate a DMA transfer
  • 21 Interrupt 21 will initiate a DMA transfer
  • 22 Interrupt 22 will initiate a DMA transfer
  • 23 Interrupt 23 will initiate a DMA transfer
  • 24 Interrupt 24 will initiate a DMA transfer
  • 25 Interrupt 25 will initiate a DMA transfer
  • 26 Interrupt 26 will initiate a DMA transfer
  • 27 Interrupt 27 will initiate a DMA transfer
  • 28 Interrupt 28 will initiate a DMA transfer
  • 29 Interrupt 29 will initiate a DMA transfer
  • 30 Interrupt 30 will initiate a DMA transfer
  • 31 Interrupt 31 will initiate a DMA transfer
  • 32 Interrupt 32 will initiate a DMA transfer
  • 33 Interrupt 33 will initiate a DMA transfer
  • 34 Interrupt 34 will initiate a DMA transfer
  • 35 Interrupt 35 will initiate a DMA transfer
  • 36 Interrupt 36 will initiate a DMA transfer
  • 37 Interrupt 37 will initiate a DMA transfer
  • 38 Interrupt 38 will initiate a DMA transfer
  • 39 Interrupt 39 will initiate a DMA transfer
  • 40 Interrupt 40 will initiate a DMA transfer
  • 41 Interrupt 41 will initiate a DMA transfer
  • 42 Interrupt 42 will initiate a DMA transfer
  • 43 Interrupt 43 will initiate a DMA transfer
  • 44 Interrupt 44 will initiate a DMA transfer
  • 45 Interrupt 45 will initiate a DMA transfer
  • 46 Interrupt 46 will initiate a DMA transfer
  • 47 Interrupt 47 will initiate a DMA transfer
  • 48 Interrupt 48 will initiate a DMA transfer
  • 49 Interrupt 49 will initiate a DMA transfer
  • 50 Interrupt 50 will initiate a DMA transfer
  • 51 Interrupt 51 will initiate a DMA transfer
  • 52 Interrupt 52 will initiate a DMA transfer
  • 53 Interrupt 53 will initiate a DMA transfer
  • 54 Interrupt 54 will initiate a DMA transfer
  • 55 Interrupt 55 will initiate a DMA transfer
  • 56 Interrupt 56 will initiate a DMA transfer
  • 57 Interrupt 57 will initiate a DMA transfer
  • 58 Interrupt 58 will initiate a DMA transfer
  • 59 Interrupt 59 will initiate a DMA transfer
  • 60 Interrupt 60 will initiate a DMA transfer
  • 61 Interrupt 61 will initiate a DMA transfer
  • 62 Interrupt 62 will initiate a DMA transfer
  • 63 Interrupt 63 will initiate a DMA transfer
  • 64 Interrupt 64 will initiate a DMA transfer
  • 65 Interrupt 65 will initiate a DMA transfer
  • 66 Interrupt 66 will initiate a DMA transfer
  • 67 Interrupt 67 will initiate a DMA transfer
  • 68 Interrupt 68 will initiate a DMA transfer
  • 69 Interrupt 69 will initiate a DMA transfer
  • 70 Interrupt 70 will initiate a DMA transfer
  • 71 Interrupt 71 will initiate a DMA transfer
  • 72 Interrupt 72 will initiate a DMA transfer
  • 73 Interrupt 73 will initiate a DMA transfer
  • 74 Interrupt 74 will initiate a DMA transfer
  • 75 Interrupt 75 will initiate a DMA transfer
  • 76 Interrupt 76 will initiate a DMA transfer
  • 77 Interrupt 77 will initiate a DMA transfer
  • 78 Interrupt 78 will initiate a DMA transfer
  • 79 Interrupt 79 will initiate a DMA transfer
  • 80 Interrupt 80 will initiate a DMA transfer
  • 81 Interrupt 81 will initiate a DMA transfer
  • 82 Interrupt 82 will initiate a DMA transfer
  • 83 Interrupt 83 will initiate a DMA transfer
  • 84 Interrupt 84 will initiate a DMA transfer
  • 85 Interrupt 85 will initiate a DMA transfer
  • 86 Interrupt 86 will initiate a DMA transfer
  • 87 Interrupt 87 will initiate a DMA transfer
  • 88 Interrupt 88 will initiate a DMA transfer
  • 89 Interrupt 89 will initiate a DMA transfer
  • 90 Interrupt 90 will initiate a DMA transfer
  • 91 Interrupt 91 will initiate a DMA transfer
  • 92 Interrupt 92 will initiate a DMA transfer
  • 93 Interrupt 93 will initiate a DMA transfer
  • 94 Interrupt 94 will initiate a DMA transfer
  • 95 Interrupt 95 will initiate a DMA transfer
  • 96 Interrupt 96 will initiate a DMA transfer
  • 97 Interrupt 97 will initiate a DMA transfer
  • 98 Interrupt 98 will initiate a DMA transfer
  • 99 Interrupt 99 will initiate a DMA transfer
  • 100 Interrupt 100 will initiate a DMA transfer
  • 101 Interrupt 101 will initiate a DMA transfer
  • 102 Interrupt 102 will initiate a DMA transfer
  • 103 Interrupt 103 will initiate a DMA transfer
  • 104 Interrupt 104 will initiate a DMA transfer
  • 105 Interrupt 105 will initiate a DMA transfer
  • 106 Interrupt 106 will initiate a DMA transfer
  • 107 Interrupt 107 will initiate a DMA transfer
  • 108 Interrupt 108 will initiate a DMA transfer
  • 109 Interrupt 109 will initiate a DMA transfer
  • 110 Interrupt 110 will initiate a DMA transfer
  • 111 Interrupt 111 will initiate a DMA transfer
  • 112 Interrupt 112 will initiate a DMA transfer
  • 113 Interrupt 113 will initiate a DMA transfer
  • 114 Interrupt 114 will initiate a DMA transfer
  • 115 Interrupt 115 will initiate a DMA transfer
  • 116 Interrupt 116 will initiate a DMA transfer
  • 117 Interrupt 117 will initiate a DMA transfer
  • 118 Interrupt 118 will initiate a DMA transfer
  • 119 Interrupt 119 will initiate a DMA transfer
  • 120 Interrupt 120 will initiate a DMA transfer
  • 121 Interrupt 121 will initiate a DMA transfer
  • 122 Interrupt 122 will initiate a DMA transfer
  • 123 Interrupt 123 will initiate a DMA transfer
  • 124 Interrupt 124 will initiate a DMA transfer
  • 125 Interrupt 125 will initiate a DMA transfer
  • 126 Interrupt 126 will initiate a DMA transfer
  • 127 Interrupt 127 will initiate a DMA transfer
  • 128 Interrupt 128 will initiate a DMA transfer
  • 129 Interrupt 129 will initiate a DMA transfer
  • 130 Interrupt 130 will initiate a DMA transfer
  • 131 Interrupt 131 will initiate a DMA transfer
  • 132 Interrupt 132 will initiate a DMA transfer
  • 133 Interrupt 133 will initiate a DMA transfer
  • 134 Interrupt 134 will initiate a DMA transfer
  • 135 Interrupt 135 will initiate a DMA transfer
  • 136 Interrupt 136 will initiate a DMA transfer
  • 137 Interrupt 137 will initiate a DMA transfer
  • 138 Interrupt 138 will initiate a DMA transfer
  • 139 Interrupt 139 will initiate a DMA transfer
  • 140 Interrupt 140 will initiate a DMA transfer
  • 141 Interrupt 141 will initiate a DMA transfer
  • 142 Interrupt 142 will initiate a DMA transfer
  • 143 Interrupt 143 will initiate a DMA transfer
  • 144 Interrupt 144 will initiate a DMA transfer
  • 145 Interrupt 145 will initiate a DMA transfer
  • 146 Interrupt 146 will initiate a DMA transfer
  • 147 Interrupt 147 will initiate a DMA transfer
  • 148 Interrupt 148 will initiate a DMA transfer
  • 149 Interrupt 149 will initiate a DMA transfer
  • 150 Interrupt 150 will initiate a DMA transfer
  • 151 Interrupt 151 will initiate a DMA transfer
  • 152 Interrupt 152 will initiate a DMA transfer
  • 153 Interrupt 153 will initiate a DMA transfer
  • 154 Interrupt 154 will initiate a DMA transfer
  • 155 Interrupt 155 will initiate a DMA transfer
  • 156 Interrupt 156 will initiate a DMA transfer
  • 157 Interrupt 157 will initiate a DMA transfer
  • 158 Interrupt 158 will initiate a DMA transfer
  • 159 Interrupt 159 will initiate a DMA transfer
  • 160 Interrupt 160 will initiate a DMA transfer
  • 161 Interrupt 161 will initiate a DMA transfer
  • 162 Interrupt 162 will initiate a DMA transfer
  • 163 Interrupt 163 will initiate a DMA transfer
  • 164 Interrupt 164 will initiate a DMA transfer
  • 165 Interrupt 165 will initiate a DMA transfer
  • 166 Interrupt 166 will initiate a DMA transfer
  • 167 Interrupt 167 will initiate a DMA transfer
  • 168 Interrupt 168 will initiate a DMA transfer
  • 169 Interrupt 169 will initiate a DMA transfer
  • 170 Interrupt 170 will initiate a DMA transfer
  • 171 Interrupt 171 will initiate a DMA transfer
  • 172 Interrupt 172 will initiate a DMA transfer
  • 173 Interrupt 173 will initiate a DMA transfer
  • 174 Interrupt 174 will initiate a DMA transfer
  • 175 Interrupt 175 will initiate a DMA transfer
  • 176 Interrupt 176 will initiate a DMA transfer
  • 177 Interrupt 177 will initiate a DMA transfer
  • 178 Interrupt 178 will initiate a DMA transfer
  • 179 Interrupt 179 will initiate a DMA transfer
  • 180 Interrupt 180 will initiate a DMA transfer
  • 181 Interrupt 181 will initiate a DMA transfer
  • 182 Interrupt 182 will initiate a DMA transfer
  • 183 Interrupt 183 will initiate a DMA transfer
  • 184 Interrupt 184 will initiate a DMA transfer
  • 185 Interrupt 185 will initiate a DMA transfer
  • 186 Interrupt 186 will initiate a DMA transfer
  • 187 Interrupt 187 will initiate a DMA transfer
  • 188 Interrupt 188 will initiate a DMA transfer
  • 189 Interrupt 189 will initiate a DMA transfer
  • 190 Interrupt 190 will initiate a DMA transfer
  • 191 Interrupt 191 will initiate a DMA transfer
  • 192 Interrupt 192 will initiate a DMA transfer
  • 193 Interrupt 193 will initiate a DMA transfer
  • 194 Interrupt 194 will initiate a DMA transfer
  • 195 Interrupt 195 will initiate a DMA transfer
  • 196 Interrupt 196 will initiate a DMA transfer
  • 197 Interrupt 197 will initiate a DMA transfer
  • 198 Interrupt 198 will initiate a DMA transfer
  • 199 Interrupt 199 will initiate a DMA transfer
  • 200 Interrupt 200 will initiate a DMA transfer
  • 201 Interrupt 201 will initiate a DMA transfer
  • 202 Interrupt 202 will initiate a DMA transfer
  • 203 Interrupt 203 will initiate a DMA transfer
  • 204 Interrupt 204 will initiate a DMA transfer
  • 205 Interrupt 205 will initiate a DMA transfer
  • 206 Interrupt 206 will initiate a DMA transfer
  • 207 Interrupt 207 will initiate a DMA transfer
  • 208 Interrupt 208 will initiate a DMA transfer
  • 209 Interrupt 209 will initiate a DMA transfer
  • 210 Interrupt 210 will initiate a DMA transfer
  • 211 Interrupt 211 will initiate a DMA transfer
  • 212 Interrupt 212 will initiate a DMA transfer
  • 213 Interrupt 213 will initiate a DMA transfer
  • 214 Interrupt 214 will initiate a DMA transfer
  • 215 Interrupt 215 will initiate a DMA transfer
  • 216 Interrupt 216 will initiate a DMA transfer
  • 217 Interrupt 217 will initiate a DMA transfer
  • 218 Interrupt 218 will initiate a DMA transfer
  • 219 Interrupt 219 will initiate a DMA transfer
  • 220 Interrupt 220 will initiate a DMA transfer
  • 221 Interrupt 221 will initiate a DMA transfer
  • 222 Interrupt 222 will initiate a DMA transfer
  • 223 Interrupt 223 will initiate a DMA transfer
  • 224 Interrupt 224 will initiate a DMA transfer
  • 225 Interrupt 225 will initiate a DMA transfer
  • 226 Interrupt 226 will initiate a DMA transfer
  • 227 Interrupt 227 will initiate a DMA transfer
  • 228 Interrupt 228 will initiate a DMA transfer
  • 229 Interrupt 229 will initiate a DMA transfer
  • 230 Interrupt 230 will initiate a DMA transfer
  • 231 Interrupt 231 will initiate a DMA transfer
  • 232 Interrupt 232 will initiate a DMA transfer
  • 233 Interrupt 233 will initiate a DMA transfer
  • 234 Interrupt 234 will initiate a DMA transfer
  • 235 Interrupt 235 will initiate a DMA transfer
  • 236 Interrupt 236 will initiate a DMA transfer
  • 237 Interrupt 237 will initiate a DMA transfer
  • 238 Interrupt 238 will initiate a DMA transfer
  • 239 Interrupt 239 will initiate a DMA transfer
  • 240 Interrupt 240 will initiate a DMA transfer
  • 241 Interrupt 241 will initiate a DMA transfer
  • 242 Interrupt 242 will initiate a DMA transfer
  • 243 Interrupt 243 will initiate a DMA transfer
  • 244 Interrupt 244 will initiate a DMA transfer
  • 245 Interrupt 245 will initiate a DMA transfer
  • 246 Interrupt 246 will initiate a DMA transfer
  • 247 Interrupt 247 will initiate a DMA transfer
  • 248 Interrupt 248 will initiate a DMA transfer
  • 249 Interrupt 249 will initiate a DMA transfer
  • 250 Interrupt 250 will initiate a DMA transfer
  • 251 Interrupt 251 will initiate a DMA transfer
  • 252 Interrupt 252 will initiate a DMA transfer
  • 253 Interrupt 253 will initiate a DMA transfer
  • 254 Interrupt 254 will initiate a DMA transfer
  • 255 Interrupt 255 will initiate a DMA transfer
CFORCE7DMA Forced Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT6DMA Abort Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is aborted when this bit is written to a 1
PATEN5Channel Pattern Match Abort Enable bit
  • 0 Pattern match is disabled
  • 1 Abort transfer and clear CHEN on pattern match
SIRQEN4Channel Start IRQ Enable bit
  • 0 Interrupt number CHSIRQ is ignored and does not start a transfer
  • 1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN3Channel Abort IRQ Enable bit
  • 0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
  • 1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs

DCH2INTDMA Channel x Interrupt Control Register

Address
0xBF883200
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CHSDIE23Channel Source Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSHIE22Channel Source Half Empty Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDDIE21Channel Destination Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDHIE20Channel Destination Half Full Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHBCIE19Channel Block Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHCCIE18Channel Cell Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHTAIE17Channel Transfer Abort Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHERIE16Channel Address Error Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSDIF7Channel Source Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF6Channel Source Half Empty Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF5Channel Destination Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF4Channel Destination Half Full Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF3Channel Block Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF2Channel Cell Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF1Channel Transfer Abort Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF0Channel Address Error Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A channel address error has been detected. Either the source or the destination address is invalid.

DCH2SSADMA Channel x Source Start Address Register

Address
0xBF883210
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2DSADMA Channel x Destination Start Address Register

Address
0xBF883220
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2SSIZDMA Channel x Source Size Register

Address
0xBF883230
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2DSIZDMA Channel x Destination Size Register

Address
0xBF883240
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2SPTRDMA Channel x Source Pointer Register

Address
0xBF883250
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2DPTRDMA Channel x Destination Pointer Register

Address
0xBF883260
Reset
0x00000000
Access
read only
Size
32-bit

DCH2CSIZDMA Channel x Cell-Size Register

Address
0xBF883270
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2CPTRDMA Channel x Cell Pointer Register

Address
0xBF883280
Reset
0x00000000
Access
read/write
Size
32-bit

DCH2DATDMA Channel x Pattern Data Register

Address
0xBF883290
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3 DMA channel 3

DCH3CONDMA Channel x Control Register

Address
0xBF8832A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
CHBUSY15Channel Busy bit
  • 0 Channel is inactive or has been disabled
  • 1 Channel is active or has been enabled
CHCHNS8Chain Channel Selection bit
  • 0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
  • 1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN7Channel Enable bit
  • 0 Channel is disabled
  • 1 Channel is enabled
CHAED6Channel Allow Events If Disabled bit
  • 0 Channel start/abort events will be ignored if the channel is disabled
  • 1 Channel start/abort events will be registered even if the channel is disabled
CHCHN5Channel Chain Enable bit
  • 0 Do not allow channel to be chained
  • 1 Allow channel to be chained
CHAEN4Channel Automatic Enable bit
  • 0 Channel is disabled on block transfer complete
  • 1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET2Channel Event Detected bit
  • 0 No events have been detected
  • 1 An event has been detected
CHPRI1:0Channel Priority bits
  • 0 Channel has priority 0
  • 1 Channel has priority 1
  • 2 Channel has priority 2
  • 3 Channel has priority 3 (highest)

DCH3ECONDMA Channel x Event Control Register

Address
0xBF8832B0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
CHAIRQ23:16Channel Transfer Abort IRQ bits
  • 0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
  • 1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
  • 2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
  • 3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
  • 4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
  • 5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
  • 6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
  • 7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
  • 8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
  • 9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
  • 10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
  • 11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
  • 12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
  • 13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
  • 14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
  • 15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
  • 16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
  • 17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
  • 18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
  • 19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
  • 20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
  • 21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
  • 22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
  • 23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
  • 24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
  • 25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
  • 26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
  • 27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
  • 28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
  • 29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
  • 30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
  • 31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
  • 32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
  • 33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
  • 34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
  • 35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
  • 36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
  • 37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
  • 38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
  • 39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
  • 40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
  • 41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
  • 42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
  • 43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
  • 44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
  • 45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
  • 46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
  • 47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
  • 48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
  • 49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
  • 50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
  • 51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
  • 52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
  • 53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
  • 54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
  • 55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
  • 56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
  • 57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
  • 58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
  • 59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
  • 60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
  • 61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
  • 62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
  • 63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
  • 64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
  • 65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
  • 66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
  • 67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
  • 68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
  • 69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
  • 70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
  • 71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
  • 72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
  • 73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
  • 74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
  • 75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
  • 76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
  • 77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
  • 78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
  • 79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
  • 80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
  • 81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
  • 82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
  • 83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
  • 84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
  • 85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
  • 86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
  • 87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
  • 88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
  • 89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
  • 90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
  • 91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
  • 92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
  • 93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
  • 94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
  • 95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
  • 96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
  • 97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
  • 98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
  • 99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
  • 100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
  • 101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
  • 102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
  • 103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
  • 104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
  • 105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
  • 106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
  • 107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
  • 108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
  • 109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
  • 110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
  • 111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
  • 112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
  • 113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
  • 114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
  • 115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
  • 116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
  • 117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
  • 118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
  • 119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
  • 120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
  • 121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
  • 122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
  • 123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
  • 124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
  • 125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
  • 126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
  • 127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
  • 128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
  • 129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
  • 130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
  • 131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
  • 132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
  • 133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
  • 134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
  • 135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
  • 136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
  • 137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
  • 138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
  • 139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
  • 140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
  • 141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
  • 142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
  • 143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
  • 144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
  • 145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
  • 146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
  • 147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
  • 148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
  • 149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
  • 150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
  • 151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
  • 152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
  • 153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
  • 154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
  • 155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
  • 156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
  • 157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
  • 158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
  • 159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
  • 160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
  • 161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
  • 162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
  • 163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
  • 164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
  • 165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
  • 166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
  • 167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
  • 168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
  • 169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
  • 170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
  • 171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
  • 172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
  • 173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
  • 174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
  • 175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
  • 176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
  • 177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
  • 178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
  • 179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
  • 180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
  • 181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
  • 182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
  • 183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
  • 184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
  • 185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
  • 186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
  • 187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
  • 188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
  • 189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
  • 190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
  • 191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
  • 192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
  • 193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
  • 194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
  • 195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
  • 196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
  • 197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
  • 198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
  • 199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
  • 200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
  • 201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
  • 202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
  • 203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
  • 204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
  • 205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
  • 206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
  • 207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
  • 208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
  • 209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
  • 210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
  • 211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
  • 212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
  • 213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
  • 214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
  • 215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
  • 216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
  • 217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
  • 218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
  • 219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
  • 220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
  • 221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
  • 222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
  • 223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
  • 224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
  • 225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
  • 226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
  • 227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
  • 228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
  • 229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
  • 230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
  • 231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
  • 232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
  • 233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
  • 234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
  • 235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
  • 236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
  • 237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
  • 238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
  • 239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
  • 240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
  • 241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
  • 242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
  • 243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
  • 244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
  • 245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
  • 246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
  • 247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
  • 248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
  • 249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
  • 250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
  • 251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
  • 252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
  • 253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
  • 254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
  • 255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ15:8Channel Transfer Start IRQ bits
  • 0 Interrupt 0 will initiate a DMA transfer
  • 1 Interrupt 1 will initiate a DMA transfer
  • 2 Interrupt 2 will initiate a DMA transfer
  • 3 Interrupt 3 will initiate a DMA transfer
  • 4 Interrupt 4 will initiate a DMA transfer
  • 5 Interrupt 5 will initiate a DMA transfer
  • 6 Interrupt 6 will initiate a DMA transfer
  • 7 Interrupt 7 will initiate a DMA transfer
  • 8 Interrupt 8 will initiate a DMA transfer
  • 9 Interrupt 9 will initiate a DMA transfer
  • 10 Interrupt 10 will initiate a DMA transfer
  • 11 Interrupt 11 will initiate a DMA transfer
  • 12 Interrupt 12 will initiate a DMA transfer
  • 13 Interrupt 13 will initiate a DMA transfer
  • 14 Interrupt 14 will initiate a DMA transfer
  • 15 Interrupt 15 will initiate a DMA transfer
  • 16 Interrupt 16 will initiate a DMA transfer
  • 17 Interrupt 17 will initiate a DMA transfer
  • 18 Interrupt 18 will initiate a DMA transfer
  • 19 Interrupt 19 will initiate a DMA transfer
  • 20 Interrupt 20 will initiate a DMA transfer
  • 21 Interrupt 21 will initiate a DMA transfer
  • 22 Interrupt 22 will initiate a DMA transfer
  • 23 Interrupt 23 will initiate a DMA transfer
  • 24 Interrupt 24 will initiate a DMA transfer
  • 25 Interrupt 25 will initiate a DMA transfer
  • 26 Interrupt 26 will initiate a DMA transfer
  • 27 Interrupt 27 will initiate a DMA transfer
  • 28 Interrupt 28 will initiate a DMA transfer
  • 29 Interrupt 29 will initiate a DMA transfer
  • 30 Interrupt 30 will initiate a DMA transfer
  • 31 Interrupt 31 will initiate a DMA transfer
  • 32 Interrupt 32 will initiate a DMA transfer
  • 33 Interrupt 33 will initiate a DMA transfer
  • 34 Interrupt 34 will initiate a DMA transfer
  • 35 Interrupt 35 will initiate a DMA transfer
  • 36 Interrupt 36 will initiate a DMA transfer
  • 37 Interrupt 37 will initiate a DMA transfer
  • 38 Interrupt 38 will initiate a DMA transfer
  • 39 Interrupt 39 will initiate a DMA transfer
  • 40 Interrupt 40 will initiate a DMA transfer
  • 41 Interrupt 41 will initiate a DMA transfer
  • 42 Interrupt 42 will initiate a DMA transfer
  • 43 Interrupt 43 will initiate a DMA transfer
  • 44 Interrupt 44 will initiate a DMA transfer
  • 45 Interrupt 45 will initiate a DMA transfer
  • 46 Interrupt 46 will initiate a DMA transfer
  • 47 Interrupt 47 will initiate a DMA transfer
  • 48 Interrupt 48 will initiate a DMA transfer
  • 49 Interrupt 49 will initiate a DMA transfer
  • 50 Interrupt 50 will initiate a DMA transfer
  • 51 Interrupt 51 will initiate a DMA transfer
  • 52 Interrupt 52 will initiate a DMA transfer
  • 53 Interrupt 53 will initiate a DMA transfer
  • 54 Interrupt 54 will initiate a DMA transfer
  • 55 Interrupt 55 will initiate a DMA transfer
  • 56 Interrupt 56 will initiate a DMA transfer
  • 57 Interrupt 57 will initiate a DMA transfer
  • 58 Interrupt 58 will initiate a DMA transfer
  • 59 Interrupt 59 will initiate a DMA transfer
  • 60 Interrupt 60 will initiate a DMA transfer
  • 61 Interrupt 61 will initiate a DMA transfer
  • 62 Interrupt 62 will initiate a DMA transfer
  • 63 Interrupt 63 will initiate a DMA transfer
  • 64 Interrupt 64 will initiate a DMA transfer
  • 65 Interrupt 65 will initiate a DMA transfer
  • 66 Interrupt 66 will initiate a DMA transfer
  • 67 Interrupt 67 will initiate a DMA transfer
  • 68 Interrupt 68 will initiate a DMA transfer
  • 69 Interrupt 69 will initiate a DMA transfer
  • 70 Interrupt 70 will initiate a DMA transfer
  • 71 Interrupt 71 will initiate a DMA transfer
  • 72 Interrupt 72 will initiate a DMA transfer
  • 73 Interrupt 73 will initiate a DMA transfer
  • 74 Interrupt 74 will initiate a DMA transfer
  • 75 Interrupt 75 will initiate a DMA transfer
  • 76 Interrupt 76 will initiate a DMA transfer
  • 77 Interrupt 77 will initiate a DMA transfer
  • 78 Interrupt 78 will initiate a DMA transfer
  • 79 Interrupt 79 will initiate a DMA transfer
  • 80 Interrupt 80 will initiate a DMA transfer
  • 81 Interrupt 81 will initiate a DMA transfer
  • 82 Interrupt 82 will initiate a DMA transfer
  • 83 Interrupt 83 will initiate a DMA transfer
  • 84 Interrupt 84 will initiate a DMA transfer
  • 85 Interrupt 85 will initiate a DMA transfer
  • 86 Interrupt 86 will initiate a DMA transfer
  • 87 Interrupt 87 will initiate a DMA transfer
  • 88 Interrupt 88 will initiate a DMA transfer
  • 89 Interrupt 89 will initiate a DMA transfer
  • 90 Interrupt 90 will initiate a DMA transfer
  • 91 Interrupt 91 will initiate a DMA transfer
  • 92 Interrupt 92 will initiate a DMA transfer
  • 93 Interrupt 93 will initiate a DMA transfer
  • 94 Interrupt 94 will initiate a DMA transfer
  • 95 Interrupt 95 will initiate a DMA transfer
  • 96 Interrupt 96 will initiate a DMA transfer
  • 97 Interrupt 97 will initiate a DMA transfer
  • 98 Interrupt 98 will initiate a DMA transfer
  • 99 Interrupt 99 will initiate a DMA transfer
  • 100 Interrupt 100 will initiate a DMA transfer
  • 101 Interrupt 101 will initiate a DMA transfer
  • 102 Interrupt 102 will initiate a DMA transfer
  • 103 Interrupt 103 will initiate a DMA transfer
  • 104 Interrupt 104 will initiate a DMA transfer
  • 105 Interrupt 105 will initiate a DMA transfer
  • 106 Interrupt 106 will initiate a DMA transfer
  • 107 Interrupt 107 will initiate a DMA transfer
  • 108 Interrupt 108 will initiate a DMA transfer
  • 109 Interrupt 109 will initiate a DMA transfer
  • 110 Interrupt 110 will initiate a DMA transfer
  • 111 Interrupt 111 will initiate a DMA transfer
  • 112 Interrupt 112 will initiate a DMA transfer
  • 113 Interrupt 113 will initiate a DMA transfer
  • 114 Interrupt 114 will initiate a DMA transfer
  • 115 Interrupt 115 will initiate a DMA transfer
  • 116 Interrupt 116 will initiate a DMA transfer
  • 117 Interrupt 117 will initiate a DMA transfer
  • 118 Interrupt 118 will initiate a DMA transfer
  • 119 Interrupt 119 will initiate a DMA transfer
  • 120 Interrupt 120 will initiate a DMA transfer
  • 121 Interrupt 121 will initiate a DMA transfer
  • 122 Interrupt 122 will initiate a DMA transfer
  • 123 Interrupt 123 will initiate a DMA transfer
  • 124 Interrupt 124 will initiate a DMA transfer
  • 125 Interrupt 125 will initiate a DMA transfer
  • 126 Interrupt 126 will initiate a DMA transfer
  • 127 Interrupt 127 will initiate a DMA transfer
  • 128 Interrupt 128 will initiate a DMA transfer
  • 129 Interrupt 129 will initiate a DMA transfer
  • 130 Interrupt 130 will initiate a DMA transfer
  • 131 Interrupt 131 will initiate a DMA transfer
  • 132 Interrupt 132 will initiate a DMA transfer
  • 133 Interrupt 133 will initiate a DMA transfer
  • 134 Interrupt 134 will initiate a DMA transfer
  • 135 Interrupt 135 will initiate a DMA transfer
  • 136 Interrupt 136 will initiate a DMA transfer
  • 137 Interrupt 137 will initiate a DMA transfer
  • 138 Interrupt 138 will initiate a DMA transfer
  • 139 Interrupt 139 will initiate a DMA transfer
  • 140 Interrupt 140 will initiate a DMA transfer
  • 141 Interrupt 141 will initiate a DMA transfer
  • 142 Interrupt 142 will initiate a DMA transfer
  • 143 Interrupt 143 will initiate a DMA transfer
  • 144 Interrupt 144 will initiate a DMA transfer
  • 145 Interrupt 145 will initiate a DMA transfer
  • 146 Interrupt 146 will initiate a DMA transfer
  • 147 Interrupt 147 will initiate a DMA transfer
  • 148 Interrupt 148 will initiate a DMA transfer
  • 149 Interrupt 149 will initiate a DMA transfer
  • 150 Interrupt 150 will initiate a DMA transfer
  • 151 Interrupt 151 will initiate a DMA transfer
  • 152 Interrupt 152 will initiate a DMA transfer
  • 153 Interrupt 153 will initiate a DMA transfer
  • 154 Interrupt 154 will initiate a DMA transfer
  • 155 Interrupt 155 will initiate a DMA transfer
  • 156 Interrupt 156 will initiate a DMA transfer
  • 157 Interrupt 157 will initiate a DMA transfer
  • 158 Interrupt 158 will initiate a DMA transfer
  • 159 Interrupt 159 will initiate a DMA transfer
  • 160 Interrupt 160 will initiate a DMA transfer
  • 161 Interrupt 161 will initiate a DMA transfer
  • 162 Interrupt 162 will initiate a DMA transfer
  • 163 Interrupt 163 will initiate a DMA transfer
  • 164 Interrupt 164 will initiate a DMA transfer
  • 165 Interrupt 165 will initiate a DMA transfer
  • 166 Interrupt 166 will initiate a DMA transfer
  • 167 Interrupt 167 will initiate a DMA transfer
  • 168 Interrupt 168 will initiate a DMA transfer
  • 169 Interrupt 169 will initiate a DMA transfer
  • 170 Interrupt 170 will initiate a DMA transfer
  • 171 Interrupt 171 will initiate a DMA transfer
  • 172 Interrupt 172 will initiate a DMA transfer
  • 173 Interrupt 173 will initiate a DMA transfer
  • 174 Interrupt 174 will initiate a DMA transfer
  • 175 Interrupt 175 will initiate a DMA transfer
  • 176 Interrupt 176 will initiate a DMA transfer
  • 177 Interrupt 177 will initiate a DMA transfer
  • 178 Interrupt 178 will initiate a DMA transfer
  • 179 Interrupt 179 will initiate a DMA transfer
  • 180 Interrupt 180 will initiate a DMA transfer
  • 181 Interrupt 181 will initiate a DMA transfer
  • 182 Interrupt 182 will initiate a DMA transfer
  • 183 Interrupt 183 will initiate a DMA transfer
  • 184 Interrupt 184 will initiate a DMA transfer
  • 185 Interrupt 185 will initiate a DMA transfer
  • 186 Interrupt 186 will initiate a DMA transfer
  • 187 Interrupt 187 will initiate a DMA transfer
  • 188 Interrupt 188 will initiate a DMA transfer
  • 189 Interrupt 189 will initiate a DMA transfer
  • 190 Interrupt 190 will initiate a DMA transfer
  • 191 Interrupt 191 will initiate a DMA transfer
  • 192 Interrupt 192 will initiate a DMA transfer
  • 193 Interrupt 193 will initiate a DMA transfer
  • 194 Interrupt 194 will initiate a DMA transfer
  • 195 Interrupt 195 will initiate a DMA transfer
  • 196 Interrupt 196 will initiate a DMA transfer
  • 197 Interrupt 197 will initiate a DMA transfer
  • 198 Interrupt 198 will initiate a DMA transfer
  • 199 Interrupt 199 will initiate a DMA transfer
  • 200 Interrupt 200 will initiate a DMA transfer
  • 201 Interrupt 201 will initiate a DMA transfer
  • 202 Interrupt 202 will initiate a DMA transfer
  • 203 Interrupt 203 will initiate a DMA transfer
  • 204 Interrupt 204 will initiate a DMA transfer
  • 205 Interrupt 205 will initiate a DMA transfer
  • 206 Interrupt 206 will initiate a DMA transfer
  • 207 Interrupt 207 will initiate a DMA transfer
  • 208 Interrupt 208 will initiate a DMA transfer
  • 209 Interrupt 209 will initiate a DMA transfer
  • 210 Interrupt 210 will initiate a DMA transfer
  • 211 Interrupt 211 will initiate a DMA transfer
  • 212 Interrupt 212 will initiate a DMA transfer
  • 213 Interrupt 213 will initiate a DMA transfer
  • 214 Interrupt 214 will initiate a DMA transfer
  • 215 Interrupt 215 will initiate a DMA transfer
  • 216 Interrupt 216 will initiate a DMA transfer
  • 217 Interrupt 217 will initiate a DMA transfer
  • 218 Interrupt 218 will initiate a DMA transfer
  • 219 Interrupt 219 will initiate a DMA transfer
  • 220 Interrupt 220 will initiate a DMA transfer
  • 221 Interrupt 221 will initiate a DMA transfer
  • 222 Interrupt 222 will initiate a DMA transfer
  • 223 Interrupt 223 will initiate a DMA transfer
  • 224 Interrupt 224 will initiate a DMA transfer
  • 225 Interrupt 225 will initiate a DMA transfer
  • 226 Interrupt 226 will initiate a DMA transfer
  • 227 Interrupt 227 will initiate a DMA transfer
  • 228 Interrupt 228 will initiate a DMA transfer
  • 229 Interrupt 229 will initiate a DMA transfer
  • 230 Interrupt 230 will initiate a DMA transfer
  • 231 Interrupt 231 will initiate a DMA transfer
  • 232 Interrupt 232 will initiate a DMA transfer
  • 233 Interrupt 233 will initiate a DMA transfer
  • 234 Interrupt 234 will initiate a DMA transfer
  • 235 Interrupt 235 will initiate a DMA transfer
  • 236 Interrupt 236 will initiate a DMA transfer
  • 237 Interrupt 237 will initiate a DMA transfer
  • 238 Interrupt 238 will initiate a DMA transfer
  • 239 Interrupt 239 will initiate a DMA transfer
  • 240 Interrupt 240 will initiate a DMA transfer
  • 241 Interrupt 241 will initiate a DMA transfer
  • 242 Interrupt 242 will initiate a DMA transfer
  • 243 Interrupt 243 will initiate a DMA transfer
  • 244 Interrupt 244 will initiate a DMA transfer
  • 245 Interrupt 245 will initiate a DMA transfer
  • 246 Interrupt 246 will initiate a DMA transfer
  • 247 Interrupt 247 will initiate a DMA transfer
  • 248 Interrupt 248 will initiate a DMA transfer
  • 249 Interrupt 249 will initiate a DMA transfer
  • 250 Interrupt 250 will initiate a DMA transfer
  • 251 Interrupt 251 will initiate a DMA transfer
  • 252 Interrupt 252 will initiate a DMA transfer
  • 253 Interrupt 253 will initiate a DMA transfer
  • 254 Interrupt 254 will initiate a DMA transfer
  • 255 Interrupt 255 will initiate a DMA transfer
CFORCE7DMA Forced Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT6DMA Abort Transfer bit
  • 0 This bit always reads 0
  • 1 A DMA transfer is aborted when this bit is written to a 1
PATEN5Channel Pattern Match Abort Enable bit
  • 0 Pattern match is disabled
  • 1 Abort transfer and clear CHEN on pattern match
SIRQEN4Channel Start IRQ Enable bit
  • 0 Interrupt number CHSIRQ is ignored and does not start a transfer
  • 1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN3Channel Abort IRQ Enable bit
  • 0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
  • 1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs

DCH3INTDMA Channel x Interrupt Control Register

Address
0xBF8832C0
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CHSDIE23Channel Source Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSHIE22Channel Source Half Empty Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDDIE21Channel Destination Done Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHDHIE20Channel Destination Half Full Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHBCIE19Channel Block Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHCCIE18Channel Cell Transfer Complete Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHTAIE17Channel Transfer Abort Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHERIE16Channel Address Error Interrupt Enable bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
CHSDIF7Channel Source Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF6Channel Source Half Empty Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF5Channel Destination Done Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF4Channel Destination Half Full Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF3Channel Block Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF2Channel Cell Transfer Complete Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF1Channel Transfer Abort Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF0Channel Address Error Interrupt Flag bit
  • 0 No interrupt is pending
  • 1 A channel address error has been detected. Either the source or the destination address is invalid.

DCH3SSADMA Channel x Source Start Address Register

Address
0xBF8832D0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3DSADMA Channel x Destination Start Address Register

Address
0xBF8832E0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3SSIZDMA Channel x Source Size Register

Address
0xBF8832F0
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3DSIZDMA Channel x Destination Size Register

Address
0xBF883300
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3SPTRDMA Channel x Source Pointer Register

Address
0xBF883310
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3DPTRDMA Channel x Destination Pointer Register

Address
0xBF883320
Reset
0x00000000
Access
read only
Size
32-bit

DCH3CSIZDMA Channel x Cell-Size Register

Address
0xBF883330
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3CPTRDMA Channel x Cell Pointer Register

Address
0xBF883340
Reset
0x00000000
Access
read/write
Size
32-bit

DCH3DATDMA Channel x Pattern Data Register

Address
0xBF883350
Reset
0x00000000
Access
read/write
Size
32-bit

USB1 USB

U1OTGIRUSB OTG Interrupt Status Register

Address
0xBF885040
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
IDIF7ID State Change Indicator bit
  • 0 No change in ID state is detected
  • 1 Change in ID state is detected
T1MSECIF61 Millisecond Timer bit
  • 0 1 millisecond timer has not expired
  • 1 1 millisecond timer has expired
LSTATEIF5Line State Stable Indicator bit
  • 0 USB line state has not been stable for 1 millisecond
  • 1 USB line state has been stable for 1millisecond
ACTVIF4Bus Activity Indicator bit
  • 0 Activity has not been detected
  • 1 Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
SESVDIF3Session Valid Change Indicator bit
  • 0 Vbus voltage has not dropped below the session end level
  • 1 VBUS voltage has dropped below the session end level
SESENDIF2B-Device Vbus Change Indicator bit
  • 0 No change on the session end input was detected
  • 1 A change on the session end input was detected
VBUSVDIF0A-Device Vbus Change Indicator bit
  • 0 No change on the session valid input is detected
  • 1 Change on the session valid input is detected

U1OTGIEUSB OTG Interrupt Enable Register

Address
0xBF885050
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
IDIE7ID Interrupt Enable bit
  • 0 ID interrupt is disabled
  • 1 ID interrupt is enabled
T1MSECIE61 Millisecond Timer Interrupt Enable bit
  • 0 1 millisecond timer interrupt is disabled
  • 1 1 millisecond timer interrupt is enabled
LSTATEIE5Line State Interrupt Enable bit
  • 0 Line state interrupt is disabled
  • 1 Line state interrupt is enabled
ACTVIE4Bus Activity Interrupt Enable bit
  • 0 ACTIVITY interrupt is disabled
  • 1 ACTIVITY interrupt is enabled
SESVDIE3Session Valid Interrupt Enable bit
  • 0 Session valid interrupt is disabled
  • 1 Session valid interrupt is enabled
SESENDIE2B-Session End Interrupt Enable bit
  • 0 B-session end interrupt is disabled
  • 1 B-session end interrupt is enabled
VBUSVDIE0A- Vbus Valid Interrupt Enable bit
  • 0 A-VBUS valid interrupt is disabled
  • 1 A-VBUS valid interrupt is enabled

U1OTGSTATUSB OTG Status Register

Address
0xBF885060
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ID7ID Pin State Indicator bit
  • 0 A Type-A cable has been plugged into the USB receptacle
  • 1 No cable is attached or a Type-B cable has been plugged into the USB receptacle
LSTATE5Line State Stable Indicator bit
  • 0 USB line state (U1CON(SE0) and U1CON(JSTATE)) has not been stable for the previous 1 ms
  • 1 USB line state (U1CON(SE0) and U1CON(JSTATE)) has been stable for the previous 1 ms
SESVD3Session Valid Indicator bit
  • 0 Vbus voltage is below Session Valid on the A or B device
  • 1 Vbus voltage is above Session Valid on the A or B device
SESEND2B-Device Session End Indicator bit
  • 0 Vbus voltage is above Session Valid on the B device
  • 1 Vbus voltage is below Session Valid on the B device
VBUSVD0A-Device Vbus Valid Indicator bit
  • 0 Vbus voltage is below Session Valid on the A device
  • 1 Vbus voltage is above Session Valid on the A device

U1OTGCONUSB OTG Control Register

Address
0xBF885070
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DPPULUP7D+ Pull-Up Enable bit
  • 0 D+ data line pull-up resistor is disabled
  • 1 D+ data line pull-up resistor is enabled
DMPULUP6D- Pull-Up Enable bit
  • 0 D- data line pull-up resistor is disabled
  • 1 D- data line pull-up resistor is enabled
DPPULDWN5D+ Pull-Down Enable bit
  • 0 D+ data line pull-down resistor is disabled
  • 1 D+ data line pull-down resistor is enabled
DMPULDWN4D- Pull-Down Enable bit
  • 0 D- data line pull-down resistor is disabled
  • 1 D- data line pull-down resistor is enabled
VBUSON3VBUS Power-on bit
  • 0 VBUS line is not powered
  • 1 VBUS line is powered
OTGEN2OTG Functionality Enable bit
  • 0 DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
  • 1 DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
VBUSCHG1VBUS Charge Enable bit
  • 0 VBUS line is not charged through a resistor
  • 1 VBUS line is charged through a pull-up resistor
VBUSDIS0VBUS Discharge Enable bit
  • 0 VBUS line is not discharged through a resistor
  • 1 VBUS line is discharged through a pull-down resistor

U1PWRCUSB Power Control Register

Address
0xBF885080
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
UACTPND7USB Activity Pending bit
  • 0 An interrupt is not pending
  • 1 USB bus activity has been detected; but an interrupt is pending
USLPGRD4USB Sleep Entry Guard bit
  • 0 USB module does not block Sleep entry
  • 1 Sleep entry is blocked if USB bus activity is detected or if a notification is pending
USBBUSY3USB Module Busy bit
  • 0 USB module is not active and is ready to be enabled
  • 1 USB module is active or disabled
USUSPEND1USB Suspend Mode bit
  • 0 USB module operates normally
  • 1 USB module is placed in Suspend mode
USBPWR0USB Operation Enable bit
  • 0 USB module is disabled
  • 1 USB module is turned on

U1IRUSB Interrupt Register

Address
0xBF885200
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
STALLIF7STALL Handshake Interrupt bit
  • 0 STALL handshake has not been sent
  • 1 (In Host mode) a STALL handshake was received during the handshake phase of the transaction / (In Device mode) a STALL handshake was transmitted during the handshake phase of the transaction
ATTACHIF6Peripheral Attach Interrupt bit
  • 0 Peripheral attachment was not detected
  • 1 Peripheral attachment was detected by the USB module
RESUMEIF5Resume Interrupt bit
  • 0 K-State is not observed
  • 1 K-State is observed on the D+ or D- pin for 2.5 usec
IDLEIF4Idle Detect Interrupt bit
  • 0 No Idle condition detected
  • 1 Idle condition detected (constant Idle state of 3 ms or more)
TRNIF3Token Processing Complete Interrupt bit
  • 0 Processing of current token not complete
  • 1 Processing of current token is complete; a read of the U1STAT register will provide endpoint information
SOFIF2SOF Token Interrupt bit
  • 0 SOF token was not received nor threshold reached
  • 1 SOF token received by the peripheral or the SOF threshold reached by the host
UERRIF1USB Error Condition Interrupt bit
  • 0 Unmasked error condition has not occurred
  • 1 Unmasked error condition has occurred
URSTIF_DETACHIF0

U1IEUSB Interrupt Enable Register

Address
0xBF885210
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
STALLIE7STALL Handshake Interrupt Enable bit
  • 0 STALL interrupt is disabled
  • 1 STALL interrupt is enabled
ATTACHIE6ATTACH Interrupt Enable bit
  • 0 ATTACH interrupt is disabled
  • 1 ATTACH interrupt is enabled
RESUMEIE5RESUME Interrupt Enable bit
  • 0 RESUME interrupt is disabled
  • 1 RESUME interrupt is enabled
IDLEIE4Idle Detect Interrupt Enable bit
  • 0 Idle interrupt is disabled
  • 1 Idle interrupt is enabled
TRNIE3Token Processing Complete Interrupt Enable bit
  • 0 TRNIF interrupt is disabled
  • 1 TRNIF interrupt is enabled
SOFIE2SOF Token Interrupt Enable bit
  • 0 SOFIF interrupt is disabled
  • 1 SOFIF interrupt is enabled
UERRIE1USB Error Interrupt Enable bit
  • 0 USB Error interrupt is disabled
  • 1 USB Error interrupt is enabled
URSTIE_DETACHIE0

U1EIRUSB Error Interrupt Status Register

Address
0xBF885220
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BTSEF7Bit Stuff Error Flag bit
  • 0 Packet is accepted
  • 1 Packet is rejected due to bit stuff error
BMXEF6Bus Matrix Error Flag bit
  • 0 No address error
  • 1 The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, i s invalid
DMAEF5DMA Error Flag bit
  • 0 No DMA error
  • 1 USB DMA error condition detected
BTOEF4Bus Turnaround Time-Out Error Flag bit
  • 0 No bus turnaround time-out
  • 1 Bus turnaround time-out has occurred
DFN8EF3Data Field Size Error Flag bit
  • 0 Data field received is an integral number of bytes
  • 1 Data field received is not an integral number of bytes
CRC16EF2CRC16 Failure Flag bit
  • 0 Data packet accepted
  • 1 Data packet rejected due to CRC16 error
CRC5EF_EOFEF1
PIDEF0PID Check Failure Flag bit
  • 0 PID check is passed
  • 1 PID check is failed

U1EIEUSB Error Interrupt Enable Register

Address
0xBF885230
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BTSEE7Bit Stuff Error Interrupt Enable bit
  • 0 BTSEF interrupt is disabled
  • 1 BTSEF interrupt is enabled
BMXEE6Bus Matrix Error Interrupt Enable bit
  • 0 BMXEF interrupt is disabled
  • 1 BMXEF interrupt is enabled
DMAEE5DMA Error Interrupt Enable bit
  • 0 DMAEF interrupt is disabled
  • 1 DMAEF interrupt is enabled
BTOEE4Bus Turnaround Time-out Error Interrupt Enable bit
  • 0 BTOEF interrupt is disabled
  • 1 BTOEF interrupt is enabled
DFN8EE3Data Field Size Error Interrupt Enable bit
  • 0 DFN8EF interrupt is disabled
  • 1 DFN8EF interrupt is enabled
CRC16EE2CRC16 Failure Interrupt Enable bit
  • 0 CRC16EF interrupt is disabled
  • 1 CRC16EF interrupt is enabled
CRC5EE_EOFEE1
PIDEE0PID Check Failure Interrupt Enable bit
  • 0 PIDEF interrupt is disabled
  • 1 PIDEF interrupt is enabled

U1STATUSB Status Register

Address
0xBF885240
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
FieldBitsWhat it does
ENDPT4Encoded Number of Last Endpoint Activity bits
  • 0 Endpoint 0
  • 1 Endpoint 1
  • 2 Endpoint 2
  • 3 Endpoint 3
  • 4 Endpoint 4
  • 5 Endpoint 5
  • 6 Endpoint 6
  • 7 Endpoint 7
  • 8 Endpoint 8
  • 9 Endpoint 9
  • 10 Endpoint 10
  • 11 Endpoint 11
  • 12 Endpoint 12
  • 13 Endpoint 13
  • 14 Endpoint 14
  • 15 Endpoint 15
DIR3Last BD Direction Indicator bit
  • 0 Last transaction was a receive transfer (RX)
  • 1 Last transaction was a transmit transfer (TX)
PPBI2Ping-Pong BD Pointer Indicator bit
  • 0 The last transaction was to the EVEN BD bank
  • 1 The last transaction was to the ODD BD bank

U1CONUSB Control Register

Address
0xBF885250
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
JSTATE7Live Differential Receiver JSTATE flag bit
  • 0 No JSTATE detected
  • 1 JSTATE detected on the USB
SE06Live Single-Ended Zero flag bit
  • 0 No Single Ended Zero detected
  • 1 Single Ended Zero detected on the USB
PKTDIS_TOKBUSY5
USBRST4Module Reset bit
  • 0 USB reset is terminated
  • 1 USB reset is generated
HOSTEN3Host Mode Enable bit
  • 0 USB host capability is disabled
  • 1 USB host capability is enabled
RESUME2RESUME Signaling Enable bit
  • 0 RESUME signaling is disabled
  • 1 RESUME signaling is activated
PPBRST1Ping-Pong Buffers Reset bit
  • 0 Even/Odd buffer pointers not being Reset
  • 1 Reset all Even/Odd buffer pointers to the EVEN BD banks
USBEN_SOFEN0

U1ADDRUSB Address Register

Address
0xBF885260
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
LSPDEN7Low Speed Enable Indicator bit
  • 0 Next token command to be executed at Full Speed
  • 1 Next token command to be executed at Low Speed
DEVADDR6:07-bit USB Device Address bits
  • 0 Device address is 0
  • 127 Device address is 0x7f

U1BDTP1USB BDT Page 1 Register

Address
0xBF885270
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRL7:1

U1FRMLUSB Frame Number Low Register

Address
0xBF885280
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FRML7:0

U1FRMHUSB Frame Number High Register

Address
0xBF885290
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FRMH2:0

U1TOKUSB Token Register

Address
0xBF8852A0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PID7:4Token Type Indicator bits
  • 1 OUT (TX) token type transaction
  • 9 IN (RX) token type transaction
  • 13 SETUP (TX) token type transaction
EP3:0Token Command Endpoint Address bits
  • 0 Endpoint address is 0

U1SOFUSB SOF Threshold Register

Address
0xBF8852B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CNT7:0SOF Threshold Value bits
  • 18 8-byte packet
  • 26 16-byte packet
  • 42 32-byte packet
  • 74 64-byte packet

U1BDTP2USB BDT PAGE 2 Register

Address
0xBF8852C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRH7:0BDT Base Address bits
  • 0 BDT base address is 0

U1BDTP3USB BDT PAGE 3 Register

Address
0xBF8852D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRU7:0BDT Base Address bits
  • 0 BDT base address is 0

U1CNFG1USB Configuration 1 Register

Address
0xBF8852E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
UTEYE7USB Eye-Pattern Test Enable bit
  • 0 Eye-Pattern Test is disabled
  • 2 Eye-Pattern Test is enabled
UOEMON6
USBSIDL4Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
UASUSPND0Automatic Suspend Enable bit
  • 0 USB module does not automatically suspend upon entry to Sleep mode.
  • 1 USB module automatically suspends upon entry to Sleep mode.

U1EP0USB Endpoint 0 Control Register

Address
0xBF885300
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
LSPD7Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
  • 0 Direct connection to a low-speed device is disabled; hub required with PRE_PID
  • 1 Direct connection to a low-speed device is enabled
RETRYDIS6Retry Disable bit (Host mode and U1EP0 only)
  • 0 Retry NAKed transactions is enabled; retry done in hardware
  • 1 Retry NAKed transactions is disabled
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP1USB Endpoint 1 Control Register

Address
0xBF885310
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP2USB Endpoint 2 Control Register

Address
0xBF885320
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP3USB Endpoint 3 Control Register

Address
0xBF885330
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP4USB Endpoint 4 Control Register

Address
0xBF885340
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP5USB Endpoint 5 Control Register

Address
0xBF885350
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP6USB Endpoint 6 Control Register

Address
0xBF885360
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP7USB Endpoint 7 Control Register

Address
0xBF885370
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP8USB Endpoint 8 Control Register

Address
0xBF885380
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP9USB Endpoint 9 Control Register

Address
0xBF885390
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP10USB Endpoint 10 Control Register

Address
0xBF8853A0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP11USB Endpoint 11 Control Register

Address
0xBF8853B0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP12USB Endpoint 12 Control Register

Address
0xBF8853C0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP13USB Endpoint 13 Control Register

Address
0xBF8853D0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP14USB Endpoint 14 Control Register

Address
0xBF8853E0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U1EP15USB Endpoint 15 Control Register

Address
0xBF8853F0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
  • 1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

PORTA I/O port A

ANSELA

Address
0xBF886000
Reset
0x00000003
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
ANSA11
ANSA00

TRISA

Address
0xBF886010
Reset
0x0000001F
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
TRISA44
TRISA33
TRISA22
TRISA11
TRISA00

PORTA

Address
0xBF886020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
RA44
RA33
RA22
RA11
RA00

LATA

Address
0xBF886030
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
LATA44
LATA33
LATA22
LATA11
LATA00

ODCA

Address
0xBF886040
Reset
0x00000000
Access
read/write
Size
32-bit

CNPUA

Address
0xBF886050
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CNPUA44
CNPUA33
CNPUA22
CNPUA11
CNPUA00

CNPDA

Address
0xBF886060
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CNPDA44
CNPDA33
CNPDA22
CNPDA11
CNPDA00

CNCONA

Address
0xBF886070
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
ON15
SIDL13

CNENA

Address
0xBF886080
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CNIEA44
CNIEA33
CNIEA22
CNIEA11
CNIEA00

CNSTATA

Address
0xBF886090
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CNSTATA44
CNSTATA33
CNSTATA22
CNSTATA11
CNSTATA00

PORTB I/O port B

ANSELB

Address
0xBF886100
Reset
0x0000E00F
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ANSB1515
ANSB1414
ANSB1313
ANSB33
ANSB22
ANSB11
ANSB00

TRISB

Address
0xBF886110
Reset
0x0000EFBF
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
TRISB1515
TRISB1414
TRISB1313
TRISB1111
TRISB1010
TRISB99
TRISB88
TRISB77
TRISB55
TRISB44
TRISB33
TRISB22
TRISB11
TRISB00

PORTB

Address
0xBF886120
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
RB1515
RB1414
RB1313
RB1111
RB1010
RB99
RB88
RB77
RB55
RB44
RB33
RB22
RB11
RB00

LATB

Address
0xBF886130
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
LATB1515
LATB1414
LATB1313
LATB1111
LATB1010
LATB99
LATB88
LATB77
LATB55
LATB44
LATB33
LATB22
LATB11
LATB00

ODCB

Address
0xBF886140
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
ODCB1515
ODCB1414
ODCB1313
ODCB1111
ODCB1010
ODCB99
ODCB88
ODCB77
ODCB55
ODCB44
ODCB33
ODCB22
ODCB11
ODCB00

CNPUB

Address
0xBF886150
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
CNPUB1515
CNPUB1414
CNPUB1313
CNPUB1111
CNPUB1010
CNPUB99
CNPUB88
CNPUB77
CNPUB55
CNPUB44
CNPUB33
CNPUB22
CNPUB11
CNPUB00

CNPDB

Address
0xBF886160
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
CNPDB1515
CNPDB1414
CNPDB1313
CNPDB1111
CNPDB1010
CNPDB99
CNPDB88
CNPDB77
CNPDB55
CNPDB44
CNPDB33
CNPDB22
CNPDB11
CNPDB00

CNCONB

Address
0xBF886170
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
ON15
SIDL13

CNENB

Address
0xBF886180
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
CNIEB1515
CNIEB1414
CNIEB1313
CNIEB1111
CNIEB1010
CNIEB99
CNIEB88
CNIEB77
CNIEB55
CNIEB44
CNIEB33
CNIEB22
CNIEB11
CNIEB00

CNSTATB

Address
0xBF886190
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
CNSTATB1515
CNSTATB1414
CNSTATB1313
CNSTATB1111
CNSTATB1010
CNSTATB99
CNSTATB88
CNSTATB77
CNSTATB55
CNSTATB44
CNSTATB33
CNSTATB22
CNSTATB11
CNSTATB00