All 395 registers by peripheral, at the virtual address XC32 and the datasheet's register tables use (the SFRs from 0xBF800000), with their reset value and every field.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DSCTRL DSCTRL
DSCONDeep Sleep Control Register
Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
DSEN
15
Deep Sleep Enable bit
0 Sleep mode is entered on a WAIT command
1 Deep Sleep mode is entered on a WAIT command
DSGPREN
13
General Purpose Registers Enable bit
0 No general purpose register retention in Deep Sleep mode
1 General purpose register retention is enabled in Deep Sleep mode
DSGPREN
12
General Purpose Registers Enable bit
0 No general purpose register retention in Deep Sleep mode
1 General purpose register retention is enabled in Deep Sleep mode
RTCCWDIS
8
RTCC Wake-up Disable bit
0 Wake-up from RTCC is enabled
1 Wake-up from RTCC is disabled
WAKEDIS
2
Wake-up Source Disable bit
0 External wake-up source is enabled
1 External wake-up source is disabled
DSBOR
1
Deep Sleep BOR Event Status bit
0 DSBOREN was disabled, or VDD did not drop below the DSBOR threshold during Deep Sleep
1 DSBOREN was enabled and VDD dropped below the DSBOR threshold during Deep Sleep
RELEASE
0
IO Pin State Release bit
0 Release IO pins and allow their respective TRIS and LAT bits to control their states
1 Upon waking from Deep Sleep, the IO pins maintain their previous states
DSWAKEDeep Sleep Wake-up Source Register
Address
0xBF800010
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
DSINT0
8
Interrupt-on-Change bit
0 Interrupt-on-change was not asserted during Deep Sleep
1 Interrupt-on-change was asserted during Deep Sleep
DSFLT
7
Deep Sleep Fault Detected bit
0 No Fault was detected during Deep Sleep
1 A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted
DSWDT
4
Deep Sleep Watchdog Timer Time-out bit
0 The Deep Sleep Watchdog Timer did not time-out during Deep Sleep
1 The Deep Sleep Watchdog Timer timed out during Deep Sleep
DSRTC
3
Real-Time Clock and Calendar Alarm bit
0 The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
1 The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
DSMCLR
2
MCLR Event bit
0 The MCLR pin was not active, or was active, but not asserted during Deep Sleep
1 The MCLR pin was active and was asserted during Deep Sleep
DSGPR0
Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR1
Address
0xBF800040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR2
Address
0xBF800044
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR3
Address
0xBF800048
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR4
Address
0xBF80004C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR5
Address
0xBF800050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR6
Address
0xBF800054
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR7
Address
0xBF800058
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR8
Address
0xBF80005C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR9
Address
0xBF800060
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR10
Address
0xBF800064
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR11
Address
0xBF800068
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR12
Address
0xBF80006C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR13
Address
0xBF800070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR14
Address
0xBF800074
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR15
Address
0xBF800078
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR16
Address
0xBF80007C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR17
Address
0xBF800080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR18
Address
0xBF800084
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR19
Address
0xBF800088
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR20
Address
0xBF80008C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR21
Address
0xBF800090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR22
Address
0xBF800094
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR23
Address
0xBF800098
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR24
Address
0xBF80009C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR25
Address
0xBF8000A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR26
Address
0xBF8000A4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR27
Address
0xBF8000A8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR28
Address
0xBF8000AC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR29
Address
0xBF8000B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR30
Address
0xBF8000B4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR31
Address
0xBF8000B8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
DSGPR32
Address
0xBF8000BC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DSGPR
31:0
RTCC Real-time clock and calendar
RTCCONReal-Time Clock and Calendar Control Register
Address
0xBF800200
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
CAL
25:16
Real-Time Clock Drift Calibration bits
0 No adjustment
1 Minimum positive adjustment, adds 1 real-time clock pulse every one minute
511 Maximum positive adjustment, adds 511 real-time clock pulses every one minute
512 Minimum negative adjustment, subtracts 512 real-time clock pulses every one minute
1023 Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
ON
15
RTCC On bit
0 RTCC module is disabled
1 RTCC module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue normal operation when CPU enters Idle mode
1 Disables RTCC operation when CPU enters Idle mode
RTCCLKSEL
10:9
RTCC Clock Select bits
0 RTCC uses the internal 32 kHz oscillator (LPRC)
1 RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
2 Reserved
3 Reserved
RTCOUTSEL
8:7
RTCC Output Data Select bits
0 Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
1 Seconds Clock is presented on the RTCC pin
2 RTCC Clock is presented on the RTCC pin
3 Reserved
RTCCLKON
6
RTCC Clock Enable Status bit
0 RTCC Clock is not running
1 RTCC Clock is actively running
RTCWREN
3
Real-Time Clock Value Registers Write Enable bit
0 Real-Time Clock Value registers are locked out from being written to by the user
1 Real-Time Clock Value registers can be written to by the user
RTCSYNC
2
Real-Time Clock Value Registers Read Synchronization bit
0 Real-time clock value registers can be read without concern about a rollover ripple
1 Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid data read). If the register is read twice and results in the same data
HALFSEC
1
Half-Second Status bit
0 First half period of a second
1 Second half period of a second
RTCOE
0
RTCC Output Enable bit
0 RTCC output is not enabled
1 RTCC output is enabled
RTCALRMReal-Time Clock ALARM Control Register
Address
0xBF800210
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ALRMEN
15
Alarm Enable bit
0 Alarm is disabled
1 Alarm is enabled
CHIME
14
Chime Enable bit
0 Chime is disabled ARPT stops once it reaches 0x00
1 Chime is enabled ARPT is allowed to rollover from 0x00 to 0xFF
PIV
13
Alarm Pulse Initial Value bit
0 (When ALRMEN is 0)low initial value of the Alarm Pulse / (when ALRMEN is 1) PIV is read-only and returns the state of the Alarm Pulse
1 (When ALRMEN is 0)high initial value of the Alarm Pulse / (when ALRMEN is 1) PIV is read-only and returns the state of the Alarm Pulse
ALRMSYNC
12
Alarm Sync bit
0 ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover
1 ARPT and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing.
AMASK
11:8
Alarm Mask Configuration bits
0 Every half-second
1 Every second
2 Every 10 seconds
3 Every minute
4 Every 10 minutes
5 Every hour
6 Once a day
7 Once a week
8 Once a month
9 Once a year (except when configured for February 29
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
ARPT
7:0
Alarm Repeat Counter Value bits
0 Alarm will trigger one time
1 Alarm will trigger two times
254 Alarm will trigger 255 times
255 Alarm will trigger 256 times
RTCTIMEReal-Time Clock Time Value Register
Address
0xBF800220
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
HR01
27:24
MIN10
23:20
MIN01
19:16
SEC10
15:12
SEC01
11:8
HR10
31:28
RTCDATEReal-Time Clock Date Value Register
Address
0xBF800230
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
YEAR01
27:24
MONTH10
23:20
MONTH01
19:16
DAY10
15:12
DAY01
11:8
WDAY01
3:0
YEAR10
31:28
ALRMTIMEAlarm Time Value Register
Address
0xBF800240
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
HR01
27:24
MIN10
23:20
MIN01
19:16
SEC10
15:12
SEC01
11:8
HR10
31:28
ALRMDATEAlarm Date Value Register
Address
0xBF800250
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
MONTH10
23:20
MONTH01
19:16
DAY10
15:12
DAY01
11:8
WDAY01
3:0
TMR1 Timer 1
T1CONTYPE A TIMER CONTROL REGISTER
Address
0xBF800600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Timer is disabled
1 Timer is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TWDIS
12
Asynchronous Timer Write Disable bit
0 Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
1 Writes to TMR1 are ignored until pending write operation completes
TWIP
11
Asynchronous Timer Write in Progress bit
0 In Asynchronous Timer mode Asynchronous write to TMR1 register complete / (In Synchronous Timer mode)bit is read as 0
1 (In Asynchronous Timer mode) Asynchronous write to TMR1 register in progress / (In Synchronous Timer mode)bit is read as 0
TECS
9:8
Timer1 External Clock Selection bits
0 External clock comes from the SOSC
1 External clock comes from the T1CK pin
2 External clock comes from the LPRC
3 Reserved
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0) Gated time accumulation is disabled / (When TCS is 1) bit is ignored
1 (When TCS is 0) Gated time accumulation is enabled / (When TCS is 1) bit is ignored
TCKPS
5:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:8 prescale value
2 1:64 prescale value
3 1:256 prescale value
TSYNC
2
Timer External Clock Input Synchronization Selection bit
0 (When TCS is 1) External clock input is not synchronized / (When TCS is 0) This bit is ignored
1 (When TCS is 1) External clock input is synchronized / (When TCS is 0) This bit is ignored
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock is defined by the TECS bits
TMR1
Address
0xBF800610
Reset
0x00000000
Access
read/write
Size
32-bit
PR1
Address
0xBF800620
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR2 Timer 2
T2CONType B Timer Control Register
Address
0xBF800800
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation when the device enters Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0): Gated time accumulation is disabled / (When TCS is 1): bit is ignored and read as 0
1 (When TCS is 0): Gated time accumulation is enabled / (When TCS is 1): bit is ignored and read as 0
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
T32
3
32-Bit Timer Mode Select bit
0 Odd numbered and even numbered timers form a separate 16-bit timer
1 Odd numbered and even numbered timers form a 32-bit timer
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock from TxCK pin
TMR2
Address
0xBF800810
Reset
0x00000000
Access
read/write
Size
32-bit
PR2
Address
0xBF800820
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR3 Timer 3
T3CONType B Timer Control Register
Address
0xBF800A00
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation when the device enters Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0): Gated time accumulation is disabled / (When TCS is 1): bit is ignored and read as 0
1 (When TCS is 0): Gated time accumulation is enabled / (When TCS is 1): bit is ignored and read as 0
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock from TxCK pin
TMR3
Address
0xBF800A10
Reset
0x00000000
Access
read/write
Size
32-bit
PR3
Address
0xBF800A20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR4 Timer 4
T4CONType B Timer Control Register
Address
0xBF800C00
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation when the device enters Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0): Gated time accumulation is disabled / (When TCS is 1): bit is ignored and read as 0
1 (When TCS is 0): Gated time accumulation is enabled / (When TCS is 1): bit is ignored and read as 0
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
T32
3
32-Bit Timer Mode Select bit
0 Odd numbered and even numbered timers form a separate 16-bit timer
1 Odd numbered and even numbered timers form a 32-bit timer
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock from TxCK pin
TMR4
Address
0xBF800C10
Reset
0x00000000
Access
read/write
Size
32-bit
PR4
Address
0xBF800C20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR5 Timer 5
T5CONType B Timer Control Register
Address
0xBF800E00
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation when the device enters Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0): Gated time accumulation is disabled / (When TCS is 1): bit is ignored and read as 0
1 (When TCS is 0): Gated time accumulation is enabled / (When TCS is 1): bit is ignored and read as 0
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock from TxCK pin
TMR5
Address
0xBF800E10
Reset
0x00000000
Access
read/write
Size
32-bit
PR5
Address
0xBF800E20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
IC1 Input capture 1
IC1CONInput Capture 1 Control Register
Address
0xBF802000
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC1BUF
Address
0xBF802010
Reset
0x00000000
Access
read only
Size
32-bit
IC2 Input capture 2
IC2CONInput Capture 1 Control Register
Address
0xBF802200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC2BUF
Address
0xBF802210
Reset
0x00000000
Access
read only
Size
32-bit
IC3 Input capture 3
IC3CONInput Capture 1 Control Register
Address
0xBF802400
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC3BUF
Address
0xBF802410
Reset
0x00000000
Access
read only
Size
32-bit
IC4 Input capture 4
IC4CONInput Capture 1 Control Register
Address
0xBF802600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC4BUF
Address
0xBF802610
Reset
0x00000000
Access
read only
Size
32-bit
IC5 Input capture 5
IC5CONInput Capture 1 Control Register
Address
0xBF802800
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC5BUF
Address
0xBF802810
Reset
0x00000000
Access
read only
Size
32-bit
OC1 Output compare 1
OC1CONOutput Compare 'x' Control Register
Address
0xBF803000
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ON
15
Output Compare Peripheral On bit
0 Output Compare peripheral is disabled
1 Output Compare peripheral is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when CPU enters Idle mode
OC32
5
32-bit Compare Mode bit
0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT
4
PWM Fault Condition Status bit
0 No PWM Fault condition has occurred
1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL
3
Output Compare Timer Select bit
0 Timer2 is the clock source for this Output Compare module
1 Timer3 is the clock source for this Output Compare module
OCM
2:0
Output Compare Mode Select bits
0 Output compare peripheral is disabled but continues to draw current
SPI Data Input Sample Phase bit (master mode only)
0 (Master mode) Input data sampled at middle of data output time / (Slave mode) value is ignored
1 (Master mode) Input data sampled at end of data output time / (Slave mode) value is ignored
CKE
8
SPI Clock Edge Select bit
0 Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
1 Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
SSEN
7
Slave Select Enable bit
0 SSx pin not used for Slave mode
1 SSx pin used for Slave mode
CKP
6
Clock Polarity Select bit
0 Idle state for clock is a low level; active state is a high level
1 Idle state for clock is a high level; active state is a low level
MSTEN
5
Master Mode Enable bit
0 Slave mode
1 Master mode
DISSDI
4
Disable SDI bit
0 SDI pin is controlled by the SPI module
1 SDI pin is not used by the SPI module (pin is controlled by PORT function)
STXISEL
3:2
SPI Transmit Buffer Empty Interrupt Mode bits
0 Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
1 Interrupt is generated when the buffer is completely empty
2 Interrupt is generated when the buffer is empty by one-half or more
3 Interrupt is generated when the buffer is not full (has one or more empty elements)
SRXISEL
1:0
SPI Receive Buffer Full Interrupt Mode bits
0 Interrupt is generated when the last word in the receive buffer is read (i.e. buffer is empty)
1 Interrupt is generated when the buffer is not empty
2 Interrupt is generated when the buffer is full by one-half or more
3 Interrupt is generated when the buffer is full
FRMEN
31
Framed SPI Support bit
0 Framed SPI support is disabled
1 Framed SPI support is enabled (SSx pin used as FSYNC input/output)
SPI2STATSPI Status Register
Address
0xBF805A10
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
RXBUFELM
28:24
TXBUFELM
20:16
FRMERR
12
SPI Frame Error status bit
0 No Frame error detected
1 Frame error detected
SPIBUSY
11
SPI Activity Status bit
0 SPI peripheral is currently idle
1 SPI peripheral is currently busy with some transactions
SPITUR
8
Transmit Under Run bit
0 Transmit buffer has no underrun condition
1 Transmit buffer has encountered an underrun condition
SRMT
7
Shift Register Empty bit
0 When SPI module shift register is not empty
1 When SPI module shift register is empty
SPIROV
6
Receive Overflow Flag bit
0 No overflow has occurred
1 A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.
SPIRBE
5
RX FIFO Empty bit (valid only when ENHBUF = 1)
0 RX FIFO is not empty (CRPTR != SWPTR)
1 RX FIFO is empty (CRPTR = SWPTR)
SPITBE
3
SPI Transmit Buffer Empty Status bit
0 Transmit buffer SPIxTXB is not empty
1 Transmit buffer SPIxTXB is empty
SPITBF
1
SPI Transmit Buffer Full Status bit
0 Transmit buffer is not full
1 Transmit not yet started SPITXB is full
SPIRBF
0
SPI Receive Buffer Full Status bit
0 Receive buffer SPIxRXB is not full
1 Receive buffer SPIxRXB is full
SPI2BUF
Address
0xBF805A20
Reset
0x00000000
Access
read/write
Size
32-bit
SPI2BRG
Address
0xBF805A30
Reset
0x00000000
Access
read/write
Size
32-bit
SPI2CON2SPI Control Register 2
Address
0xBF805A40
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
SPISGNEXT
15
Sign Extend Read Data from the RX FIFO bit
0 Data from RX FIFO is not sign extened
1 Data from RX FIFO is sign extended
FRMERREN
12
Enable Interrupt Events via FRMERR bit
0 Frame Error does not generate error events
1 Frame Error overflow generates error events
SPIROVEN
11
Enable Interrupt Events via SPIROV bit
0 Receive overflow does not generate error events
1 Receive overflow generates error events
SPITUREN
10
Enable Interrupt Events via SPITUR bit
0 Transmit Underrun Does Not Generates Error Events
1 Transmit Underrun Generates Error Events
IGNROV
9
Ignore Receive Overflow bit
0 A ROV is a critical error which stop SPI operation
1 A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
IGNTUR
8
Ignore Transmit Underrun bit
0 A TUR is a critical error which stop SPI operation
1 A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
AUDEN
7
Enable Audio CODEC Support bit
0 Audio protocol disabled
1 Audio protocol enabled
AUDMONO
3
Transmit Audio Data Format bit
0 Audio data is stereo
1 Audio data is mono (Each data word is transmitted on both left and right channels)
AUDMOD
1:0
Audio Protocol Mode bit
0 I2S mode
1 Left Justified mode
2 Right Justified mode
3 PCM/DSP mode
UART1 UART 1
U1MODEUARTx Mode Register
Address
0xBF806000
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
SLPEN
23
Run During Sleep Enable bit
0 UARTx BRG clock is turned off during Sleep mode
1 UARTx BRG clock runs during Sleep mode
ACTIVE
22
UARTx Module Running Status bit
0 UARTx module is not active (UxMODE register can be updated)
1 UARTx module is active (UxMODE register should not be updated)
CLKSEL
18:17
UARTx Module Clock Selection bits
0 BRG clock is PBCLK (turned off in Sleep mode)
1 BRG clock is SYSCLK (turned off in Sleep mode)
2 BRG clock is FRC
3 BRG clock is PBCLK
OVFDIS
16
ON
15
UARTx Enable bit
0 UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx, and LATx registers; UARTx power consumption is minimal
1 UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when device enters Idle mode
IREN
12
IrDA Encoder and Decoder Enable bit
0 IrDA is disabled
1 IrDA is enabled
RTSMD
11
Mode Selection for UxRTS Pin bit
0 UxRTS pin is in Flow Control mode
1 UxRTS pin is in Simplex mode
UEN
9:8
UARTx Module Enable bits
0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
1 UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
2 UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
3 UxTX, UxRX and UxBCLK pins are enabled and used
WAKE
7
Enable Wake-up on Start bit Detect During Sleep Mode bit
0 Wake-up disabled
1 Wake-up enabled
LPBACK
6
UARTx Loopback Mode Select bit
0 Loopback mode is disabled
1 Loopback mode is enabled
ABAUD
5
Auto-Baud Enable bit
0 Baud rate measurement disabled or completed
1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV
4
Receive Polarity Inversion bit
0 UxRX Idle state is 1
1 UxRX Idle state is 0
BRGH
3
High Baud Rate Enable bit
0 Standard Speed mode 16x baud clock enabled
1 High-Speed mode 4x baud clock enabled
PDSEL
2:1
Parity and Data Selection bits
0 8-bit data, no parity
1 8-bit data, even parity
2 8-bit data, odd parity
3 9-bit data, no parity
STSEL
0
Stop Selection bit
0 1 Stop bit
1 2 Stop bits
U1STAUARTx Status and Control Register
Address
0xBF806010
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ADDR
23:16
UTXISEL
15:14
TX Interrupt Mode Selection bits
0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
1 Interrupt is generated and asserted when all characters have been transmitted
2 Interrupt is generated and asserted while the transmit buffer is empty
3 Reserved
UTXINV
13
Transmit Polarity Inversion bit
0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN
12
Receiver Enable bit
0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK
11
Transmit Break bit
0 Break transmission is disabled or completed
1 Send Break on next transmission. Start bit followed by twelve 0 bits
UTXEN
10
Transmit Enable bit
0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF
9
Transmit Buffer Full Status bit (read-only)
0 Transmit buffer is not full, at least one more character can be written
1 Transmit buffer is full
TRMT
8
Transmit Shift Register is Empty bit (read-only)
0 Transmit shift register is not empty
1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL
7:6
Receive Interrupt Mode Selection bit
0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
3 Reserved
ADDEN
5
Address Character Detect bit (bit 8 of received data = 1)
0 Address Detect mode is disabled
1 Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
RIDLE
4
Receiver Idle bit (read-only)
0 Data is being received
1 Receiver is Idle
PERR
3
Parity Error Status bit (read-only)
0 Parity error has not been detected
1 Parity error has been detected for the current character
FERR
2
Framing Error Status bit (read-only)
0 Framing error has not been detected
1 Framing error has been detected for the current character
OERR
1
Receive Buffer Overrun Error Status bit.
0 Receive buffer has not overflowed
1 Receive buffer has overflowed
URXDA
0
Receive Buffer Data Available bit (read-only)
0 Receive buffer is empty
1 Receive buffer has data
MASK
31:24
UARTx Address Match Mask bits
0 Corresponding ADDRx bits are not used to detect the address match.
510 Corresponding ADDRx bits are used to detect the address match
U1TXREG
Address
0xBF806020
Reset
0x00000000
Access
read/write
Size
32-bit
U1RXREG
Address
0xBF806030
Reset
0x00000000
Access
read only
Size
32-bit
U1BRG
Address
0xBF806040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BRG
19:0
Baud Rate Generator
1 Divisor value is 1
UART2 UART 2
U2MODEUARTx Mode Register
Address
0xBF806200
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
SLPEN
23
Run During Sleep Enable bit
0 UARTx BRG clock is turned off during Sleep mode
1 UARTx BRG clock runs during Sleep mode
ACTIVE
22
UARTx Module Running Status bit
0 UARTx module is not active (UxMODE register can be updated)
1 UARTx module is active (UxMODE register should not be updated)
CLKSEL
18:17
UARTx Module Clock Selection bits
0 BRG clock is PBCLK (turned off in Sleep mode)
1 BRG clock is SYSCLK (turned off in Sleep mode)
2 BRG clock is FRC
3 BRG clock is PBCLK
OVFDIS
16
ON
15
UARTx Enable bit
0 UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx, and LATx registers; UARTx power consumption is minimal
1 UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when device enters Idle mode
IREN
12
IrDA Encoder and Decoder Enable bit
0 IrDA is disabled
1 IrDA is enabled
RTSMD
11
Mode Selection for UxRTS Pin bit
0 UxRTS pin is in Flow Control mode
1 UxRTS pin is in Simplex mode
UEN
9:8
UARTx Module Enable bits
0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
1 UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
2 UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
3 UxTX, UxRX and UxBCLK pins are enabled and used
WAKE
7
Enable Wake-up on Start bit Detect During Sleep Mode bit
0 Wake-up disabled
1 Wake-up enabled
LPBACK
6
UARTx Loopback Mode Select bit
0 Loopback mode is disabled
1 Loopback mode is enabled
ABAUD
5
Auto-Baud Enable bit
0 Baud rate measurement disabled or completed
1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV
4
Receive Polarity Inversion bit
0 UxRX Idle state is 1
1 UxRX Idle state is 0
BRGH
3
High Baud Rate Enable bit
0 Standard Speed mode 16x baud clock enabled
1 High-Speed mode 4x baud clock enabled
PDSEL
2:1
Parity and Data Selection bits
0 8-bit data, no parity
1 8-bit data, even parity
2 8-bit data, odd parity
3 9-bit data, no parity
STSEL
0
Stop Selection bit
0 1 Stop bit
1 2 Stop bits
U2STAUARTx Status and Control Register
Address
0xBF806210
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ADDR
23:16
UTXISEL
15:14
TX Interrupt Mode Selection bits
0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
1 Interrupt is generated and asserted when all characters have been transmitted
2 Interrupt is generated and asserted while the transmit buffer is empty
3 Reserved
UTXINV
13
Transmit Polarity Inversion bit
0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN
12
Receiver Enable bit
0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK
11
Transmit Break bit
0 Break transmission is disabled or completed
1 Send Break on next transmission. Start bit followed by twelve 0 bits
UTXEN
10
Transmit Enable bit
0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF
9
Transmit Buffer Full Status bit (read-only)
0 Transmit buffer is not full, at least one more character can be written
1 Transmit buffer is full
TRMT
8
Transmit Shift Register is Empty bit (read-only)
0 Transmit shift register is not empty
1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL
7:6
Receive Interrupt Mode Selection bit
0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
3 Reserved
ADDEN
5
Address Character Detect bit (bit 8 of received data = 1)
0 Address Detect mode is disabled
1 Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
RIDLE
4
Receiver Idle bit (read-only)
0 Data is being received
1 Receiver is Idle
PERR
3
Parity Error Status bit (read-only)
0 Parity error has not been detected
1 Parity error has been detected for the current character
FERR
2
Framing Error Status bit (read-only)
0 Framing error has not been detected
1 Framing error has been detected for the current character
OERR
1
Receive Buffer Overrun Error Status bit.
0 Receive buffer has not overflowed
1 Receive buffer has overflowed
URXDA
0
Receive Buffer Data Available bit (read-only)
0 Receive buffer is empty
1 Receive buffer has data
MASK
31:24
UARTx Address Match Mask bits
0 Corresponding ADDRx bits are not used to detect the address match.
510 Corresponding ADDRx bits are used to detect the address match
U2TXREG
Address
0xBF806220
Reset
0x00000000
Access
read/write
Size
32-bit
U2RXREG
Address
0xBF806230
Reset
0x00000000
Access
read only
Size
32-bit
U2BRG
Address
0xBF806240
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BRG
19:0
Baud Rate Generator
1 Divisor value is 1
PMP Parallel master port
PMCONParallel Port Control Register
Address
0xBF807000
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
RDSTART
23
Start Read on PMP Bus bit
0 No effect
1 Start a read cycle on the PMP bus
DUALBUF
17
ON
15
Parallel Master Port Enable bit
0 PMP disabled, no off-chip access performed
1 PMP is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation when the device enters Idle mode
1 Discontinue module operation when device enters Idle mode
ADRMUX
12:11
Address/Data Multiplexing Selection bits
0 Address and data appear on separate pins
1 Lower 8 bits of address are multiplexed on PMD pins, upper bits are on PMA(10-8) and PMCS1
2 All 16 bits of address are multiplexed on PMD pins
3 Lower 8 bits of address are multiplexed on PMD pins; upper 8 bits are not used
1 Interrupt is generated at the end of the read/write cycle
2 Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)or on a read or write operation when PMA = 11 (Addressable Slave mode only)
3 Reserved
INCM
12:11
Increment Mode bits
0 No increment or decrement of address
1 Increment ADDR(10:2) and ADDR(14) by 1 every read/write cycle
2 Decrement ADDR(10:2) and ADDR(14) by 1 every read/write cycle
0 Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD
1 Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD, and PMA
2 Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD)
3 Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD)
WAITB
7:6
Data Setup to Read/Write Strobe Wait States bits
0 Data wait of 1 Tpbclk2
1 Data wait of 2 Tpbclk2
2 Data wait of 3 Tpbclk2
3 Data wait of 4 Tpbclk2
WAITM
5:2
Data Read/Write Strobe Wait States bits
0 Wait of 1 Tpbclk2 (default)
1 Wait of 2 Tpbclk2
2 Wait of 3 Tpbclk2
3 Wait of 4 Tpbclk2
4 Wait of 5 Tpbclk2
5 Wait of 6 Tpbclk2
6 Wait of 7 Tpbclk2
7 Wait of 8 Tpbclk2
8 Wait of 9 Tpbclk2
9 Wait of 10 Tpbclk2
10 Wait of 11 Tpbclk2
11 Wait of 12 Tpbclk2
12 Wait of 13 Tpbclk2
13 Wait of 14 Tpbclk2
14 Wait of 15 Tpbclk2
15 Wait of 16 Tpbclk2
WAITE
1:0
Data Hold After Read/Write Strobe Wait States bits
0 (for writes) Wait of 1 Tpbclk2 (default) / (for reads) Wait of 0 Tpbclk2 (default)
1 (for writes) Wait of 2 Tpbclk2 / (for reads) Wait of 1 Tpbclk2
2 (for writes) Wait of 3 Tpbclk2 / (for reads) Wait of 2 Tpbclk2
3 (for writes) Wait of 4 Tpbclk2 / (for reads) Wait of 3 Tpbclk2
PMADDRParallel Port Address Register
Address
0xBF807020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ADDR14
14
ADDR
13:0
Destination Address bits
0 Address is 0
PMDOUTParallel Port Output Data Register
Address
0xBF807030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATAOUT
31:0
PMDINParallel Port Input Data Register
Address
0xBF807040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATAIN
31:0
PMAENParallel Port Pin Enable Register
Address
0xBF807050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PTEN
23:0
PMALH/PMALL Port Enable bits
0 PMA1 and PMA0 pads function as port I/O
1 PMA1 and PMA0 function as either PMA or PMALH and PMALL
PMSTATParallel Port Status Register (Slave modes only)
Address
0xBF807060
Reset
0x0000008F
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
IBF
15
Input Buffer Full Status bit
0 Some or all of the writable input buffer registers are empty
1 All writable input buffer registers are full
IBOV
14
Input Buffer Overflow Status bit
0 No overflow is occurred
1 A write attempt to a full input byte buffer is occurred (must be cleared in software)
IB3F
11
Input Buffer 3 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB2F
10
Input Buffer 2 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB1F
9
Input Buffer 1 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB0F
8
Input Buffer 0 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
OBE
7
Output Buffer Empty Status bit
0 Some or all of the readable output buffer registers are full
1 All readable output buffer registers are empty
OBUF
6
Output Buffer Underflow Status bit
0 No underflow is occurred
1 A read occurred from an empty output byte buffer (must be cleared in software)
OB3E
3
Output Buffer 3 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB2E
2
Output Buffer 2 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB1E
1
Output Buffer 1 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB0E
0
Output Buffer 0 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
PMWADDRParallel Port Write Address Register
Address
0xBF807070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
WADDR
23:0
Address bits
0 Address is 0
PMRADDRParallel Port Read Address Register
Address
0xBF807080
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
RADDR15
15
RADDR14
14
RADDR
13:0
Address bits
PMRDINParallel Port Read Input Data Register
Address
0xBF807090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RDATAIN
31:0
ADC Analog-to-digital converter
AD1CON1ADC Control Register 1
Address
0xBF809000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
ADC Operating Mode bit
0 ADC module is not operating
1 ADC module is operating
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
FORM
10:8
Data Output Format bits
0 Integer 16-bit
1 Signed Integer 16-bit
2 Fractional 16-bit
3 Signed Fractional 16-bit
4 Integer 32-bit
5 Signed Integer 32-bit
6 Fractional 32-bit
7 Signed Fractional 32-bit
SSRC
7:5
Conversion Trigger Source Select bits
0 Clearing SAMP bit ends sampling and starts conversion
1 Active transition on INT0 pin ends sampling and starts conversion
2 Timer 3 period match ends sampling and starts conversion
3 CTMU ends sampling and starts conversion
4 Reserved
5 Reserved
6 Reserved
7 Internal counter ends sampling and starts conversion (auto convert)
CLRASAM
4
Stop Conversion Sequence bit (when the first ADC interrupt is generated)
0 Normal operation, buffer contents will be overwritten by the next conversion sequence
1 Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated
ASAM
2
ADC Sample Auto-Start bit
0 Sampling begins when SAMP bit is set
1 Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
SAMP
1
ADC Sample Enable bit
0 The ADC sample/hold amplifier is holding
1 The ADC sample and hold amplifier is sampling
DONE
0
Analog-to-Digital Conversion Status bit
0 Analog-to-digital conversion is not done or has not started
1 Analog-to-digital conversion is done
AD1CON2ADC Control Register 2
Address
0xBF809010
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
VCFG
15:13
Voltage Reference Configuration bits
0 VREFH is AVDD and VREFL is AVSS
1 VREFH is External VREF+ pin and VREFL is AVSS
2 VREFH is AVDD and VREFL is External VREF- pin
3 VREFH is External VREF+ pin and VREFL is External VREF- pin
4 VREFH is AVDD and VREFL is AVSS
5 VREFH is AVDD and VREFL is AVSS
6 VREFH is AVDD and VREFL is AVSS
7 VREFH is AVDD and VREFL is AVSS
OFFCAL
12
Input Offset Calibration Mode Select bit
0 Disable Offset Calibration mode
1 Enable Offset Calibration mode
CSCNA
10
Input Scan Select bit
0 Do not scan inputs
1 Scan inputs
BUFS
7
Buffer Fill Status bit
0 ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
1 ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
SMPI
5:2
Sample/Convert Sequences Per Interrupt Selection bits
0 Interrupts at the completion of conversion for each sample/convert sequence
1 Interrupts at the completion of conversion for each 2nd sample/convert sequence
2 Interrupts at the completion of conversion for each 3rd sample/convert sequence
3 Interrupts at the completion of conversion for each 4th sample/convert sequence
4 Interrupts at the completion of conversion for each 5th sample/convert sequence
5 Interrupts at the completion of conversion for each 6th sample/convert sequence
6 Interrupts at the completion of conversion for each 7th sample/convert sequence
7 Interrupts at the completion of conversion for each 8th sample/convert sequence
8 Interrupts at the completion of conversion for each 9th sample/convert sequence
9 Interrupts at the completion of conversion for each 10th sample/convert sequence
10 Interrupts at the completion of conversion for each 11th sample/convert sequence
11 Interrupts at the completion of conversion for each 12th sample/convert sequence
12 Interrupts at the completion of conversion for each 13th sample/convert sequence
13 Interrupts at the completion of conversion for each 14th sample/convert sequence
14 Interrupts at the completion of conversion for each 15th sample/convert sequence
15 Interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM
1
ADC Result Buffer Mode Select bit
0 Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
1 Buffer configured as two 8-word buffers
ALTS
0
Alternate Input Sample Mode Select bit
0 Always use Sample A input multiplexer settings
1 Uses Sample A input multiplexer settings for first sample then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples
AD1CON3ADC Control Register 3
Address
0xBF809020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ADRC
15
ADC Conversion Clock Source bit
0 Clock derived from Peripheral Bus Clock (PBCLK)
1 Clock derived from FRC
SAMC
12:8
Auto-Sample Time bits
1 1 TAD
2 2 TAD
3 3 TAD
4 4 TAD
5 5 TAD
6 6 TAD
7 7 TAD
8 8 TAD
9 9 TAD
10 10 TAD
11 11 TAD
12 12 TAD
13 13 TAD
14 14 TAD
15 15 TAD
16 16 TAD
17 17 TAD
18 18 TAD
19 19 TAD
20 20 TAD
21 21 TAD
22 22 TAD
23 23 TAD
24 24 TAD
25 25 TAD
26 26 TAD
27 27 TAD
28 28 TAD
29 29 TAD
30 30 TAD
31 31 TAD
ADCS
7:0
ADC Conversion Clock Select bits
0 2 TPB
1 4 TPB
2 6 TPB
3 8 TPB
4 10 TPB
5 12 TPB
6 14 TPB
7 16 TPB
8 18 TPB
9 20 TPB
10 22 TPB
11 24 TPB
12 26 TPB
13 28 TPB
14 30 TPB
15 32 TPB
16 34 TPB
17 36 TPB
18 38 TPB
19 40 TPB
20 42 TPB
21 44 TPB
22 46 TPB
23 48 TPB
24 50 TPB
25 52 TPB
26 54 TPB
27 56 TPB
28 58 TPB
29 60 TPB
30 62 TPB
31 64 TPB
32 66 TPB
33 68 TPB
34 70 TPB
35 72 TPB
36 74 TPB
37 76 TPB
38 78 TPB
39 80 TPB
40 82 TPB
41 84 TPB
42 86 TPB
43 88 TPB
44 90 TPB
45 92 TPB
46 94 TPB
47 96 TPB
48 98 TPB
49 100 TPB
50 102 TPB
51 104 TPB
52 106 TPB
53 108 TPB
54 110 TPB
55 112 TPB
56 114 TPB
57 116 TPB
58 118 TPB
59 120 TPB
60 122 TPB
61 124 TPB
62 126 TPB
63 128 TPB
64 130 TPB
65 132 TPB
66 134 TPB
67 136 TPB
68 138 TPB
69 140 TPB
70 142 TPB
71 144 TPB
72 146 TPB
73 148 TPB
74 150 TPB
75 152 TPB
76 154 TPB
77 156 TPB
78 158 TPB
79 160 TPB
80 162 TPB
81 164 TPB
82 166 TPB
83 168 TPB
84 170 TPB
85 172 TPB
86 174 TPB
87 176 TPB
88 178 TPB
89 180 TPB
90 182 TPB
91 184 TPB
92 186 TPB
93 188 TPB
94 190 TPB
95 192 TPB
96 194 TPB
97 196 TPB
98 198 TPB
99 200 TPB
100 202 TPB
101 204 TPB
102 206 TPB
103 208 TPB
104 210 TPB
105 212 TPB
106 214 TPB
107 216 TPB
108 218 TPB
109 220 TPB
110 222 TPB
111 224 TPB
112 226 TPB
113 228 TPB
114 230 TPB
115 232 TPB
116 234 TPB
117 236 TPB
118 238 TPB
119 240 TPB
120 242 TPB
121 244 TPB
122 246 TPB
123 248 TPB
124 250 TPB
125 252 TPB
126 254 TPB
127 256 TPB
128 258 TPB
129 260 TPB
130 262 TPB
131 264 TPB
132 266 TPB
133 268 TPB
134 270 TPB
135 272 TPB
136 274 TPB
137 276 TPB
138 278 TPB
139 280 TPB
140 282 TPB
141 284 TPB
142 286 TPB
143 288 TPB
144 290 TPB
145 292 TPB
146 294 TPB
147 296 TPB
148 298 TPB
149 300 TPB
150 302 TPB
151 304 TPB
152 306 TPB
153 308 TPB
154 310 TPB
155 312 TPB
156 314 TPB
157 316 TPB
158 318 TPB
159 320 TPB
160 322 TPB
161 324 TPB
162 326 TPB
163 328 TPB
164 330 TPB
165 332 TPB
166 334 TPB
167 336 TPB
168 338 TPB
169 340 TPB
170 342 TPB
171 344 TPB
172 346 TPB
173 348 TPB
174 350 TPB
175 352 TPB
176 354 TPB
177 356 TPB
178 358 TPB
179 360 TPB
180 362 TPB
181 364 TPB
182 366 TPB
183 368 TPB
184 370 TPB
185 372 TPB
186 374 TPB
187 376 TPB
188 378 TPB
189 380 TPB
190 382 TPB
191 384 TPB
192 386 TPB
193 388 TPB
194 390 TPB
195 392 TPB
196 394 TPB
197 396 TPB
198 398 TPB
199 400 TPB
200 402 TPB
201 404 TPB
202 406 TPB
203 408 TPB
204 410 TPB
205 412 TPB
206 414 TPB
207 416 TPB
208 418 TPB
209 420 TPB
210 422 TPB
211 424 TPB
212 426 TPB
213 428 TPB
214 430 TPB
215 432 TPB
216 434 TPB
217 436 TPB
218 438 TPB
219 440 TPB
220 442 TPB
221 444 TPB
222 446 TPB
223 448 TPB
224 450 TPB
225 452 TPB
226 454 TPB
227 456 TPB
228 458 TPB
229 460 TPB
230 462 TPB
231 464 TPB
232 466 TPB
233 468 TPB
234 470 TPB
235 472 TPB
236 474 TPB
237 476 TPB
238 478 TPB
239 480 TPB
240 482 TPB
241 484 TPB
242 486 TPB
243 488 TPB
244 490 TPB
245 492 TPB
246 494 TPB
247 496 TPB
248 498 TPB
249 500 TPB
250 502 TPB
251 504 TPB
252 506 TPB
253 508 TPB
254 510 TPB
255 512 TPB
AD1CHSADC Input Select Register
Address
0xBF809040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CH0SB
29:24
Positive Input Select bits for Sample B
0 Channel 0 positive input is AN0
1 Channel 0 positive input is AN1
2 Channel 0 positive input is AN2
3 Channel 0 positive input is AN3
4 Channel 0 positive input is AN4
5 Channel 0 positive input is AN5
6 Channel 0 positive input is AN6
7 Channel 0 positive input is AN7
8 Channel 0 positive input is AN8
9 Channel 0 positive input is AN9
10 Channel 0 positive input is AN10
11 Channel 0 positive input is AN11
12 Channel 0 positive input is AN12
13 Channel 0 positive input is CTMU temperature sensor (CTMUT)
14 Channel 0 positive input is IVREF
15 Reserved
16 Reserved
17 Channel 0 positive input is VDD/2
18 Reserved
19 Reserved
20 Reserved
21 Reserved
22 Reserved
23 Reserved
24 Reserved
25 Reserved
26 Reserved
27 Reserved
28 Reserved
29 Reserved
30 Reserved
31 Reserved
CH0NA
23
Negative Input Select bit for Sample A Multiplexer Setting
0 Channel 0 negative input is VREFL
1 Channel 0 negative input is AN1
CH0SA
21:16
Positive Input Select bits for Sample A Multiplexer Setting
0 Channel 0 positive input is AN0
1 Channel 0 positive input is AN1
2 Channel 0 positive input is AN2
3 Channel 0 positive input is AN3
4 Channel 0 positive input is AN4
5 Channel 0 positive input is AN5
6 Channel 0 positive input is AN6
7 Channel 0 positive input is AN7
8 Channel 0 positive input is AN8
9 Channel 0 positive input is AN9
10 Channel 0 positive input is AN10
11 Channel 0 positive input is AN11
12 Channel 0 positive input is AN12
13 Channel 0 positive input is CTMU temperature sensor (CTMUT)
14 Channel 0 positive input is IVREF
15 Reserved
16 Reserved
17 Channel 0 positive input is VDD/2
18 Reserved
19 Reserved
20 Reserved
21 Reserved
22 Reserved
23 Reserved
24 Reserved
25 Reserved
26 Reserved
27 Reserved
28 Reserved
29 Reserved
30 Reserved
31 Reserved
CH0NB
31
Negative Input Select bit for Sample B
0 Channel 0 negative input is VREFL
1 Channel 0 negative input is AN1
AD1CSSLADC Input Scan Select Register
Address
0xBF809050
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CSSL17
17
ADC Input Pin Scan Selection bits
0 Skip VDD_DIV_2 for input scan; CSSL17 = VDD_DIV_2
1 Select VDD_DIV_2 for input scan; CSSL17 = VDD_DIV_2
CSSL15
15
ADC Input Pin Scan Selection bits
0 Skip AVSS for input scan; CSSL15 = AVSS
1 Select AVSS for input scan; CSSL15 = AVSS
CSSL14
14
ADC Input Pin Scan Selection bits
0 Skip IVREF for input scan; CSSL14 = IVREF
1 Select IVREF for input scan; CSSL14 = IVREF
CSSL13
13
ADC Input Pin Scan Selection bits
0 Skip CTMUT for input scan; CSSL13 = CTMUT
1 Select CTMUT for input scan; CSSL13 = CTMUT
CSSL11
11
ADC Input Pin Scan Selection bits
0 Skip AN11 for input scan; CSSL11 = AN11
1 Select AN11 for input scan; CSSL11 = AN11
CSSL10
10
ADC Input Pin Scan Selection bits
0 Skip AN10 for input scan; CSSL10 = AN10
1 Select AN10 for input scan; CSSL10 = AN10
CSSL9
9
ADC Input Pin Scan Selection bits
0 Skip AN9 for input scan; CSSL9 = AN9
1 Select AN9 for input scan; CSSL9 = AN9
CSSL8
8
ADC Input Pin Scan Selection bits
0 Skip AN8 for input scan; CSSL8 = AN8
1 Select AN8 for input scan; CSSL8 = AN8
CSSL7
7
ADC Input Pin Scan Selection bits
0 Skip AN7 for input scan; CSSL7 = AN7
1 Select AN7 for input scan; CSSL7 = AN7
CSSL6
6
ADC Input Pin Scan Selection bits
0 Skip AN6 for input scan; CSSL6 = AN6
1 Select AN6 for input scan; CSSL6 = AN6
CSSL5
5
ADC Input Pin Scan Selection bits
0 Skip AN5 for input scan; CSSL5 = AN5
1 Select AN5 for input scan; CSSL5 = AN5
CSSL4
4
ADC Input Pin Scan Selection bits
0 Skip AN4 for input scan; CSSL4 = AN4
1 Select AN4 for input scan; CSSL4 = AN4
CSSL3
3
ADC Input Pin Scan Selection bits
0 Skip AN3 for input scan; CSSL3 = AN3
1 Select AN3 for input scan; CSSL3 = AN3
CSSL2
2
ADC Input Pin Scan Selection bits
0 Skip AN2 for input scan; CSSL2 = AN2
1 Select AN2 for input scan; CSSL2 = AN2
CSSL1
1
ADC Input Pin Scan Selection bits
0 Skip AN1 for input scan; CSSL1 = AN1
1 Select AN1 for input scan; CSSL1 = AN1
CSSL0
0
ADC Input Pin Scan Selection bits
0 Skip AN0 for input scan; CSSL0 = AN0
1 Select AN0 for input scan; CSSL0 = AN0
ADC1BUF0
Address
0xBF809070
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF1
Address
0xBF809080
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF2
Address
0xBF809090
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF3
Address
0xBF8090A0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF4
Address
0xBF8090B0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF5
Address
0xBF8090C0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF6
Address
0xBF8090D0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF7
Address
0xBF8090E0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF8
Address
0xBF8090F0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF9
Address
0xBF809100
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFA
Address
0xBF809110
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFB
Address
0xBF809120
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFC
Address
0xBF809130
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFD
Address
0xBF809140
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFE
Address
0xBF809150
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFF
Address
0xBF809160
Reset
0x00000000
Access
read only
Size
32-bit
SFR Other special function registers
RESERVED1
Address
0xBF809030
Reset
0x00000000
Access
read/write
Size
32-bit
CVR Comparator voltage reference
CVRCONComparator Voltage Reference Control Register
Address
0xBF809800
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Comparator Voltage Reference On bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in the register.
1 Module is enabled. Setting this bit does not affect other bits in the register.
CVROE
6
CVrefout Enable bit
0 Voltage level is disconnected from CVrefout pin
1 Voltage level is output on CVrefout pin
CVRR
5
CVref Range Selection bit
0 0.25 CVrsrc to 0.75 CVrsrc with CVrsrc/32 step size
1 0 to 0.67 CVrsrc with CVrsrc/24 step size
CVRSS
4
CVref Source Selection bit
0 Comparator voltage reference source CVrsrc = AVdd - AVss
1 Comparator voltage reference source CVrsrc = (Vref+) - (Vref-)
CVR
3:0
CVref Value Selection
0 (When CVRR is 1) CVREF is (0/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (0/32)*CVRSRC
1 (When CVRR is 1) CVREF is (1/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (1/32)*CVRSRC
2 (When CVRR is 1) CVREF is (2/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (2/32)*CVRSRC
3 (When CVRR is 1) CVREF is (3/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (3/32)*CVRSRC
4 (When CVRR is 1) CVREF is (4/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (4/32)*CVRSRC
5 (When CVRR is 1) CVREF is (5/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (5/32)*CVRSRC
6 (When CVRR is 1) CVREF is (6/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (6/32)*CVRSRC
7 (When CVRR is 1) CVREF is (7/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (7/32)*CVRSRC
8 (When CVRR is 1) CVREF is (8/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (8/32)*CVRSRC
9 (When CVRR is 1) CVREF is (9/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (9/32)*CVRSRC
10 (When CVRR is 1) CVREF is (10/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (10/32)*CVRSRC
11 (When CVRR is 1) CVREF is (11/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (11/32)*CVRSRC
12 (When CVRR is 1) CVREF is (12/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (12/32)*CVRSRC
13 (When CVRR is 1) CVREF is (13/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (13/32)*CVRSRC
14 (When CVRR is 1) CVREF is (14/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (14/32)*CVRSRC
15 (When CVRR is 1) CVREF is (15/24) * CVRSRC / (When CVRR is 0) CVREF is CVRSRC/4 + (15/32)*CVRSRC
CMP1 Comparator 1
CM1CONComparator Control Register
Address
0xBF80A000
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ON
15
Comparator ON bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
1 Module is enabled. Setting this bit does not affect the other bits in this register
COE
14
Comparator Output Enable bit
0 Comparator output is not driven on the output CxOUT pin
1 Comparator output is driven on the output CxOUT pin
CPOL
13
Comparator Output Inversion bit
0 Output is not inverted
1 Output is inverted
COUT
8
Comparator Output bit
0 Output of the Comparator is a 0
1 Output of the Comparator is a 1
EVPOL
7:6
Interrupt Event Polarity Select bits
0 Comparator interrupt generation is disabled
1 Comparator interrupt is generated on a low-to-high transition of the comparator output
2 Comparator interrupt is generated on a high-to-low transition of the comparator output
3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF
4
Comparator Positive Input Configure bit
0 Comparator non-inverting input is connected to the CxINA pin
1 Comparator non-inverting input is connected to the internal CVref
CCH
1:0
Comparator Negative Input Select bits for Comparator
0 Comparator inverting input is connected to the CxINB pin
1 Comparator inverting input is connected to the CxINC pin
2 Comparator inverting input is connected to the CxIND pin
3 Comparator inverting input is connected to the IVREF
CMP2 Comparator 2
CM2CONComparator Control Register
Address
0xBF80A010
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ON
15
Comparator ON bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
1 Module is enabled. Setting this bit does not affect the other bits in this register
COE
14
Comparator Output Enable bit
0 Comparator output is not driven on the output CxOUT pin
1 Comparator output is driven on the output CxOUT pin
CPOL
13
Comparator Output Inversion bit
0 Output is not inverted
1 Output is inverted
COUT
8
Comparator Output bit
0 Output of the Comparator is a 0
1 Output of the Comparator is a 1
EVPOL
7:6
Interrupt Event Polarity Select bits
0 Comparator interrupt generation is disabled
1 Comparator interrupt is generated on a low-to-high transition of the comparator output
2 Comparator interrupt is generated on a high-to-low transition of the comparator output
3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF
4
Comparator Positive Input Configure bit
0 Comparator non-inverting input is connected to the CxINA pin
1 Comparator non-inverting input is connected to the internal CVref
CCH
1:0
Comparator Negative Input Select bits for Comparator
0 Comparator inverting input is connected to the CxINB pin
1 Comparator inverting input is connected to the CxINC pin
2 Comparator inverting input is connected to the CxIND pin
3 Comparator inverting input is connected to the IVREF
CMP3 Comparator 3
CM3CONComparator Control Register
Address
0xBF80A020
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ON
15
Comparator ON bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
1 Module is enabled. Setting this bit does not affect the other bits in this register
COE
14
Comparator Output Enable bit
0 Comparator output is not driven on the output CxOUT pin
1 Comparator output is driven on the output CxOUT pin
CPOL
13
Comparator Output Inversion bit
0 Output is not inverted
1 Output is inverted
COUT
8
Comparator Output bit
0 Output of the Comparator is a 0
1 Output of the Comparator is a 1
EVPOL
7:6
Interrupt Event Polarity Select bits
0 Comparator interrupt generation is disabled
1 Comparator interrupt is generated on a low-to-high transition of the comparator output
2 Comparator interrupt is generated on a high-to-low transition of the comparator output
3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF
4
Comparator Positive Input Configure bit
0 Comparator non-inverting input is connected to the CxINA pin
1 Comparator non-inverting input is connected to the internal CVref
CCH
1:0
Comparator Negative Input Select bits for Comparator
0 Comparator inverting input is connected to the CxINB pin
1 Comparator inverting input is connected to the CxINC pin
2 Comparator inverting input is connected to the CxIND pin
3 Comparator inverting input is connected to the IVREF
CMP Comparator
CMSTATComparator Status Register
Address
0xBF80A060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
SIDL
13
Stop in Idle Control bit
0 All Comparator modules continue to operate in the Idle mode
1 All Comparator modules are disabled in Idle mode
C3OUT
2
Comparator Output bit
0 Output of Comparator 3 is a 0
1 Output of Comparator 3 is a 1
C2OUT
1
Comparator Output bit
0 Output of Comparator 2 is a 0
1 Output of Comparator 2 is a 1
C1OUT
0
Comparator Output bit
0 Output of Comparator 1 is a 0
1 Output of Comparator 1 is a 1
CTMU Charge time measurement unit
CTMUCONCTMU Control Register
Address
0xBF80A200
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
Field
Bits
What it does
EDG1POL
30
Edge 1 Polarity Select bit
0 Edge1 programmed for a negative edge response
1 Edge1 programmed for a positive edge response
EDG1SEL
29:26
Edge 1 Source Select bits
0 Timer1 Event is selected
1 OC1 Compare Event is selected
2 CTED2 pin is selected
3 CTED1 pin is selected
4 CTED3 pin is selected
5 CTED4 pin is selected
6 CTED5 pin is selected
7 CTED6 pin is selected
8 CTED7 pin is selected
9 CTED8 pin is selected
10 IC1 Capture Event is selected
11 IC2 Capture Event is selected
12 IC3 Capture Event is selected
13 C1OUT pin is selected
14 C2OUT pin is selected
15 C3OUT pin is selected
EDG2STAT
25
Edge2 Status bit
0 Edge2 has not occurred
1 Edge2 has occurred
EDG1STAT
24
Edge1 Status bit
0 Edge1 has not occurred
1 Edge1 has occurred
EDG2MOD
23
Edge2 Edge Sampling Select bit
0 Input is level-sensitive
1 Input is edge-sensitive
EDG2POL
22
Edge 2 Polarity Select bit
0 Edge2 programmed for a negative edge response
1 Edge2 programmed for a positive edge response
EDG2SEL
21:18
Edge 2 Source Select bits
0 Timer1 Event is selected
1 OC1 Compare Event is selected
2 CTED2 pin is selected
3 CTED1 pin is selected
4 CTED9 pin is selected
5 CTED10 pin is selected
6 CTED11 pin is selected
7 CTED12 pin is selected
8 CTED13 pin is selected
9 IC1 Capture Event is selected
10 IC2 Capture Event is selected
11 IC3 Capture Event is selected
12 PBCLK clock is selected
13 C1OUT pin is selected
14 C2OUT pin is selected
15 C3OUT pin is selected
ON
15
ON Enable bit
0 Module is disabled
1 Module is enabled
CTMUSIDL
13
Stop-in-Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
TGEN
12
Time Generation Enable bit
0 Disables edge delay generation
1 Enables edge delay generation
EDGEN
11
Edge Enable bit
0 Edges are blocked
1 Edges are not blocked
EDGSEQEN
10
Edge Sequence Enable bit
0 No edge sequence is needed
1 Edge1 must occur before Edge2 can occur
IDISSEN
9
Analog Current Source Control bit
0 Analog current source output is not grounded
1 Analog current source output is grounded
CTTRIG
8
Trigger Control bit
0 Trigger output is disabled
1 Trigger output is enabled
ITRIM
7:2
Current Source Trim bits
0 Nominal current output specified by IRNG
1 Minimum positive change from nominal current
31 Maximum positive change from nominal current
33 Maximum negative change from nominal current
63 Minimum negative change from nominal current
IRNG
1:0
Current Range Select bits
0 1000 times base current(4)
1 Base current level
2 10 times base current
3 100 times base current
EDG1MOD
31
Edge1 Edge Sampling Select bit
0 Input is level-sensitive
1 Input is edge-sensitive
OSC Oscillator and clocks
OSCCONOscillator Control Register
Address
0xBF80F000
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FRCDIV
26:24
Internal Fast RC Oscillator Clock Divider bits
0 FRC divided by 1 (default setting)
1 FRC divided by 2
2 FRC divided by 4
3 FRC divided by 8
4 FRC divided by 16
5 FRC divided by 32
6 FRC divided by 64
7 FRC divided by 256
DRMEN
23
Dream Mode Enable bit
0 Dream mode is disabled
1 Dream mode is enabled
SLP2SPD
21
Sleep Two-speed Start-up Control bit
0 Use the selected clock directly
1 Use FRC as SYSCLK until the selected clock is ready
COSC
14:12
Current Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
1 System PLL (SPLL)
2 Primary Oscillator (POSC) (HS or EC)
3 Reserved
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Reserved
7 Reserved
NOSC
10:8
New Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
1 System PLL (SPLL)
2 Primary Oscillator (POSC) (HS or EC)
3 Reserved
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Reserved
7 Reserved
CLKLOCK
7
Clock Selection Lock Enable bit
0 Clock and PLL selections are not locked and may be modified
1 Clock and PLL selections are locked
SLPEN
4
Sleep Mode Enable bit
0 Device will enter Idle mode when a WAIT instruction is executed
1 Device will enter Sleep mode when a WAIT instruction is executed
CF
3
Clock Fail Detect bit
0 No clock failure has been detected
1 FSCM has detected a clock failure
UFRCEN
2
USB FRC Clock Enable bit
0 Use the Primary Oscillator or UPLL as the USB clock source
1 Enable FRC as the USB clock source
SOSCEN
1
Secondary Oscillator Enable bit
0 Disable Secondary Oscillator
1 Enable Secondary Oscillator
OSWEN
0
Oscillator Switch Enable bit
0 Oscillator switch is complete
1 Initiate an oscillator switch to selection specified by NOSC bits
OSCTUNFRC Tuning Register
Address
0xBF80F010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TUN
5:0
FRC Oscillator Tuning bits
0 Center frequency; Oscillator runs at nominal frequency (8 MHz)
31 Center frequency +2%
32 Center frequency -2%
SPLLCONSystem PLL Control Register
Address
0xBF80F020
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
PLLODIV
26:24
System PLL Output Clock Divider bits
0 PLL Divide by 1
1 PLL Divide by 2
2 PLL Divide by 4
3 PLL Divide by 8
4 PLL Divide by 16
5 PLL Divide by 32
6 PLL Divide by 64
7 PLL Divide by 256
PLLMULT
22:16
System PLL Multiplier bits
0 Multiply by 15
1 Multiply by 16
2 Multiply by 17
3 Multiply by 18
4 Multiply by 19
5 Multiply by 20
6 Multiply by 21
7 Multiply by 24
PLLIDIV
10:8
System PLL Input Clock Divider bits
0 Divide by 1
1 Divide by 2
2 Divide by 3
3 Divide by 4
4 Divide by 5
5 Divide by 6
6 Divide by 10
7 Divide by 12
PLLICLK
7
System PLL Input Clock Source bit
0 POSC is selected as the input to the System PLL
1 FRC is selected as the input to the System PLL
UPLLCONUSB PLL Control Register
Address
0xBF80F030
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PLLODIV
26:24
USB PLL Output Clock Divider bits
0 PLL Divide by 1
1 PLL Divide by 2
2 PLL Divide by 4
3 PLL Divide by 8
4 PLL Divide by 16
5 PLL Divide by 32
6 PLL Divide by 64
7 PLL Divide by 256
PLLMULT
22:16
USB PLL Multiplier bits
0 Multiply by 15
1 Multiply by 16
2 Multiply by 17
3 Multiply by 18
4 Multiply by 19
5 Multiply by 20
6 Multiply by 21
7 Multiply by 24
PLLIDIV
10:8
USB PLL Input Clock Divider bits
0 Divide by 1
1 Divide by 2
2 Divide by 3
3 Divide by 4
4 Divide by 5
5 Divide by 6
6 Divide by 10
7 Divide by 12
PB1DIVPeripheral Bus Clock Divisor Control Register
Address
0xBF80F100
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
Output Enable bit
0 PBCLK output clock is disabled
1 PBCLK output clock is enabled
PBDIVRDY
11
Peripheral Bus x Clock Divisor Ready bit
0 Clock divisor logic is currently switching values and the PBDIV bits cannot be written
1 Clock divisor logic is not switching divisors and the PBDIV bits may be written
PBDIV
6:0
Peripheral Bus Clock Divisor Control bits
0 PBCLK is SYSCLK divided by 1
1 PBCLK is SYSCLK divided by 2
2 PBCLK is SYSCLK divided by 3
3 PBCLK is SYSCLK divided by 4
4 PBCLK is SYSCLK divided by 5
5 PBCLK is SYSCLK divided by 6
6 PBCLK is SYSCLK divided by 7
7 PBCLK is SYSCLK divided by 8
8 PBCLK is SYSCLK divided by 9
9 PBCLK is SYSCLK divided by 10
10 PBCLK is SYSCLK divided by 11
11 PBCLK is SYSCLK divided by 12
12 PBCLK is SYSCLK divided by 13
13 PBCLK is SYSCLK divided by 14
14 PBCLK is SYSCLK divided by 15
15 PBCLK is SYSCLK divided by 16
16 PBCLK is SYSCLK divided by 17
17 PBCLK is SYSCLK divided by 18
18 PBCLK is SYSCLK divided by 19
19 PBCLK is SYSCLK divided by 20
20 PBCLK is SYSCLK divided by 21
21 PBCLK is SYSCLK divided by 22
22 PBCLK is SYSCLK divided by 23
23 PBCLK is SYSCLK divided by 24
24 PBCLK is SYSCLK divided by 25
25 PBCLK is SYSCLK divided by 26
26 PBCLK is SYSCLK divided by 27
27 PBCLK is SYSCLK divided by 28
28 PBCLK is SYSCLK divided by 29
29 PBCLK is SYSCLK divided by 30
30 PBCLK is SYSCLK divided by 31
31 PBCLK is SYSCLK divided by 32
32 PBCLK is SYSCLK divided by 33
33 PBCLK is SYSCLK divided by 34
34 PBCLK is SYSCLK divided by 35
35 PBCLK is SYSCLK divided by 36
36 PBCLK is SYSCLK divided by 37
37 PBCLK is SYSCLK divided by 38
38 PBCLK is SYSCLK divided by 39
39 PBCLK is SYSCLK divided by 40
40 PBCLK is SYSCLK divided by 41
41 PBCLK is SYSCLK divided by 42
42 PBCLK is SYSCLK divided by 43
43 PBCLK is SYSCLK divided by 44
44 PBCLK is SYSCLK divided by 45
45 PBCLK is SYSCLK divided by 46
46 PBCLK is SYSCLK divided by 47
47 PBCLK is SYSCLK divided by 48
48 PBCLK is SYSCLK divided by 49
49 PBCLK is SYSCLK divided by 50
50 PBCLK is SYSCLK divided by 51
51 PBCLK is SYSCLK divided by 52
52 PBCLK is SYSCLK divided by 53
53 PBCLK is SYSCLK divided by 54
54 PBCLK is SYSCLK divided by 55
55 PBCLK is SYSCLK divided by 56
56 PBCLK is SYSCLK divided by 57
57 PBCLK is SYSCLK divided by 58
58 PBCLK is SYSCLK divided by 59
59 PBCLK is SYSCLK divided by 60
60 PBCLK is SYSCLK divided by 61
61 PBCLK is SYSCLK divided by 62
62 PBCLK is SYSCLK divided by 63
63 PBCLK is SYSCLK divided by 64
64 PBCLK is SYSCLK divided by 65
65 PBCLK is SYSCLK divided by 66
66 PBCLK is SYSCLK divided by 67
67 PBCLK is SYSCLK divided by 68
68 PBCLK is SYSCLK divided by 69
69 PBCLK is SYSCLK divided by 70
70 PBCLK is SYSCLK divided by 71
71 PBCLK is SYSCLK divided by 72
72 PBCLK is SYSCLK divided by 73
73 PBCLK is SYSCLK divided by 74
74 PBCLK is SYSCLK divided by 75
75 PBCLK is SYSCLK divided by 76
76 PBCLK is SYSCLK divided by 77
77 PBCLK is SYSCLK divided by 78
78 PBCLK is SYSCLK divided by 79
79 PBCLK is SYSCLK divided by 80
80 PBCLK is SYSCLK divided by 81
81 PBCLK is SYSCLK divided by 82
82 PBCLK is SYSCLK divided by 83
83 PBCLK is SYSCLK divided by 84
84 PBCLK is SYSCLK divided by 85
85 PBCLK is SYSCLK divided by 86
86 PBCLK is SYSCLK divided by 87
87 PBCLK is SYSCLK divided by 88
88 PBCLK is SYSCLK divided by 89
89 PBCLK is SYSCLK divided by 90
90 PBCLK is SYSCLK divided by 91
91 PBCLK is SYSCLK divided by 92
92 PBCLK is SYSCLK divided by 93
93 PBCLK is SYSCLK divided by 94
94 PBCLK is SYSCLK divided by 95
95 PBCLK is SYSCLK divided by 96
96 PBCLK is SYSCLK divided by 97
97 PBCLK is SYSCLK divided by 98
98 PBCLK is SYSCLK divided by 99
99 PBCLK is SYSCLK divided by 100
100 PBCLK is SYSCLK divided by 101
101 PBCLK is SYSCLK divided by 102
102 PBCLK is SYSCLK divided by 103
103 PBCLK is SYSCLK divided by 104
104 PBCLK is SYSCLK divided by 105
105 PBCLK is SYSCLK divided by 106
106 PBCLK is SYSCLK divided by 107
107 PBCLK is SYSCLK divided by 108
108 PBCLK is SYSCLK divided by 109
109 PBCLK is SYSCLK divided by 110
110 PBCLK is SYSCLK divided by 111
111 PBCLK is SYSCLK divided by 112
112 PBCLK is SYSCLK divided by 113
113 PBCLK is SYSCLK divided by 114
114 PBCLK is SYSCLK divided by 115
115 PBCLK is SYSCLK divided by 116
116 PBCLK is SYSCLK divided by 117
117 PBCLK is SYSCLK divided by 118
118 PBCLK is SYSCLK divided by 119
119 PBCLK is SYSCLK divided by 120
120 PBCLK is SYSCLK divided by 121
121 PBCLK is SYSCLK divided by 122
122 PBCLK is SYSCLK divided by 123
123 PBCLK is SYSCLK divided by 124
124 PBCLK is SYSCLK divided by 125
125 PBCLK is SYSCLK divided by 126
126 PBCLK is SYSCLK divided by 127
127 PBCLK is SYSCLK divided by 128
CLKSTAT
Address
0xBF80F1D0
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
UPLLRDY
8
SPLLRDY
7
LPRCRDY
5
SOSCRDY
4
POSCRDY
2
SPDIVRDY
1
FRCRDY
0
RCON Reset control
RCONPeripheral Bus Clock Divisor Control Register
Address
0xBF80F040
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
BCFGERR
27
BCFGFAIL
26
VBPOR
17
VBPOR Mode Flag bit
0 A VBAT domain POR has not occurred
1 A VBAT domain POR has occurred
VBAT
16
VBAT Mode Flag bit
DPSLP
10
Deep Sleep Mode Flag bit
0 Deep Sleep mode has not occurred
1 Deep Sleep mode has occurred
CMR
9
Configuration Mismatch Reset Flag bit
0 A Configuration Mismatch Reset has not occurred
1 A Configuration Mismatch Reset has occurred
EXTR
7
External Reset (MCLR) Pin Flag bit
0 Master Clear (pin) Reset has not occurred
1 Master Clear (pin) Reset has occurred
SWR
6
Software Reset Flag bit
0 Software Reset was not executed
1 Software Reset was executed
WDTO
4
Watchdog Timer Time-out Flag bit
0 WDT Time-out has not occurred
1 WDT Time-out has occurred
SLEEP
3
Wake From Sleep Flag bit
0 Device was not in Sleep mode
1 Device was in Sleep mode
IDLE
2
Wake From Idle Flag bit
0 Device was not in Idle mode
1 Device was in Idle mode
BOR
1
Brown-out Reset Flag bit
0 Brown-out Reset has not occurred
1 Brown-out Reset has occurred
POR
0
Power-on Reset Flag bit
0 Power-on Reset has not occurred
1 Power-on Reset has occurred
RSWRST
Address
0xBF80F050
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
SWRST
0
RNMICONNon-maskable Interrupt (NMI) Control Register
Address
0xBF80F060
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
WDTO
24
Watchdog Timer Time-Out Flag bit
0 WDT Time-out has not occurred
1 WDT Time-out has occurred
SWNMI
23
Software NMI Trigger
GNMI
19
General NMI bit
HLVD
18
High/Low-Voltage Detect bit
CF
17
Clock Fail Detect bit
WDTS
16
Watchdog Timer Time-out in Sleep Mode Flag bit
NMICNT
15:0
NMI Reset Counter Value bits
PWRCONPower Control Register
Address
0xBF80F070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
VREGS
0
Voltage Regulator Stand-by Enable bit
REFO1 Reference clock output 1
REFO1CONReference Oscillator Control Register
Address
0xBF80F080
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RODIV
30:16
Reference Clock Divider Bits
0 No divider selected
1 REFO clock is Base clock frequency divided by 2
2 REFO clock is Base clock frequency divided by 4
3 REFO clock is Base clock frequency divided by 6
32767 REFO clock is Base clock frequency divided by 65534
ON
15
Output Enable bit
0 Reference Oscillator Module is disabled
1 Reference Oscillator Module is enabled
SIDL
13
Peripheral Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
OE
12
Reference Clock Output Enable bit
0 Reference clock is not driven out on REFCLKO pin
1 Reference clock is driven out on REFCLKO pin
RSLP
11
Reference Oscillator Module Run in Sleep bit
0 Reference Oscillator Module output is disabled in Sleep
1 Reference Oscillator Module output continues to run in Sleep
DIVSWEN
9
Divider Switch Enable bit
0 Divider switch is complete
1 Divider switch is in progress
ACTIVE
8
Reference Clock Request Status bit
0 Reference clock request is not active
1 Reference clock request is active
ROSEL
3:0
Reference Clock Source Select bits
0 SYSCLK
1 PBCLK
2 POSC
3 FRC
4 LPRC
5 SOSC
6 USB PLL output
7 System PLL output
8 REFCLKI
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
REFO1TRIMReference Oscillator Trim Register
Address
0xBF80F090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ROTRIM
31:23
Reference Oscillator Trim bits
0 0 divisor added to RODIV value
1 1/512 divisor added to RODIV value
2 2/512 divisor added to RODIV value
3 3/512 divisor added to RODIV value
4 4/512 divisor added to RODIV value
5 5/512 divisor added to RODIV value
6 6/512 divisor added to RODIV value
7 7/512 divisor added to RODIV value
8 8/512 divisor added to RODIV value
9 9/512 divisor added to RODIV value
10 10/512 divisor added to RODIV value
11 11/512 divisor added to RODIV value
12 12/512 divisor added to RODIV value
13 13/512 divisor added to RODIV value
14 14/512 divisor added to RODIV value
15 15/512 divisor added to RODIV value
16 16/512 divisor added to RODIV value
17 17/512 divisor added to RODIV value
18 18/512 divisor added to RODIV value
19 19/512 divisor added to RODIV value
20 20/512 divisor added to RODIV value
21 21/512 divisor added to RODIV value
22 22/512 divisor added to RODIV value
23 23/512 divisor added to RODIV value
24 24/512 divisor added to RODIV value
25 25/512 divisor added to RODIV value
26 26/512 divisor added to RODIV value
27 27/512 divisor added to RODIV value
28 28/512 divisor added to RODIV value
29 29/512 divisor added to RODIV value
30 30/512 divisor added to RODIV value
31 31/512 divisor added to RODIV value
32 32/512 divisor added to RODIV value
33 33/512 divisor added to RODIV value
34 34/512 divisor added to RODIV value
35 35/512 divisor added to RODIV value
36 36/512 divisor added to RODIV value
37 37/512 divisor added to RODIV value
38 38/512 divisor added to RODIV value
39 39/512 divisor added to RODIV value
40 40/512 divisor added to RODIV value
41 41/512 divisor added to RODIV value
42 42/512 divisor added to RODIV value
43 43/512 divisor added to RODIV value
44 44/512 divisor added to RODIV value
45 45/512 divisor added to RODIV value
46 46/512 divisor added to RODIV value
47 47/512 divisor added to RODIV value
48 48/512 divisor added to RODIV value
49 49/512 divisor added to RODIV value
50 50/512 divisor added to RODIV value
51 51/512 divisor added to RODIV value
52 52/512 divisor added to RODIV value
53 53/512 divisor added to RODIV value
54 54/512 divisor added to RODIV value
55 55/512 divisor added to RODIV value
56 56/512 divisor added to RODIV value
57 57/512 divisor added to RODIV value
58 58/512 divisor added to RODIV value
59 59/512 divisor added to RODIV value
60 60/512 divisor added to RODIV value
61 61/512 divisor added to RODIV value
62 62/512 divisor added to RODIV value
63 63/512 divisor added to RODIV value
64 64/512 divisor added to RODIV value
65 65/512 divisor added to RODIV value
66 66/512 divisor added to RODIV value
67 67/512 divisor added to RODIV value
68 68/512 divisor added to RODIV value
69 69/512 divisor added to RODIV value
70 70/512 divisor added to RODIV value
71 71/512 divisor added to RODIV value
72 72/512 divisor added to RODIV value
73 73/512 divisor added to RODIV value
74 74/512 divisor added to RODIV value
75 75/512 divisor added to RODIV value
76 76/512 divisor added to RODIV value
77 77/512 divisor added to RODIV value
78 78/512 divisor added to RODIV value
79 79/512 divisor added to RODIV value
80 80/512 divisor added to RODIV value
81 81/512 divisor added to RODIV value
82 82/512 divisor added to RODIV value
83 83/512 divisor added to RODIV value
84 84/512 divisor added to RODIV value
85 85/512 divisor added to RODIV value
86 86/512 divisor added to RODIV value
87 87/512 divisor added to RODIV value
88 88/512 divisor added to RODIV value
89 89/512 divisor added to RODIV value
90 90/512 divisor added to RODIV value
91 91/512 divisor added to RODIV value
92 92/512 divisor added to RODIV value
93 93/512 divisor added to RODIV value
94 94/512 divisor added to RODIV value
95 95/512 divisor added to RODIV value
96 96/512 divisor added to RODIV value
97 97/512 divisor added to RODIV value
98 98/512 divisor added to RODIV value
99 99/512 divisor added to RODIV value
100 100/512 divisor added to RODIV value
101 101/512 divisor added to RODIV value
102 102/512 divisor added to RODIV value
103 103/512 divisor added to RODIV value
104 104/512 divisor added to RODIV value
105 105/512 divisor added to RODIV value
106 106/512 divisor added to RODIV value
107 107/512 divisor added to RODIV value
108 108/512 divisor added to RODIV value
109 109/512 divisor added to RODIV value
110 110/512 divisor added to RODIV value
111 111/512 divisor added to RODIV value
112 112/512 divisor added to RODIV value
113 113/512 divisor added to RODIV value
114 114/512 divisor added to RODIV value
115 115/512 divisor added to RODIV value
116 116/512 divisor added to RODIV value
117 117/512 divisor added to RODIV value
118 118/512 divisor added to RODIV value
119 119/512 divisor added to RODIV value
120 120/512 divisor added to RODIV value
121 121/512 divisor added to RODIV value
122 122/512 divisor added to RODIV value
123 123/512 divisor added to RODIV value
124 124/512 divisor added to RODIV value
125 125/512 divisor added to RODIV value
126 126/512 divisor added to RODIV value
127 127/512 divisor added to RODIV value
128 128/512 divisor added to RODIV value
129 129/512 divisor added to RODIV value
130 130/512 divisor added to RODIV value
131 131/512 divisor added to RODIV value
132 132/512 divisor added to RODIV value
133 133/512 divisor added to RODIV value
134 134/512 divisor added to RODIV value
135 135/512 divisor added to RODIV value
136 136/512 divisor added to RODIV value
137 137/512 divisor added to RODIV value
138 138/512 divisor added to RODIV value
139 139/512 divisor added to RODIV value
140 140/512 divisor added to RODIV value
141 141/512 divisor added to RODIV value
142 142/512 divisor added to RODIV value
143 143/512 divisor added to RODIV value
144 144/512 divisor added to RODIV value
145 145/512 divisor added to RODIV value
146 146/512 divisor added to RODIV value
147 147/512 divisor added to RODIV value
148 148/512 divisor added to RODIV value
149 149/512 divisor added to RODIV value
150 150/512 divisor added to RODIV value
151 151/512 divisor added to RODIV value
152 152/512 divisor added to RODIV value
153 153/512 divisor added to RODIV value
154 154/512 divisor added to RODIV value
155 155/512 divisor added to RODIV value
156 156/512 divisor added to RODIV value
157 157/512 divisor added to RODIV value
158 158/512 divisor added to RODIV value
159 159/512 divisor added to RODIV value
160 160/512 divisor added to RODIV value
161 161/512 divisor added to RODIV value
162 162/512 divisor added to RODIV value
163 163/512 divisor added to RODIV value
164 164/512 divisor added to RODIV value
165 165/512 divisor added to RODIV value
166 166/512 divisor added to RODIV value
167 167/512 divisor added to RODIV value
168 168/512 divisor added to RODIV value
169 169/512 divisor added to RODIV value
170 170/512 divisor added to RODIV value
171 171/512 divisor added to RODIV value
172 172/512 divisor added to RODIV value
173 173/512 divisor added to RODIV value
174 174/512 divisor added to RODIV value
175 175/512 divisor added to RODIV value
176 176/512 divisor added to RODIV value
177 177/512 divisor added to RODIV value
178 178/512 divisor added to RODIV value
179 179/512 divisor added to RODIV value
180 180/512 divisor added to RODIV value
181 181/512 divisor added to RODIV value
182 182/512 divisor added to RODIV value
183 183/512 divisor added to RODIV value
184 184/512 divisor added to RODIV value
185 185/512 divisor added to RODIV value
186 186/512 divisor added to RODIV value
187 187/512 divisor added to RODIV value
188 188/512 divisor added to RODIV value
189 189/512 divisor added to RODIV value
190 190/512 divisor added to RODIV value
191 191/512 divisor added to RODIV value
192 192/512 divisor added to RODIV value
193 193/512 divisor added to RODIV value
194 194/512 divisor added to RODIV value
195 195/512 divisor added to RODIV value
196 196/512 divisor added to RODIV value
197 197/512 divisor added to RODIV value
198 198/512 divisor added to RODIV value
199 199/512 divisor added to RODIV value
200 200/512 divisor added to RODIV value
201 201/512 divisor added to RODIV value
202 202/512 divisor added to RODIV value
203 203/512 divisor added to RODIV value
204 204/512 divisor added to RODIV value
205 205/512 divisor added to RODIV value
206 206/512 divisor added to RODIV value
207 207/512 divisor added to RODIV value
208 208/512 divisor added to RODIV value
209 209/512 divisor added to RODIV value
210 210/512 divisor added to RODIV value
211 211/512 divisor added to RODIV value
212 212/512 divisor added to RODIV value
213 213/512 divisor added to RODIV value
214 214/512 divisor added to RODIV value
215 215/512 divisor added to RODIV value
216 216/512 divisor added to RODIV value
217 217/512 divisor added to RODIV value
218 218/512 divisor added to RODIV value
219 219/512 divisor added to RODIV value
220 220/512 divisor added to RODIV value
221 221/512 divisor added to RODIV value
222 222/512 divisor added to RODIV value
223 223/512 divisor added to RODIV value
224 224/512 divisor added to RODIV value
225 225/512 divisor added to RODIV value
226 226/512 divisor added to RODIV value
227 227/512 divisor added to RODIV value
228 228/512 divisor added to RODIV value
229 229/512 divisor added to RODIV value
230 230/512 divisor added to RODIV value
231 231/512 divisor added to RODIV value
232 232/512 divisor added to RODIV value
233 233/512 divisor added to RODIV value
234 234/512 divisor added to RODIV value
235 235/512 divisor added to RODIV value
236 236/512 divisor added to RODIV value
237 237/512 divisor added to RODIV value
238 238/512 divisor added to RODIV value
239 239/512 divisor added to RODIV value
240 240/512 divisor added to RODIV value
241 241/512 divisor added to RODIV value
242 242/512 divisor added to RODIV value
243 243/512 divisor added to RODIV value
244 244/512 divisor added to RODIV value
245 245/512 divisor added to RODIV value
246 246/512 divisor added to RODIV value
247 247/512 divisor added to RODIV value
248 248/512 divisor added to RODIV value
249 249/512 divisor added to RODIV value
250 250/512 divisor added to RODIV value
251 251/512 divisor added to RODIV value
252 252/512 divisor added to RODIV value
253 253/512 divisor added to RODIV value
254 254/512 divisor added to RODIV value
255 255/512 divisor added to RODIV value
256 256/512 divisor added to RODIV value
257 257/512 divisor added to RODIV value
258 258/512 divisor added to RODIV value
259 259/512 divisor added to RODIV value
260 260/512 divisor added to RODIV value
261 261/512 divisor added to RODIV value
262 262/512 divisor added to RODIV value
263 263/512 divisor added to RODIV value
264 264/512 divisor added to RODIV value
265 265/512 divisor added to RODIV value
266 266/512 divisor added to RODIV value
267 267/512 divisor added to RODIV value
268 268/512 divisor added to RODIV value
269 269/512 divisor added to RODIV value
270 270/512 divisor added to RODIV value
271 271/512 divisor added to RODIV value
272 272/512 divisor added to RODIV value
273 273/512 divisor added to RODIV value
274 274/512 divisor added to RODIV value
275 275/512 divisor added to RODIV value
276 276/512 divisor added to RODIV value
277 277/512 divisor added to RODIV value
278 278/512 divisor added to RODIV value
279 279/512 divisor added to RODIV value
280 280/512 divisor added to RODIV value
281 281/512 divisor added to RODIV value
282 282/512 divisor added to RODIV value
283 283/512 divisor added to RODIV value
284 284/512 divisor added to RODIV value
285 285/512 divisor added to RODIV value
286 286/512 divisor added to RODIV value
287 287/512 divisor added to RODIV value
288 288/512 divisor added to RODIV value
289 289/512 divisor added to RODIV value
290 290/512 divisor added to RODIV value
291 291/512 divisor added to RODIV value
292 292/512 divisor added to RODIV value
293 293/512 divisor added to RODIV value
294 294/512 divisor added to RODIV value
295 295/512 divisor added to RODIV value
296 296/512 divisor added to RODIV value
297 297/512 divisor added to RODIV value
298 298/512 divisor added to RODIV value
299 299/512 divisor added to RODIV value
300 300/512 divisor added to RODIV value
301 301/512 divisor added to RODIV value
302 302/512 divisor added to RODIV value
303 303/512 divisor added to RODIV value
304 304/512 divisor added to RODIV value
305 305/512 divisor added to RODIV value
306 306/512 divisor added to RODIV value
307 307/512 divisor added to RODIV value
308 308/512 divisor added to RODIV value
309 309/512 divisor added to RODIV value
310 310/512 divisor added to RODIV value
311 311/512 divisor added to RODIV value
312 312/512 divisor added to RODIV value
313 313/512 divisor added to RODIV value
314 314/512 divisor added to RODIV value
315 315/512 divisor added to RODIV value
316 316/512 divisor added to RODIV value
317 317/512 divisor added to RODIV value
318 318/512 divisor added to RODIV value
319 319/512 divisor added to RODIV value
320 320/512 divisor added to RODIV value
321 321/512 divisor added to RODIV value
322 322/512 divisor added to RODIV value
323 323/512 divisor added to RODIV value
324 324/512 divisor added to RODIV value
325 325/512 divisor added to RODIV value
326 326/512 divisor added to RODIV value
327 327/512 divisor added to RODIV value
328 328/512 divisor added to RODIV value
329 329/512 divisor added to RODIV value
330 330/512 divisor added to RODIV value
331 331/512 divisor added to RODIV value
332 332/512 divisor added to RODIV value
333 333/512 divisor added to RODIV value
334 334/512 divisor added to RODIV value
335 335/512 divisor added to RODIV value
336 336/512 divisor added to RODIV value
337 337/512 divisor added to RODIV value
338 338/512 divisor added to RODIV value
339 339/512 divisor added to RODIV value
340 340/512 divisor added to RODIV value
341 341/512 divisor added to RODIV value
342 342/512 divisor added to RODIV value
343 343/512 divisor added to RODIV value
344 344/512 divisor added to RODIV value
345 345/512 divisor added to RODIV value
346 346/512 divisor added to RODIV value
347 347/512 divisor added to RODIV value
348 348/512 divisor added to RODIV value
349 349/512 divisor added to RODIV value
350 350/512 divisor added to RODIV value
351 351/512 divisor added to RODIV value
352 352/512 divisor added to RODIV value
353 353/512 divisor added to RODIV value
354 354/512 divisor added to RODIV value
355 355/512 divisor added to RODIV value
356 356/512 divisor added to RODIV value
357 357/512 divisor added to RODIV value
358 358/512 divisor added to RODIV value
359 359/512 divisor added to RODIV value
360 360/512 divisor added to RODIV value
361 361/512 divisor added to RODIV value
362 362/512 divisor added to RODIV value
363 363/512 divisor added to RODIV value
364 364/512 divisor added to RODIV value
365 365/512 divisor added to RODIV value
366 366/512 divisor added to RODIV value
367 367/512 divisor added to RODIV value
368 368/512 divisor added to RODIV value
369 369/512 divisor added to RODIV value
370 370/512 divisor added to RODIV value
371 371/512 divisor added to RODIV value
372 372/512 divisor added to RODIV value
373 373/512 divisor added to RODIV value
374 374/512 divisor added to RODIV value
375 375/512 divisor added to RODIV value
376 376/512 divisor added to RODIV value
377 377/512 divisor added to RODIV value
378 378/512 divisor added to RODIV value
379 379/512 divisor added to RODIV value
380 380/512 divisor added to RODIV value
381 381/512 divisor added to RODIV value
382 382/512 divisor added to RODIV value
383 383/512 divisor added to RODIV value
384 384/512 divisor added to RODIV value
385 385/512 divisor added to RODIV value
386 386/512 divisor added to RODIV value
387 387/512 divisor added to RODIV value
388 388/512 divisor added to RODIV value
389 389/512 divisor added to RODIV value
390 390/512 divisor added to RODIV value
391 391/512 divisor added to RODIV value
392 392/512 divisor added to RODIV value
393 393/512 divisor added to RODIV value
394 394/512 divisor added to RODIV value
395 395/512 divisor added to RODIV value
396 396/512 divisor added to RODIV value
397 397/512 divisor added to RODIV value
398 398/512 divisor added to RODIV value
399 399/512 divisor added to RODIV value
400 400/512 divisor added to RODIV value
401 401/512 divisor added to RODIV value
402 402/512 divisor added to RODIV value
403 403/512 divisor added to RODIV value
404 404/512 divisor added to RODIV value
405 405/512 divisor added to RODIV value
406 406/512 divisor added to RODIV value
407 407/512 divisor added to RODIV value
408 408/512 divisor added to RODIV value
409 409/512 divisor added to RODIV value
410 410/512 divisor added to RODIV value
411 411/512 divisor added to RODIV value
412 412/512 divisor added to RODIV value
413 413/512 divisor added to RODIV value
414 414/512 divisor added to RODIV value
415 415/512 divisor added to RODIV value
416 416/512 divisor added to RODIV value
417 417/512 divisor added to RODIV value
418 418/512 divisor added to RODIV value
419 419/512 divisor added to RODIV value
420 420/512 divisor added to RODIV value
421 421/512 divisor added to RODIV value
422 422/512 divisor added to RODIV value
423 423/512 divisor added to RODIV value
424 424/512 divisor added to RODIV value
425 425/512 divisor added to RODIV value
426 426/512 divisor added to RODIV value
427 427/512 divisor added to RODIV value
428 428/512 divisor added to RODIV value
429 429/512 divisor added to RODIV value
430 430/512 divisor added to RODIV value
431 431/512 divisor added to RODIV value
432 432/512 divisor added to RODIV value
433 433/512 divisor added to RODIV value
434 434/512 divisor added to RODIV value
435 435/512 divisor added to RODIV value
436 436/512 divisor added to RODIV value
437 437/512 divisor added to RODIV value
438 438/512 divisor added to RODIV value
439 439/512 divisor added to RODIV value
440 440/512 divisor added to RODIV value
441 441/512 divisor added to RODIV value
442 442/512 divisor added to RODIV value
443 443/512 divisor added to RODIV value
444 444/512 divisor added to RODIV value
445 445/512 divisor added to RODIV value
446 446/512 divisor added to RODIV value
447 447/512 divisor added to RODIV value
448 448/512 divisor added to RODIV value
449 449/512 divisor added to RODIV value
450 450/512 divisor added to RODIV value
451 451/512 divisor added to RODIV value
452 452/512 divisor added to RODIV value
453 453/512 divisor added to RODIV value
454 454/512 divisor added to RODIV value
455 455/512 divisor added to RODIV value
456 456/512 divisor added to RODIV value
457 457/512 divisor added to RODIV value
458 458/512 divisor added to RODIV value
459 459/512 divisor added to RODIV value
460 460/512 divisor added to RODIV value
461 461/512 divisor added to RODIV value
462 462/512 divisor added to RODIV value
463 463/512 divisor added to RODIV value
464 464/512 divisor added to RODIV value
465 465/512 divisor added to RODIV value
466 466/512 divisor added to RODIV value
467 467/512 divisor added to RODIV value
468 468/512 divisor added to RODIV value
469 469/512 divisor added to RODIV value
470 470/512 divisor added to RODIV value
471 471/512 divisor added to RODIV value
472 472/512 divisor added to RODIV value
473 473/512 divisor added to RODIV value
474 474/512 divisor added to RODIV value
475 475/512 divisor added to RODIV value
476 476/512 divisor added to RODIV value
477 477/512 divisor added to RODIV value
478 478/512 divisor added to RODIV value
479 479/512 divisor added to RODIV value
480 480/512 divisor added to RODIV value
481 481/512 divisor added to RODIV value
482 482/512 divisor added to RODIV value
483 483/512 divisor added to RODIV value
484 484/512 divisor added to RODIV value
485 485/512 divisor added to RODIV value
486 486/512 divisor added to RODIV value
487 487/512 divisor added to RODIV value
488 488/512 divisor added to RODIV value
489 489/512 divisor added to RODIV value
490 490/512 divisor added to RODIV value
491 491/512 divisor added to RODIV value
492 492/512 divisor added to RODIV value
493 493/512 divisor added to RODIV value
494 494/512 divisor added to RODIV value
495 495/512 divisor added to RODIV value
496 496/512 divisor added to RODIV value
497 497/512 divisor added to RODIV value
498 498/512 divisor added to RODIV value
499 499/512 divisor added to RODIV value
500 500/512 divisor added to RODIV value
501 501/512 divisor added to RODIV value
502 502/512 divisor added to RODIV value
503 503/512 divisor added to RODIV value
504 504/512 divisor added to RODIV value
505 505/512 divisor added to RODIV value
506 506/512 divisor added to RODIV value
507 507/512 divisor added to RODIV value
508 508/512 divisor added to RODIV value
509 509/512 divisor added to RODIV value
510 510/512 divisor added to RODIV value
511 511/512 divisor added to RODIV value
CFG Configuration and pin control
CFGCONConfiguration Control Register
Address
0xBF80F200
Reset
0x00000008
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
IOLOCK
13
Peripheral Pin Select Lock bit
0 Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
1 Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
PMDLOCK
12
Peripheral Module Disable bit
0 Peripheral module is not locked. Writes to PMD registers is allowed.
1 Peripheral module is locked. Writes to PMD registers is not allowed.
1 Initiate a Flash operation. Hardware clears this bit when the operation completes
WREN
14
Write Enable bit
0 Disable writes to WR bit and disables HLVD circuit
1 Enable writes to WR bit and enables HLVD circuit
WRERR
13
Write Error bit (LVD circuit must be enabled)
0 Program or erase sequence completed normally
1 Program or erase sequence did not complete successfully
LVDERR
12
Low-Voltage Detect Error bit (LVD circuit must be enabled)
0 Voltage level is acceptable for programming
1 Low-voltage detected (possible data corruption
LVDSTAT
11
Low-Voltage Detect Status bit (LVD circuit must be enabled)
0 Low-voltage event is not active
1 Low-voltage event is active
NVMOP
3:0
NVM Operation bits
0 No operation
1 Word program operation: programs word selected by NVMADDR
2 No operation
3 Row program operation: programs row selected by NVMADDR
4 Page erase operation: erases page selected by NVMADDR
5 Program Flash Memory (PFM) erase operation: erases PFM
6 No operation
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
NVMKEYProgramming Unlock Register
Address
0xBF80F410
Reset
0x00000000
Access
write only
Size
32-bit
NVMADDRFlash Address Register
Address
0xBF80F420
Reset
0x00000000
Access
read/write
Size
32-bit
NVMDATAFlash Program Data Register
Address
0xBF80F430
Reset
0x00000000
Access
read/write
Size
32-bit
NVMSRCADDRSource Data Address Register
Address
0xBF80F440
Reset
0x00000000
Access
read/write
Size
32-bit
WDT Watchdog timer
WDTCONWatchdog Timer Control Register
Address
0xBF80F600
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ON
15
Watchdog Timer Enable bit
0 The WDT module is disabled
1 The WDT module is enabled
RUNDIV
12:8
WDTWINEN
0
Watchdog Timer Window Enable bit
0 Disable windowed Watchdog Timer
1 Enable windowed Watchdog Timer
WDTCLRKEY
31:16
PPS Peripheral pin select
INT1R
Address
0xBF80FA04
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
INT1R
3:0
INT2R
Address
0xBF80FA08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
INT2R
3:0
INT3R
Address
0xBF80FA0C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
INT3R
3:0
INT4R
Address
0xBF80FA10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
INT4R
3:0
T2CKR
Address
0xBF80FA18
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
T2CKR
3:0
T3CKR
Address
0xBF80FA1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
T3CKR
3:0
T4CKR
Address
0xBF80FA20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
T4CKR
3:0
T5CKR
Address
0xBF80FA24
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
T5CKR
3:0
IC1R
Address
0xBF80FA28
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
IC1R
3:0
IC2R
Address
0xBF80FA2C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
IC2R
3:0
IC3R
Address
0xBF80FA30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
IC3R
3:0
IC4R
Address
0xBF80FA34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
IC4R
3:0
IC5R
Address
0xBF80FA38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
IC5R
3:0
OCFAR
Address
0xBF80FA48
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
OCFAR
3:0
OCFBR
Address
0xBF80FA4C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
OCFBR
3:0
U1RXR
Address
0xBF80FA50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
U1RXR
3:0
U1CTSR
Address
0xBF80FA54
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
U1CTSR
3:0
U2RXR
Address
0xBF80FA58
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
U2RXR
3:0
U2CTSR
Address
0xBF80FA5C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
U2CTSR
3:0
SDI1R
Address
0xBF80FA84
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SDI1R
3:0
SS1R
Address
0xBF80FA88
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SS1R
3:0
SDI2R
Address
0xBF80FA90
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SDI2R
3:0
SS2R
Address
0xBF80FA94
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SS2R
3:0
REFCLKIR
Address
0xBF80FAB8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
REFCLKIR
3:0
RPA0R
Address
0xBF80FB00
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA0R
3:0
RPA1R
Address
0xBF80FB04
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA1R
3:0
RPA2R
Address
0xBF80FB08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA2R
3:0
RPA3R
Address
0xBF80FB0C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA3R
3:0
RPA4R
Address
0xBF80FB10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA4R
3:0
RPA8R
Address
0xBF80FB20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA8R
3:0
RPA9R
Address
0xBF80FB24
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPA9R
3:0
RPB0R
Address
0xBF80FB2C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB0R
3:0
RPB1R
Address
0xBF80FB30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB1R
3:0
RPB2R
Address
0xBF80FB34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB2R
3:0
RPB3R
Address
0xBF80FB38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB3R
3:0
RPB4R
Address
0xBF80FB3C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB4R
3:0
RPB5R
Address
0xBF80FB40
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB5R
3:0
RPB6R
Address
0xBF80FB44
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB6R
3:0
RPB7R
Address
0xBF80FB48
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB7R
3:0
RPB8R
Address
0xBF80FB4C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB8R
3:0
RPB9R
Address
0xBF80FB50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB9R
3:0
RPB10R
Address
0xBF80FB54
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB10R
3:0
RPB11R
Address
0xBF80FB58
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB11R
3:0
RPB13R
Address
0xBF80FB60
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB13R
3:0
RPB14R
Address
0xBF80FB64
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB14R
3:0
RPB15R
Address
0xBF80FB68
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPB15R
3:0
RPC0R
Address
0xBF80FB6C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC0R
3:0
RPC1R
Address
0xBF80FB70
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC1R
3:0
RPC2R
Address
0xBF80FB74
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC2R
3:0
RPC3R
Address
0xBF80FB78
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC3R
3:0
RPC4R
Address
0xBF80FB7C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC4R
3:0
RPC5R
Address
0xBF80FB80
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC5R
3:0
RPC6R
Address
0xBF80FB84
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC6R
3:0
RPC7R
Address
0xBF80FB88
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC7R
3:0
RPC8R
Address
0xBF80FB8C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC8R
3:0
RPC9R
Address
0xBF80FB90
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RPC9R
3:0
HLVD High/low-voltage detect
HLVDCONHigh/Low-Voltage Detect Control Register
Address
0xBF80FC00
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ON
15
HLVD Module Enable bit
0 HLVD module is enabled
0 HLVD module is disabled
SIDL
13
VDIR
11
Voltage Change Direction Select bit
0 Event occurs when voltage equals or falls below the trip point (HLVDL)
1 Event occurs when voltage equals or exceeds the trip point (HLVDL)
BGVST
10
Band Gap Reference Voltages Stable Status bit
0 Indicates internal band gap voltage reference is not stable
1 Indicates internal band gap voltage references is stable
HLEVT
8
HLVDL
3:0
High/Low-Voltage Detection Limit Select bits
0 Reserved; do not use
1 Reserved; do not use
2 Reserved; do not use
3 Reserved; do not use
4 Selects Trip Point 3.59V (Typ.)
5 Selects Trip Point 3.44V (Typ.)
6 Selects Trip Point 3.13V (Typ.)
7 Selects Trip Point 2.92V (Typ.)
8 Selects Trip Point 2.81V (Typ.)
9 Selects Trip Point 2.60V (Typ.)
10 Selects Trip Point 2.50V (Typ.)
11 Reserved; do not use
12 Reserved; do not use
13 Reserved; do not use
14 Reserved; do not use
15 External LVDIN pin
INT Interrupt controller
INTCONInterrupt Control Register
Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SS0
16
MVEC
12
Multi Vector Configuration bit
0 Interrupt controller configured for Single-vectored mode
1 Interrupt controller configured for Multi-vectored mode
TPC
10:8
Interrupt Proximity Timer Control bits
0 Disables Interrupt Proximity timer
1 Interrupts of group priority 1 start the Interrupt Proximity timer
2 Interrupts of group priority 2 or lower start the Interrupt Proximity timer
3 Interrupts of group priority 3 or lower start the Interrupt Proximity timer
4 Interrupts of group priority 4 or lower start the Interrupt Proximity timer
5 Interrupts of group priority 5 or lower start the Interrupt Proximity timer
6 Interrupts of group priority 6 or lower start the Interrupt Proximity timer
7 Interrupts of group priority 7 or lower start the Interrupt Proximity timer
INT4EP
4
External Interrupt 4 Edge
0 Falling edge
1 Rising edge
INT3EP
3
External Interrupt 3 Edge
0 Falling edge
1 Rising edge
INT2EP
2
External Interrupt 2 Edge
0 Falling edge
1 Rising edge
INT1EP
1
External Interrupt 1 Edge
0 Falling edge
1 Rising edge
INT0EP
0
External Interrupt 0 Edge
0 Falling edge
1 Rising edge
INTSTATInterrupt Status Register
Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
SRIPL
10:8
VEC
5:0
IPTMRInterrupt Proximity Timer Register
Address
0xBF881020
Reset
0x00000000
Access
read/write
Size
32-bit
IFS0Interrupt Flag Status Register
Address
0xBF881030
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
RTCCIF
30
FSCMIF
29
AD1IF
28
OC5IF
27
IC5IF
26
IC5EIF
25
T5IF
24
INT4IF
23
OC4IF
22
IC4IF
21
IC4EIF
20
T4IF
19
INT3IF
18
OC3IF
17
IC3IF
16
IC3EIF
15
T3IF
14
INT2IF
13
OC2IF
12
IC2IF
11
IC2EIF
10
T2IF
9
INT1IF
8
OC1IF
7
IC1IF
6
IC1EIF
5
T1IF
4
INT0IF
3
CS1IF
2
CS0IF
1
CTIF
0
FCEIF
31
IFS1Interrupt Flag Status Register
Address
0xBF881040
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
DMA2IF
30
DMA1IF
29
DMA0IF
28
CTMUIF
27
I2C2MIF
26
I2C2SIF
25
I2C2BIF
24
U2TXIF
23
U2RXIF
22
U2EIF
21
SPI2TXIF
20
SPI2RXIF
19
SPI2EIF
18
PMPEIF
17
PMPIF
16
CNCIF
15
CNBIF
14
CNAIF
13
I2C1MIF
12
I2C1SIF
11
I2C1BIF
10
U1TXIF
9
U1RXIF
8
U1EIF
7
SPI1TXIF
6
SPI1RXIF
5
SPI1EIF
4
USBIF
3
CMP3IF
2
CMP2IF
1
CMP1IF
0
DMA3IF
31
IEC0Interrupt Enable Control Register
Address
0xBF881060
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
RTCCIE
30
FSCMIE
29
AD1IE
28
OC5IE
27
IC5IE
26
IC5EIE
25
T5IE
24
INT4IE
23
OC4IE
22
IC4IE
21
IC4EIE
20
T4IE
19
INT3IE
18
OC3IE
17
IC3IE
16
IC3EIE
15
T3IE
14
INT2IE
13
OC2IE
12
IC2IE
11
IC2EIE
10
T2IE
9
INT1IE
8
OC1IE
7
IC1IE
6
IC1EIE
5
T1IE
4
INT0IE
3
CS1IE
2
CS0IE
1
CTIE
0
FCEIE
31
IEC1Interrupt Enable Control Register
Address
0xBF881070
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
DMA2IE
30
DMA1IE
29
DMA0IE
28
CTMUIE
27
I2C2MIE
26
I2C2SIE
25
I2C2BIE
24
U2TXIE
23
U2RXIE
22
U2EIE
21
SPI2TXIE
20
SPI2RXIE
19
SPI2EIE
18
PMPEIE
17
PMPIE
16
CNCIE
15
CNBIE
14
CNAIE
13
I2C1MIE
12
I2C1SIE
11
I2C1BIE
10
U1TXIE
9
U1RXIE
8
U1EIE
7
SPI1TXIE
6
SPI1RXIE
5
SPI1EIE
4
USBIE
3
CMP3IE
2
CMP2IE
1
CMP1IE
0
DMA3IE
31
IPC0Interrupt Priority Control Register
Address
0xBF881090
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT0IP
28:26
INT0IS
25:24
CS1IP
20:18
CS1IS
17:16
CS0IP
12:10
CS0IS
9:8
CTIP
4:2
CTIS
1:0
IPC1Interrupt Priority Control Register
Address
0xBF8810A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT1IP
28:26
INT1IS
25:24
OC1IP
20:18
OC1IS
17:16
IC1IP
12:10
IC1IS
9:8
T1IP
4:2
T1IS
1:0
IPC2Interrupt Priority Control Register
Address
0xBF8810B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT2IP
28:26
INT2IS
25:24
OC2IP
20:18
OC2IS
17:16
IC2IP
12:10
IC2IS
9:8
T2IP
4:2
T2IS
1:0
IPC3Interrupt Priority Control Register
Address
0xBF8810C0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT3IP
28:26
INT3IS
25:24
OC3IP
20:18
OC3IS
17:16
IC3IP
12:10
IC3IS
9:8
T3IP
4:2
T3IS
1:0
IPC4Interrupt Priority Control Register
Address
0xBF8810D0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT4IP
28:26
INT4IS
25:24
OC4IP
20:18
OC4IS
17:16
IC4IP
12:10
IC4IS
9:8
T4IP
4:2
T4IS
1:0
IPC5Interrupt Priority Control Register
Address
0xBF8810E0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
AD1IP
28:26
AD1IS
25:24
OC5IP
20:18
OC5IS
17:16
IC5IP
12:10
IC5IS
9:8
T5IP
4:2
T5IS
1:0
IPC6Interrupt Priority Control Register
Address
0xBF8810F0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CMP1IP
28:26
CMP1IS
25:24
FCEIP
20:18
FCEIS
17:16
RTCCIP
12:10
RTCCIS
9:8
FSCMIP
4:2
FSCMIS
1:0
IPC7Interrupt Priority Control Register
Address
0xBF881100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SPI1IP
28:26
SPI1IS
25:24
USBIP
20:18
USBIS
17:16
CMP3IP
12:10
CMP3IS
9:8
CMP2IP
4:2
CMP2IS
1:0
IPC8Interrupt Priority Control Register
Address
0xBF881110
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
PMPIP
28:26
PMPIS
25:24
CNIP
20:18
CNIS
17:16
I2C1IP
12:10
I2C1IS
9:8
U1IP
4:2
U1IS
1:0
IPC9Interrupt Priority Control Register
Address
0xBF881120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CTMUIP
28:26
CTMUIS
25:24
I2C2IP
20:18
I2C2IS
17:16
U2IP
12:10
U2IS
9:8
SPI2IP
4:2
SPI2IS
1:0
IPC10Interrupt Priority Control Register
Address
0xBF881130
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DMA3IP
28:26
DMA3IS
25:24
DMA2IP
20:18
DMA2IS
17:16
DMA1IP
12:10
DMA1IS
9:8
DMA0IP
4:2
DMA0IS
1:0
BMX Bus matrix
BMXCONBus Matrix Configuration Register
Address
0xBF882000
Reset
0x001F0041
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BMXCHEDMA
26
BMX PFM Cacheability for DMA Accesses bit
0 Disable program Flash memory (data) cacheability for DMA accesses(hits are still read from the cache
1 Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled)
BMXERRIXI
20
Enable Bus Error from IXI bit
0 Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
1 Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD
19
Enable Bus Error from ICD Debug Unit bit
0 Disable bus error exceptions for unmapped address accesses initiated from ICD
1 Enable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA
18
Bus Error from DMA bit
0 Disable bus error exceptions for unmapped address accesses initiated from DMA
1 Enable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS
17
Bus Error from CPU Data Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU data access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS
16
Bus Error from CPU Instruction Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
BMXWSDRM
6
CPU Instruction or Data Access from Data RAM Wait State bit
0 Data RAM accesses from CPU have zero wait states for address setup
1 Data RAM accesses from CPU have one wait state for address setup
BMXARB
2:0
Bus Matrix Arbitration Mode bits
0 Arbitration Mode 0
1 Arbitration Mode 1 (default)
2 Arbitration Mode 2
3 Reserved (using these configuration modes will produce undefined behavior)
4 Reserved (using these configuration modes will produce undefined behavior)
5 Reserved (using these configuration modes will produce undefined behavior)
6 Reserved (using these configuration modes will produce undefined behavior)
7 Reserved (using these configuration modes will produce undefined behavior)
BMXDKPBAData RAM Kernel Program Base Address Register
Address
0xBF882010
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUDBAData RAM User Data Base Address Register
Address
0xBF882020
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUPBAData RAM User Program Base Address Register
Address
0xBF882030
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDRMSZData RAM Size Register
Address
0xBF882040
Reset
0x00020000
Access
read only
Size
32-bit
BMXPUPBAProgram Flash (PFM) User Program Base Address Register
Address
0xBF882050
Reset
0x00000000
Access
read/write
Size
32-bit
BMXPFMSZProgram Flash (PFM) Size Register
Address
0xBF882060
Reset
0x00080000
Access
read only
Size
32-bit
BMXBOOTSZBoot Flash (IFM) Size Register
Address
0xBF882070
Reset
0x00003000
Access
read only
Size
32-bit
DMAC DMA controller
DMACONDMA Controller Control Register
Address
0xBF883000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
DMA On bit
0 DMA module is enabled
0 DMA module is disabled
SUSPEND
12
DMA Suspend bit
0 DMA operates normally
1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY
11
DMA Module Busy bit
0 DMA module is disabled and not actively transferring data
1 DMA module is active
DMASTATDMA Status Register
Address
0xBF883010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
RDWR
3
Read/Write Status bit
0 Last DMA bus access was a write
1 Last DMA bus access was a read
DMACH
1:0
DMAADDRDMA Address Register
Address
0xBF883020
Reset
0x00000000
Access
read only
Size
32-bit
DCRCCONDMA CRC Control Register
Address
0xBF883030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BYTO
29:28
CRC Byte Order Selection bits
0 No swapping (i.e. source byte order)
1 Endian byte swap on word boundaries (i.e. reverse source byte order)
2 Swap half-words on word boundaries (i.e. reverse source half-word order with source byte order per half-word)
3 Endian byte swap on half-word boundaries (i.e. source half-word order with reverse source byte order per half-word)
WBO
27
CRC Write Byte Order Selection bit
0 Source data is written to the destination unaltered
1 Source data is written to the destination re-ordered as defined by BYTO
BITO
24
CRC Bit Order Selection bit
0 (When CRCTYP is 1) The IP header checksum is calculated Most Significant bit (MSb) first (i.e. not reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Most Significant bit first (i.e. not reflected)
1 (When CRCTYP is 1) The IP header checksum is calculated Least Significant bit (LSb) first (i.e. reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Least Significant bit first (i.e. reflected)
PLEN
12:8
Polynomial Length bits
1 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 0
2 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 1
3 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 2
4 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 3
5 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 4
6 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 5
7 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 6
8 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 7
9 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 8
10 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 9
11 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 10
12 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 11
13 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 12
14 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 13
15 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 14
16 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 15
17 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 16
18 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 17
19 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 18
20 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 19
21 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 20
22 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 21
23 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 22
24 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 23
25 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 24
26 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 25
27 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 26
28 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 27
29 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 28
30 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 29
31 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 30
CRCEN
7
CRC Enable bit
0 CRC module is disabled and channel transfers proceed normally
1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP
6
CRC Append Mode bit
0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP
5
CRC Type Selection bit
0 The CRC module will calculate a LFSR CRC
1 The CRC module will calculate an IP header checksum
CRCCH
2:0
CRC Channel Select bits
0 CRC is assigned to Channel 0
1 CRC is assigned to Channel 1
2 CRC is assigned to Channel 2
3 CRC is assigned to Channel 3
4 Reserved
5 Reserved
6 Reserved
7 Reserved
DCRCDATADMA CRC Data Register
Address
0xBF883040
Reset
0x00000000
Access
read/write
Size
32-bit
DCRCXORDMA CRCXOR Enable Register
Address
0xBF883050
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0 DMA channel 0
DCH0CONDMA Channel x Control Register
Address
0xBF883060
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CHBUSY
15
Channel Busy bit
0 Channel is inactive or has been disabled
1 Channel is active or has been enabled
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH0ECONDMA Channel x Event Control Register
Address
0xBF883070
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH0INTDMA Channel x Interrupt Control Register
Address
0xBF883080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH0SSADMA Channel x Source Start Address Register
Address
0xBF883090
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DSADMA Channel x Destination Start Address Register
Address
0xBF8830A0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0SSIZDMA Channel x Source Size Register
Address
0xBF8830B0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DSIZDMA Channel x Destination Size Register
Address
0xBF8830C0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0SPTRDMA Channel x Source Pointer Register
Address
0xBF8830D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DPTRDMA Channel x Destination Pointer Register
Address
0xBF8830E0
Reset
0x00000000
Access
read only
Size
32-bit
DCH0CSIZDMA Channel x Cell-Size Register
Address
0xBF8830F0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0CPTRDMA Channel x Cell Pointer Register
Address
0xBF883100
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DATDMA Channel x Pattern Data Register
Address
0xBF883110
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1 DMA channel 1
DCH1CONDMA Channel x Control Register
Address
0xBF883120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CHBUSY
15
Channel Busy bit
0 Channel is inactive or has been disabled
1 Channel is active or has been enabled
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH1ECONDMA Channel x Event Control Register
Address
0xBF883130
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH1INTDMA Channel x Interrupt Control Register
Address
0xBF883140
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH1SSADMA Channel x Source Start Address Register
Address
0xBF883150
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DSADMA Channel x Destination Start Address Register
Address
0xBF883160
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1SSIZDMA Channel x Source Size Register
Address
0xBF883170
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DSIZDMA Channel x Destination Size Register
Address
0xBF883180
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1SPTRDMA Channel x Source Pointer Register
Address
0xBF883190
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DPTRDMA Channel x Destination Pointer Register
Address
0xBF8831A0
Reset
0x00000000
Access
read only
Size
32-bit
DCH1CSIZDMA Channel x Cell-Size Register
Address
0xBF8831B0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1CPTRDMA Channel x Cell Pointer Register
Address
0xBF8831C0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DATDMA Channel x Pattern Data Register
Address
0xBF8831D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2 DMA channel 2
DCH2CONDMA Channel x Control Register
Address
0xBF8831E0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CHBUSY
15
Channel Busy bit
0 Channel is inactive or has been disabled
1 Channel is active or has been enabled
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH2ECONDMA Channel x Event Control Register
Address
0xBF8831F0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH2INTDMA Channel x Interrupt Control Register
Address
0xBF883200
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH2SSADMA Channel x Source Start Address Register
Address
0xBF883210
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DSADMA Channel x Destination Start Address Register
Address
0xBF883220
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2SSIZDMA Channel x Source Size Register
Address
0xBF883230
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DSIZDMA Channel x Destination Size Register
Address
0xBF883240
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2SPTRDMA Channel x Source Pointer Register
Address
0xBF883250
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DPTRDMA Channel x Destination Pointer Register
Address
0xBF883260
Reset
0x00000000
Access
read only
Size
32-bit
DCH2CSIZDMA Channel x Cell-Size Register
Address
0xBF883270
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2CPTRDMA Channel x Cell Pointer Register
Address
0xBF883280
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DATDMA Channel x Pattern Data Register
Address
0xBF883290
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3 DMA channel 3
DCH3CONDMA Channel x Control Register
Address
0xBF8832A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CHBUSY
15
Channel Busy bit
0 Channel is inactive or has been disabled
1 Channel is active or has been enabled
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH3ECONDMA Channel x Event Control Register
Address
0xBF8832B0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH3INTDMA Channel x Interrupt Control Register
Address
0xBF8832C0
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH3SSADMA Channel x Source Start Address Register
Address
0xBF8832D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DSADMA Channel x Destination Start Address Register
Address
0xBF8832E0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3SSIZDMA Channel x Source Size Register
Address
0xBF8832F0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DSIZDMA Channel x Destination Size Register
Address
0xBF883300
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3SPTRDMA Channel x Source Pointer Register
Address
0xBF883310
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DPTRDMA Channel x Destination Pointer Register
Address
0xBF883320
Reset
0x00000000
Access
read only
Size
32-bit
DCH3CSIZDMA Channel x Cell-Size Register
Address
0xBF883330
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3CPTRDMA Channel x Cell Pointer Register
Address
0xBF883340
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DATDMA Channel x Pattern Data Register
Address
0xBF883350
Reset
0x00000000
Access
read/write
Size
32-bit
PCACHE Prefetch cache
CHECONCache Control Register
Address
0xBF884000
Reset
0x00000007
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CHECOH
16
Cache Coherency Setting on a PFM Program Cycle bit
0 Invalidate all data lines and instruction lines that are not locked
1 Invalidate all data and instruction lines
DCSZ
9:8
Data Cache Size in Lines bits
0 Disable data caching
1 Enable data caching with a size of 1 Line
2 Enable data caching with a size of 2 Lines
3 Enable data caching with a size of 4 Lines
PREFEN
5:4
Predictive Prefetch Enable bits
0 Disable predictive prefetch
1 Enable predictive prefetch for cacheable regions only
2 Enable predictive prefetch for non-cacheable regions only
3 Enable predictive prefetch for both cacheable and non-cacheable regions
PFMWS
2:0
PFM Access Time Defined in Terms of SYSLK Wait States bits
0 Zero Wait state
1 One Wait state
2 Two Wait states
3 Three Wait states
4 Four Wait states
5 Five Wait states
6 Six Wait states
7 Seven Wait states
CHEACCCache Access Register
Address
0xBF884010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CHEIDX
3:0
Cache Line Index bits
0 Select cache line 0 for reading or writing
1 Select cache line 1 for reading or writing
2 Select cache line 2 for reading or writing
3 Select cache line 3 for reading or writing
4 Select cache line 4 for reading or writing
5 Select cache line 5 for reading or writing
6 Select cache line 6 for reading or writing
7 Select cache line 7 for reading or writing
8 Select cache line 8 for reading or writing
9 Select cache line 9 for reading or writing
10 Select cache line 10 for reading or writing
11 Select cache line 11 for reading or writing
12 Select cache line 12 for reading or writing
13 Select cache line 13 for reading or writing
14 Select cache line 14 for reading or writing
15 Select cache line 15 for reading or writing
CHEWEN
31
Cache Access Enable bits for registers CHETAG
0 The cache line selected by CHEIDX(3:0) is not writeable
1 The cache line selected by CHEIDX(3:0) is writeable
CHETAGCache TAG Register
Address
0xBF884020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
LTAG
4
LVALID
3
Line Valid bit
0 The line is not valid and is not compared to the physical address for hit detection
1 The line is valid and is compared to the physical address for hit detection
LLOCK
2
Line Lock bit
0 The line is not locked and can be replaced
1 The line is locked and will not be replaced
LTYPE
1
Line Type bit
0 The line caches data words
1 The line caches instruction words
LTAGBOOT
31
Line TAG Address Boot bit
0 The line is in the 0x1FC00000 (physical) area of memory
1 The line is in the 0x1D000000 (physical) area of memory
CHEMSKCache TAG Mask Register
Address
0xBF884030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LMASK
15:5
Line Mask bits
0 Only writeable for values of CHEIDX(3:0) bits (CHEACC(3:0)) equal to 0x0A and 0x0B. Disables mask logic.
1 Enables mask logic to force a match on the corresponding bit position in the LTAG(19:0) bits (CHETAG(23:4)) and the physical address.
CHEW0Cache Word 0
Address
0xBF884040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEW0
31:0
CHEW1Cache Word 1
Address
0xBF884050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEW1
31:0
CHEW2Cache Word 2
Address
0xBF884060
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEW2
31:0
CHEW3Cache Word 3
Address
0xBF884070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEW3
31:0
CHELRUCache LRU Register
Address
0xBF884080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHELRU
24:0
CHEHITCache Hit Statistics Register
Address
0xBF884090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEHIT
31:0
CHEMISCache Miss Statistics Register
Address
0xBF8840A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEMIS
31:0
CHEPFABTPrefetch Cache Abort Statistics Register
Address
0xBF8840C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHEPFABT
31:0
USB1 USB
U1OTGIRUSB OTG Interrupt Status Register
Address
0xBF885040
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
IDIF
7
ID State Change Indicator bit
0 No change in ID state is detected
1 Change in ID state is detected
T1MSECIF
6
1 Millisecond Timer bit
0 1 millisecond timer has not expired
1 1 millisecond timer has expired
LSTATEIF
5
Line State Stable Indicator bit
0 USB line state has not been stable for 1 millisecond
1 USB line state has been stable for 1millisecond
ACTVIF
4
Bus Activity Indicator bit
0 Activity has not been detected
1 Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
SESVDIF
3
Session Valid Change Indicator bit
0 Vbus voltage has not dropped below the session end level
1 VBUS voltage has dropped below the session end level
SESENDIF
2
B-Device Vbus Change Indicator bit
0 No change on the session end input was detected
1 A change on the session end input was detected
VBUSVDIF
0
A-Device Vbus Change Indicator bit
0 No change on the session valid input is detected
1 Change on the session valid input is detected
U1OTGIEUSB OTG Interrupt Enable Register
Address
0xBF885050
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
IDIE
7
ID Interrupt Enable bit
0 ID interrupt is disabled
1 ID interrupt is enabled
T1MSECIE
6
1 Millisecond Timer Interrupt Enable bit
0 1 millisecond timer interrupt is disabled
1 1 millisecond timer interrupt is enabled
LSTATEIE
5
Line State Interrupt Enable bit
0 Line state interrupt is disabled
1 Line state interrupt is enabled
ACTVIE
4
Bus Activity Interrupt Enable bit
0 ACTIVITY interrupt is disabled
1 ACTIVITY interrupt is enabled
SESVDIE
3
Session Valid Interrupt Enable bit
0 Session valid interrupt is disabled
1 Session valid interrupt is enabled
SESENDIE
2
B-Session End Interrupt Enable bit
0 B-session end interrupt is disabled
1 B-session end interrupt is enabled
VBUSVDIE
0
A- Vbus Valid Interrupt Enable bit
0 A-VBUS valid interrupt is disabled
1 A-VBUS valid interrupt is enabled
U1OTGSTATUSB OTG Status Register
Address
0xBF885060
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ID
7
ID Pin State Indicator bit
0 A Type-A cable has been plugged into the USB receptacle
1 No cable is attached or a Type-B cable has been plugged into the USB receptacle
LSTATE
5
Line State Stable Indicator bit
0 USB line state (U1CON(SE0) and U1CON(JSTATE)) has not been stable for the previous 1 ms
1 USB line state (U1CON(SE0) and U1CON(JSTATE)) has been stable for the previous 1 ms
SESVD
3
Session Valid Indicator bit
0 Vbus voltage is below Session Valid on the A or B device
1 Vbus voltage is above Session Valid on the A or B device
SESEND
2
B-Device Session End Indicator bit
0 Vbus voltage is above Session Valid on the B device
1 Vbus voltage is below Session Valid on the B device
VBUSVD
0
A-Device Vbus Valid Indicator bit
0 Vbus voltage is below Session Valid on the A device
1 Vbus voltage is above Session Valid on the A device
U1OTGCONUSB OTG Control Register
Address
0xBF885070
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DPPULUP
7
D+ Pull-Up Enable bit
0 D+ data line pull-up resistor is disabled
1 D+ data line pull-up resistor is enabled
DMPULUP
6
D- Pull-Up Enable bit
0 D- data line pull-up resistor is disabled
1 D- data line pull-up resistor is enabled
DPPULDWN
5
D+ Pull-Down Enable bit
0 D+ data line pull-down resistor is disabled
1 D+ data line pull-down resistor is enabled
DMPULDWN
4
D- Pull-Down Enable bit
0 D- data line pull-down resistor is disabled
1 D- data line pull-down resistor is enabled
VBUSON
3
VBUS Power-on bit
0 VBUS line is not powered
1 VBUS line is powered
OTGEN
2
OTG Functionality Enable bit
0 DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
1 DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
VBUSCHG
1
VBUS Charge Enable bit
0 VBUS line is not charged through a resistor
1 VBUS line is charged through a pull-up resistor
VBUSDIS
0
VBUS Discharge Enable bit
0 VBUS line is not discharged through a resistor
1 VBUS line is discharged through a pull-down resistor
U1PWRCUSB Power Control Register
Address
0xBF885080
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
UACTPND
7
USB Activity Pending bit
0 An interrupt is not pending
1 USB bus activity has been detected; but an interrupt is pending
USLPGRD
4
USB Sleep Entry Guard bit
0 USB module does not block Sleep entry
1 Sleep entry is blocked if USB bus activity is detected or if a notification is pending
USBBUSY
3
USB Module Busy bit
0 USB module is not active and is ready to be enabled
1 USB module is active or disabled
USUSPEND
1
USB Suspend Mode bit
0 USB module operates normally
1 USB module is placed in Suspend mode
USBPWR
0
USB Operation Enable bit
0 USB module is disabled
1 USB module is turned on
U1IRUSB Interrupt Register
Address
0xBF885200
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
STALLIF
7
STALL Handshake Interrupt bit
0 STALL handshake has not been sent
1 (In Host mode) a STALL handshake was received during the handshake phase of the transaction / (In Device mode) a STALL handshake was transmitted during the handshake phase of the transaction
ATTACHIF
6
Peripheral Attach Interrupt bit
0 Peripheral attachment was not detected
1 Peripheral attachment was detected by the USB module
RESUMEIF
5
Resume Interrupt bit
0 K-State is not observed
1 K-State is observed on the D+ or D- pin for 2.5 usec
IDLEIF
4
Idle Detect Interrupt bit
0 No Idle condition detected
1 Idle condition detected (constant Idle state of 3 ms or more)
TRNIF
3
Token Processing Complete Interrupt bit
0 Processing of current token not complete
1 Processing of current token is complete; a read of the U1STAT register will provide endpoint information
SOFIF
2
SOF Token Interrupt bit
0 SOF token was not received nor threshold reached
1 SOF token received by the peripheral or the SOF threshold reached by the host
UERRIF
1
USB Error Condition Interrupt bit
0 Unmasked error condition has not occurred
1 Unmasked error condition has occurred
URSTIF_DETACHIF
0
U1IEUSB Interrupt Enable Register
Address
0xBF885210
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
STALLIE
7
STALL Handshake Interrupt Enable bit
0 STALL interrupt is disabled
1 STALL interrupt is enabled
ATTACHIE
6
ATTACH Interrupt Enable bit
0 ATTACH interrupt is disabled
1 ATTACH interrupt is enabled
RESUMEIE
5
RESUME Interrupt Enable bit
0 RESUME interrupt is disabled
1 RESUME interrupt is enabled
IDLEIE
4
Idle Detect Interrupt Enable bit
0 Idle interrupt is disabled
1 Idle interrupt is enabled
TRNIE
3
Token Processing Complete Interrupt Enable bit
0 TRNIF interrupt is disabled
1 TRNIF interrupt is enabled
SOFIE
2
SOF Token Interrupt Enable bit
0 SOFIF interrupt is disabled
1 SOFIF interrupt is enabled
UERRIE
1
USB Error Interrupt Enable bit
0 USB Error interrupt is disabled
1 USB Error interrupt is enabled
URSTIE_DETACHIE
0
U1EIRUSB Error Interrupt Status Register
Address
0xBF885220
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BTSEF
7
Bit Stuff Error Flag bit
0 Packet is accepted
1 Packet is rejected due to bit stuff error
BMXEF
6
Bus Matrix Error Flag bit
0 No address error
1 The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, i s invalid
DMAEF
5
DMA Error Flag bit
0 No DMA error
1 USB DMA error condition detected
BTOEF
4
Bus Turnaround Time-Out Error Flag bit
0 No bus turnaround time-out
1 Bus turnaround time-out has occurred
DFN8EF
3
Data Field Size Error Flag bit
0 Data field received is an integral number of bytes
1 Data field received is not an integral number of bytes
CRC16EF
2
CRC16 Failure Flag bit
0 Data packet accepted
1 Data packet rejected due to CRC16 error
CRC5EF_EOFEF
1
PIDEF
0
PID Check Failure Flag bit
0 PID check is passed
1 PID check is failed
U1EIEUSB Error Interrupt Enable Register
Address
0xBF885230
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BTSEE
7
Bit Stuff Error Interrupt Enable bit
0 BTSEF interrupt is disabled
1 BTSEF interrupt is enabled
BMXEE
6
Bus Matrix Error Interrupt Enable bit
0 BMXEF interrupt is disabled
1 BMXEF interrupt is enabled
DMAEE
5
DMA Error Interrupt Enable bit
0 DMAEF interrupt is disabled
1 DMAEF interrupt is enabled
BTOEE
4
Bus Turnaround Time-out Error Interrupt Enable bit
0 BTOEF interrupt is disabled
1 BTOEF interrupt is enabled
DFN8EE
3
Data Field Size Error Interrupt Enable bit
0 DFN8EF interrupt is disabled
1 DFN8EF interrupt is enabled
CRC16EE
2
CRC16 Failure Interrupt Enable bit
0 CRC16EF interrupt is disabled
1 CRC16EF interrupt is enabled
CRC5EE_EOFEE
1
PIDEE
0
PID Check Failure Interrupt Enable bit
0 PIDEF interrupt is disabled
1 PIDEF interrupt is enabled
U1STATUSB Status Register
Address
0xBF885240
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
ENDPT
4
Encoded Number of Last Endpoint Activity bits
0 Endpoint 0
1 Endpoint 1
2 Endpoint 2
3 Endpoint 3
4 Endpoint 4
5 Endpoint 5
6 Endpoint 6
7 Endpoint 7
8 Endpoint 8
9 Endpoint 9
10 Endpoint 10
11 Endpoint 11
12 Endpoint 12
13 Endpoint 13
14 Endpoint 14
15 Endpoint 15
DIR
3
Last BD Direction Indicator bit
0 Last transaction was a receive transfer (RX)
1 Last transaction was a transmit transfer (TX)
PPBI
2
Ping-Pong BD Pointer Indicator bit
0 The last transaction was to the EVEN BD bank
1 The last transaction was to the ODD BD bank
U1CONUSB Control Register
Address
0xBF885250
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
JSTATE
7
Live Differential Receiver JSTATE flag bit
0 No JSTATE detected
1 JSTATE detected on the USB
SE0
6
Live Single-Ended Zero flag bit
0 No Single Ended Zero detected
1 Single Ended Zero detected on the USB
PKTDIS_TOKBUSY
5
USBRST
4
Module Reset bit
0 USB reset is terminated
1 USB reset is generated
HOSTEN
3
Host Mode Enable bit
0 USB host capability is disabled
1 USB host capability is enabled
RESUME
2
RESUME Signaling Enable bit
0 RESUME signaling is disabled
1 RESUME signaling is activated
PPBRST
1
Ping-Pong Buffers Reset bit
0 Even/Odd buffer pointers not being Reset
1 Reset all Even/Odd buffer pointers to the EVEN BD banks
USBEN_SOFEN
0
U1ADDRUSB Address Register
Address
0xBF885260
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
LSPDEN
7
Low Speed Enable Indicator bit
0 Next token command to be executed at Full Speed
1 Next token command to be executed at Low Speed
DEVADDR
6:0
7-bit USB Device Address bits
0 Device address is 0
127 Device address is 0x7f
U1BDTP1USB BDT Page 1 Register
Address
0xBF885270
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BDTPTRL
7:1
U1FRMLUSB Frame Number Low Register
Address
0xBF885280
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
FRML
7:0
U1FRMHUSB Frame Number High Register
Address
0xBF885290
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
FRMH
2:0
U1TOKUSB Token Register
Address
0xBF8852A0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
PID
7:4
Token Type Indicator bits
1 OUT (TX) token type transaction
9 IN (RX) token type transaction
13 SETUP (TX) token type transaction
EP
3:0
Token Command Endpoint Address bits
0 Endpoint address is 0
U1SOFUSB SOF Threshold Register
Address
0xBF8852B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CNT
7:0
SOF Threshold Value bits
18 8-byte packet
26 16-byte packet
42 32-byte packet
74 64-byte packet
U1BDTP2USB BDT PAGE 2 Register
Address
0xBF8852C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BDTPTRH
7:0
BDT Base Address bits
0 BDT base address is 0
U1BDTP3USB BDT PAGE 3 Register
Address
0xBF8852D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BDTPTRU
7:0
BDT Base Address bits
0 BDT base address is 0
U1CNFG1USB Configuration 1 Register
Address
0xBF8852E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
UTEYE
7
USB Eye-Pattern Test Enable bit
0 Eye-Pattern Test is disabled
2 Eye-Pattern Test is enabled
UOEMON
6
USBSIDL
4
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
UASUSPND
0
Automatic Suspend Enable bit
0 USB module does not automatically suspend upon entry to Sleep mode.
1 USB module automatically suspends upon entry to Sleep mode.
U1EP0USB Endpoint 0 Control Register
Address
0xBF885300
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
LSPD
7
Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
0 Direct connection to a low-speed device is disabled; hub required with PRE_PID
1 Direct connection to a low-speed device is enabled
RETRYDIS
6
Retry Disable bit (Host mode and U1EP0 only)
0 Retry NAKed transactions is enabled; retry done in hardware
1 Retry NAKed transactions is disabled
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP1USB Endpoint 1 Control Register
Address
0xBF885310
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP2USB Endpoint 2 Control Register
Address
0xBF885320
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP3USB Endpoint 3 Control Register
Address
0xBF885330
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP4USB Endpoint 4 Control Register
Address
0xBF885340
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP5USB Endpoint 5 Control Register
Address
0xBF885350
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP6USB Endpoint 6 Control Register
Address
0xBF885360
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP7USB Endpoint 7 Control Register
Address
0xBF885370
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP8USB Endpoint 8 Control Register
Address
0xBF885380
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP9USB Endpoint 9 Control Register
Address
0xBF885390
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP10USB Endpoint 10 Control Register
Address
0xBF8853A0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP11USB Endpoint 11 Control Register
Address
0xBF8853B0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP12USB Endpoint 12 Control Register
Address
0xBF8853C0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP13USB Endpoint 13 Control Register
Address
0xBF8853D0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP14USB Endpoint 14 Control Register
Address
0xBF8853E0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
1 Endpoint Handshake is enabled
U1EP15USB Endpoint 15 Control Register
Address
0xBF8853F0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
EPCONDIS
4
Bidirectional Endpoint Control bit
0 Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
1 Disable Endpoint n from Control transfers; only TX and RX transfers allowed
EPRXEN
3
Endpoint Receive Enable bit
0 Endpoint n receive is disabled
1 Endpoint n receive is enabled
EPTXEN
2
Endpoint Transmit Enable bit
0 Endpoint n transmit is disabled
1 Endpoint n transmit is enabled
EPSTALL
1
Endpoint Stall Status bit
0 Endpoint n was not stalled
1 Endpoint n was stalled
EPHSHK
0
Endpoint Handshake Enable bit
0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
BETA