All 247 registers by peripheral, at the virtual address XC32 and the datasheet's register tables use (the SFRs from 0xBF800000), with their reset value and every field.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
WDT Watchdog timer
WDTCON
Address
0xBF800000
Reset
0x00000600
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
Watchdog Timer Enable bit
0 Disable the WDT if it was enabled in software
1 Enables the WDT if it is not enabled by the device configuration
SWDTPS
6:2
WDTCLR
0
Watchdog Timer Reset bit
0 Software cannot force this bit to a 0
1 Writing a 1 will clear the WDT
RTCC Real-time clock and calendar
RTCCONRTC Control Register
Address
0xBF800200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
CAL
25:16
RTC Drift Calibration bits
0 No adjustment
1 Minimum positive adjustment, adds 1 RTC clock pulse every one minute
511 Maximum positive adjustment, adds 511 RTC clock pulses every one minute
512 Maximum negative adjustment, subtracts 512 clock pulses every one minute
1023 Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
ON
15
RTCC On bit
0 RTCC module is disabled
1 RTCC module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue normal operation in Idle mode
1 Disables the PBCLK to the RTCC when CPU enters in Idle mode
RTSECSEL
7
RTCC Seconds Clock Output Select bit
0 RTCC Alarm Pulse is selected for the RTCC pin
1 RTCC Seconds Clock is selected for the RTCC pin
RTCCLKON
6
RTCC Clock Enable Status bit
0 RTCC Clock is not running
1 RTCC Clock is actively running
RTCWREN
3
RTC Value Registers Write Enable bit
0 RTC Value registers are locked out from being written to by the user
1 RTC Value registers can be written to by the user
RTCSYNC
2
RTCC Value Registers Read Synchronization bit
0 RTC Value registers can be read without concern about a rollover ripple
1 RTC Value registers can change while reading due to a rollover ripple that results in an invalid data read
HALFSEC
1
Half-Second Status bit
0 First half period of a second
1 Second half period of a second
RTCOE
0
RTCC Output Enable bit
0 RTCC clock output is disabled
1 RTCC clock output is enabled clock presented onto an I/O
RTCALRMRTC ALARM Control Register
Address
0xBF800210
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ALRMEN
15
Alarm Enable bit
0 Alarm is disabled
1 Alarm is enabled
CHIME
14
Chime Enable bit
0 Chime is disabled ARPT(7:0) stops once it reaches 0x00
1 Chime is enabled ARPT(7:0) is allowed to rollover from 0x00 to 0xFF
PIV
13
Alarm Pulse Initial Value bit
0 (When ALRMEN = 0) Alarm pulse low / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
1 (When ALRMEN = 0) Alarm pulse high / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
ALRMSYNC
12
Alarm Sync bit
0 ARPT(7:0) and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 RTC clocks away from a half-second rollover
1 ARPT(7:0) and ALRMEN may change as a result of a half second rollover during a read.
AMASK
11:8
Alarm Mask Configuration bits
0 Every half-second
1 Every second
2 Every 10 seconds
3 Every minute
4 Every 10 minutes
5 Every hour
6 Once a day
7 Once a week
8 Once a month
9 Once a year (except when configured for February 29
10 Reserved; do not use
11 Reserved; do not use
12 Reserved; do not use
13 Reserved; do not use
14 Reserved; do not use
15 Reserved; do not use
ARPT
7:0
Alarm Repeat Counter Value bits
0 Alarm will trigger 1 times
1 Alarm will trigger 2 times
2 Alarm will trigger 3 times
3 Alarm will trigger 4 times
4 Alarm will trigger 5 times
5 Alarm will trigger 6 times
6 Alarm will trigger 7 times
7 Alarm will trigger 8 times
8 Alarm will trigger 9 times
9 Alarm will trigger 10 times
10 Alarm will trigger 11 times
11 Alarm will trigger 12 times
12 Alarm will trigger 13 times
13 Alarm will trigger 14 times
14 Alarm will trigger 15 times
15 Alarm will trigger 16 times
16 Alarm will trigger 17 times
17 Alarm will trigger 18 times
18 Alarm will trigger 19 times
19 Alarm will trigger 20 times
20 Alarm will trigger 21 times
21 Alarm will trigger 22 times
22 Alarm will trigger 23 times
23 Alarm will trigger 24 times
24 Alarm will trigger 25 times
25 Alarm will trigger 26 times
26 Alarm will trigger 27 times
27 Alarm will trigger 28 times
28 Alarm will trigger 29 times
29 Alarm will trigger 30 times
30 Alarm will trigger 31 times
31 Alarm will trigger 32 times
32 Alarm will trigger 33 times
33 Alarm will trigger 34 times
34 Alarm will trigger 35 times
35 Alarm will trigger 36 times
36 Alarm will trigger 37 times
37 Alarm will trigger 38 times
38 Alarm will trigger 39 times
39 Alarm will trigger 40 times
40 Alarm will trigger 41 times
41 Alarm will trigger 42 times
42 Alarm will trigger 43 times
43 Alarm will trigger 44 times
44 Alarm will trigger 45 times
45 Alarm will trigger 46 times
46 Alarm will trigger 47 times
47 Alarm will trigger 48 times
48 Alarm will trigger 49 times
49 Alarm will trigger 50 times
50 Alarm will trigger 51 times
51 Alarm will trigger 52 times
52 Alarm will trigger 53 times
53 Alarm will trigger 54 times
54 Alarm will trigger 55 times
55 Alarm will trigger 56 times
56 Alarm will trigger 57 times
57 Alarm will trigger 58 times
58 Alarm will trigger 59 times
59 Alarm will trigger 60 times
60 Alarm will trigger 61 times
61 Alarm will trigger 62 times
62 Alarm will trigger 63 times
63 Alarm will trigger 64 times
64 Alarm will trigger 65 times
65 Alarm will trigger 66 times
66 Alarm will trigger 67 times
67 Alarm will trigger 68 times
68 Alarm will trigger 69 times
69 Alarm will trigger 70 times
70 Alarm will trigger 71 times
71 Alarm will trigger 72 times
72 Alarm will trigger 73 times
73 Alarm will trigger 74 times
74 Alarm will trigger 75 times
75 Alarm will trigger 76 times
76 Alarm will trigger 77 times
77 Alarm will trigger 78 times
78 Alarm will trigger 79 times
79 Alarm will trigger 80 times
80 Alarm will trigger 81 times
81 Alarm will trigger 82 times
82 Alarm will trigger 83 times
83 Alarm will trigger 84 times
84 Alarm will trigger 85 times
85 Alarm will trigger 86 times
86 Alarm will trigger 87 times
87 Alarm will trigger 88 times
88 Alarm will trigger 89 times
89 Alarm will trigger 90 times
90 Alarm will trigger 91 times
91 Alarm will trigger 92 times
92 Alarm will trigger 93 times
93 Alarm will trigger 94 times
94 Alarm will trigger 95 times
95 Alarm will trigger 96 times
96 Alarm will trigger 97 times
97 Alarm will trigger 98 times
98 Alarm will trigger 99 times
99 Alarm will trigger 100 times
100 Alarm will trigger 101 times
101 Alarm will trigger 102 times
102 Alarm will trigger 103 times
103 Alarm will trigger 104 times
104 Alarm will trigger 105 times
105 Alarm will trigger 106 times
106 Alarm will trigger 107 times
107 Alarm will trigger 108 times
108 Alarm will trigger 109 times
109 Alarm will trigger 110 times
110 Alarm will trigger 111 times
111 Alarm will trigger 112 times
112 Alarm will trigger 113 times
113 Alarm will trigger 114 times
114 Alarm will trigger 115 times
115 Alarm will trigger 116 times
116 Alarm will trigger 117 times
117 Alarm will trigger 118 times
118 Alarm will trigger 119 times
119 Alarm will trigger 120 times
120 Alarm will trigger 121 times
121 Alarm will trigger 122 times
122 Alarm will trigger 123 times
123 Alarm will trigger 124 times
124 Alarm will trigger 125 times
125 Alarm will trigger 126 times
126 Alarm will trigger 127 times
127 Alarm will trigger 128 times
128 Alarm will trigger 129 times
129 Alarm will trigger 130 times
130 Alarm will trigger 131 times
131 Alarm will trigger 132 times
132 Alarm will trigger 133 times
133 Alarm will trigger 134 times
134 Alarm will trigger 135 times
135 Alarm will trigger 136 times
136 Alarm will trigger 137 times
137 Alarm will trigger 138 times
138 Alarm will trigger 139 times
139 Alarm will trigger 140 times
140 Alarm will trigger 141 times
141 Alarm will trigger 142 times
142 Alarm will trigger 143 times
143 Alarm will trigger 144 times
144 Alarm will trigger 145 times
145 Alarm will trigger 146 times
146 Alarm will trigger 147 times
147 Alarm will trigger 148 times
148 Alarm will trigger 149 times
149 Alarm will trigger 150 times
150 Alarm will trigger 151 times
151 Alarm will trigger 152 times
152 Alarm will trigger 153 times
153 Alarm will trigger 154 times
154 Alarm will trigger 155 times
155 Alarm will trigger 156 times
156 Alarm will trigger 157 times
157 Alarm will trigger 158 times
158 Alarm will trigger 159 times
159 Alarm will trigger 160 times
160 Alarm will trigger 161 times
161 Alarm will trigger 162 times
162 Alarm will trigger 163 times
163 Alarm will trigger 164 times
164 Alarm will trigger 165 times
165 Alarm will trigger 166 times
166 Alarm will trigger 167 times
167 Alarm will trigger 168 times
168 Alarm will trigger 169 times
169 Alarm will trigger 170 times
170 Alarm will trigger 171 times
171 Alarm will trigger 172 times
172 Alarm will trigger 173 times
173 Alarm will trigger 174 times
174 Alarm will trigger 175 times
175 Alarm will trigger 176 times
176 Alarm will trigger 177 times
177 Alarm will trigger 178 times
178 Alarm will trigger 179 times
179 Alarm will trigger 180 times
180 Alarm will trigger 181 times
181 Alarm will trigger 182 times
182 Alarm will trigger 183 times
183 Alarm will trigger 184 times
184 Alarm will trigger 185 times
185 Alarm will trigger 186 times
186 Alarm will trigger 187 times
187 Alarm will trigger 188 times
188 Alarm will trigger 189 times
189 Alarm will trigger 190 times
190 Alarm will trigger 191 times
191 Alarm will trigger 192 times
192 Alarm will trigger 193 times
193 Alarm will trigger 194 times
194 Alarm will trigger 195 times
195 Alarm will trigger 196 times
196 Alarm will trigger 197 times
197 Alarm will trigger 198 times
198 Alarm will trigger 199 times
199 Alarm will trigger 200 times
200 Alarm will trigger 201 times
201 Alarm will trigger 202 times
202 Alarm will trigger 203 times
203 Alarm will trigger 204 times
204 Alarm will trigger 205 times
205 Alarm will trigger 206 times
206 Alarm will trigger 207 times
207 Alarm will trigger 208 times
208 Alarm will trigger 209 times
209 Alarm will trigger 210 times
210 Alarm will trigger 211 times
211 Alarm will trigger 212 times
212 Alarm will trigger 213 times
213 Alarm will trigger 214 times
214 Alarm will trigger 215 times
215 Alarm will trigger 216 times
216 Alarm will trigger 217 times
217 Alarm will trigger 218 times
218 Alarm will trigger 219 times
219 Alarm will trigger 220 times
220 Alarm will trigger 221 times
221 Alarm will trigger 222 times
222 Alarm will trigger 223 times
223 Alarm will trigger 224 times
224 Alarm will trigger 225 times
225 Alarm will trigger 226 times
226 Alarm will trigger 227 times
227 Alarm will trigger 228 times
228 Alarm will trigger 229 times
229 Alarm will trigger 230 times
230 Alarm will trigger 231 times
231 Alarm will trigger 232 times
232 Alarm will trigger 233 times
233 Alarm will trigger 234 times
234 Alarm will trigger 235 times
235 Alarm will trigger 236 times
236 Alarm will trigger 237 times
237 Alarm will trigger 238 times
238 Alarm will trigger 239 times
239 Alarm will trigger 240 times
240 Alarm will trigger 241 times
241 Alarm will trigger 242 times
242 Alarm will trigger 243 times
243 Alarm will trigger 244 times
244 Alarm will trigger 245 times
245 Alarm will trigger 246 times
246 Alarm will trigger 247 times
247 Alarm will trigger 248 times
248 Alarm will trigger 249 times
249 Alarm will trigger 250 times
250 Alarm will trigger 251 times
251 Alarm will trigger 252 times
252 Alarm will trigger 253 times
253 Alarm will trigger 254 times
254 Alarm will trigger 255 times
255 Alarm will trigger 256 times
RTCTIMERTC Time Value Register
Address
0xBF800220
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
HR01
27:24
MIN10
23:20
MIN01
19:16
SEC10
15:12
SEC01
11:8
HR10
31:28
RTCDATERTC Date Value Register
Address
0xBF800230
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
YEAR01
27:24
MONTH10
23:20
MONTH01
19:16
DAY10
15:12
DAY01
11:8
WDAY01
3:0
YEAR10
31:28
ALRMTIMEAlarm Time Value Register
Address
0xBF800240
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
HR01
27:24
MIN10
23:20
MIN01
19:16
SEC10
15:12
SEC01
11:8
HR10
31:28
ALRMDATEAlarm Date Value Register
Address
0xBF800250
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
MONTH10
23:20
MONTH01
19:16
DAY10
15:12
DAY01
11:8
WDAY01
3:0
TMR1 Timer 1
T1CONTYPE A TIMER CONTROL REGISTER
Address
0xBF800600
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Timer is disabled
1 Timer is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TWDIS
12
Asynchronous Timer Write Disable bit
0 Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
1 Writes to TMR1 are ignored until pending write operation completes
TWIP
11
Asynchronous Timer Write in Progress bit
0 (In Asynchronous Timer mode) Asynchronous write to TMR1 register complete / (in synchronous mode) read as 0
1 (In Asynchronous Timer mode) Asynchronous write to TMR1 register in progress / (in synchronous mode) read as 0
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0) Gated time accumulation is disabled / (When TCS is 1) bit is ignored
1 (When TCS is 0) Gated time accumulation is enabled / (When TCS is 1) bit is ignored
TCKPS
5:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:8 prescale value
2 1:64 prescale value
3 1:256 prescale value
TSYNC
2
Timer External Clock Input Synchronization Selection bit
0 (When TCS is 1) External clock input is not synchronized / (When TCS is 0) bit is ignored
1 (When TCS is 1) External clock input is synchronized / (When TCS is 0) bit is ignored
TCS
1
Timer Clock Source Select bit
0 Internal peripheral clock
1 External clock from T1CKI pin
TMR1
Address
0xBF800610
Reset
0x00000000
Access
read/write
Size
32-bit
PR1
Address
0xBF800620
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR2 Timer 2
T2CONType B Timer Control Register
Address
0xBF800800
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 Gated time accumulation is disabled
1 Gated time accumulation is enabled
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
T32
3
32-Bit Timer Mode Select bit
0 Odd numbered and even numbered timers form separate 16-bit timers
1 Odd numbered and even numbered timers form a 32-bit timer
TMR2
Address
0xBF800810
Reset
0x00000000
Access
read/write
Size
32-bit
PR2
Address
0xBF800820
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR3 Timer 3
T3CONType B Timer Control Register
Address
0xBF800A00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 Gated time accumulation is disabled
1 Gated time accumulation is enabled
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
TMR3
Address
0xBF800A10
Reset
0x00000000
Access
read/write
Size
32-bit
PR3
Address
0xBF800A20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR4 Timer 4
T4CONType B Timer Control Register
Address
0xBF800C00
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 Gated time accumulation is disabled
1 Gated time accumulation is enabled
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
T32
3
32-Bit Timer Mode Select bit
0 Odd numbered and even numbered timers form separate 16-bit timers
1 Odd numbered and even numbered timers form a 32-bit timer
TMR4
Address
0xBF800C10
Reset
0x00000000
Access
read/write
Size
32-bit
PR4
Address
0xBF800C20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
TMR5 Timer 5
T5CONType B Timer Control Register
Address
0xBF800E00
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Module is disabled
1 Module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TGATE
7
Timer Gated Time Accumulation Enable bit
0 Gated time accumulation is disabled
1 Gated time accumulation is enabled
TCKPS
6:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:2 prescale value
2 1:4 prescale value
3 1:8 prescale value
4 1:16 prescale value
5 1:32 prescale value
6 1:64 prescale value
7 1:256 prescale value
TMR5
Address
0xBF800E10
Reset
0x00000000
Access
read/write
Size
32-bit
PR5
Address
0xBF800E20
Reset
0x0000FFFF
Access
read/write
Size
32-bit
IC1 Input capture 1
IC1CONInput Capture 1 Control Register
Address
0xBF802000
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit (read-only)
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit (read-only)
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC1BUF
Address
0xBF802010
Reset
0x00000000
Access
read only
Size
32-bit
IC2 Input capture 2
IC2CONInput Capture 1 Control Register
Address
0xBF802200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit (read-only)
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit (read-only)
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC2BUF
Address
0xBF802210
Reset
0x00000000
Access
read only
Size
32-bit
IC3 Input capture 3
IC3CONInput Capture 1 Control Register
Address
0xBF802400
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit (read-only)
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit (read-only)
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC3BUF
Address
0xBF802410
Reset
0x00000000
Access
read only
Size
32-bit
IC4 Input capture 4
IC4CONInput Capture 1 Control Register
Address
0xBF802600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit (read-only)
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit (read-only)
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC4BUF
Address
0xBF802610
Reset
0x00000000
Access
read only
Size
32-bit
IC5 Input capture 5
IC5CONInput Capture 1 Control Register
Address
0xBF802800
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit (read-only)
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit (read-only)
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
IC5BUF
Address
0xBF802810
Reset
0x00000000
Access
read only
Size
32-bit
OC1 Output compare 1
OC1CONOutput Compare 'x' Control Register
Address
0xBF803000
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ON
15
Output Compare Peripheral On bit
0 Output Compare peripheral is disabled
1 Output Compare peripheral is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when CPU enters Idle mode
OC32
5
32-bit Compare Mode bit
0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT
4
PWM Fault Condition Status bit
0 No PWM Fault condition has occurred
1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL
3
Output Compare Timer Select bit
0 Timer2 is the clock source for this Output Compare module
1 Timer3 is the clock source for this Output Compare module
OCM
2:0
Output Compare Mode Select bits
0 Output compare peripheral is disabled but continues to draw current
1 Interrupt generated at the end of the read/write cycle
2 Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA(1:0) =11 (Addressable Slave mode only)
3 Reserved
INCM
12:11
Increment Mode bits
0 No increment or decrement of address
1 Increment ADDR(15:0) by 1 every read/write cycle
2 Decrement ADDR(15:0) by 1 every read/write cycle
0 Legacy Parallel Slave Port (PMRD, PMWR, PMCS1, and PMD)
1 Enhanced Slave mode (PMRD, PMWR, PMCS1, PMD, and PMA)
2 Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD)
3 Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD)
WAITB
7:6
Data Setup to Read/Write Strobe Wait States bits
0 Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
1 Data wait of 2 TPB; multiplexed address phase of 2 TPB
2 Data wait of 3 TPB; multiplexed address phase of 3 TPB
3 Data wait of 4 TPB; multiplexed address phase of 4 TPB
WAITM
5:2
Data Read/Write Strobe Wait States bits
0 Wait of 1TPB (default)
1 Wait of 2TPB
2 Wait of 3TPB
3 Wait of 4TPB
4 Wait of 5TPB
5 Wait of 6TPB
6 Wait of 7TPB
7 Wait of 8TPB
8 Wait of 9TPB
9 Wait of 10TPB
10 Wait of 11TPB
11 Wait of 12TPB
12 Wait of 13TPB
13 Wait of 14TPB
14 Wait of 15TPB
15 Wait of 16TPB
WAITE
1:0
Data Hold After Read/Write Strobe Wait States bits
0 (for write operations) Wait of 1 TPB (default) / (for read operations) Wait of 0 TPB (default)
1 (for write operations) Wait of 2 TPB / (for read operations) Wait of 1 TPB
2 (for write operations) Wait of 3 TPB / (for read operations) Wait of 2 TPB
3 (for write operations) Wait of 4 TPB / (for read operations) Wait of 3 TPB
PMADDRParallel Port Address Register
Address
0xBF807020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CS
14
Chip Select bit
0 Chip Select 1 and 2 are inactive
1 Chip Select 1 is active, Chip Select 2 is inactive
2 Chip Select 1 is inactive, Chip Select 2 is active
3 Chip Select 1 and 2 are active
ADDR
13:0
PMDOUTParallel Port Output Data Register
Address
0xBF807030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATAOUT
31:0
Port Data Output bits
0 Data output is 0
PMDINParallel Port Input Data Register
Address
0xBF807040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATAIN
31:0
Port Data Input bits
0 Data input is 0
PMAENParallel Port Pin Enable Register
Address
0xBF807050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PTEN
15:0
PMALH/PMALL Strobe Enable bits
0 PMA14 functions as port I/O
0 PMA(10:2) function as port I/O
0 PMA1 and PMA0 pads function as port I/O
1 PMA1 and PMA0 function as either PMA(1:0) or PMALH and PMALL
4 PMA(10:2) function as PMP address lines
16384 PMA14 functions as either PMA(14) or PMCS1
PMSTATParallel Port Status Register (Slave modes only)
Address
0xBF807060
Reset
0x0000008F
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
IBF
15
Input Buffer Full Status bit
0 Some or all of the writable input buffer registers are empty
1 All writable input buffer registers are full
IBOV
14
Input Buffer Overflow Status bit
0 No overflow occurred
1 A write attempt to a full input byte buffer occurred (must be cleared in software)
IB3F
11
Input Buffer 3 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB2F
10
Input Buffer 2 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB1F
9
Input Buffer 1 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB0F
8
Input Buffer 0 Status Full bit
0 Input Buffer does not contain any unread data
1 Input Buffer contains data that has not been read (reading buffer will clear this bit)
OBE
7
Output Buffer Empty Status bit
0 Some or all of the readable output buffer registers are full
1 All readable output buffer registers are empty
OBUF
6
Output Buffer Underflow Status bit
0 No underflow occurred
1 A read occurred from an empty output byte buffer (must be cleared in software)
OB3E
3
Output Buffer 3 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB2E
2
Output Buffer 2 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB1E
1
Output Buffer 1 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
OB0E
0
Output Buffer 0 Status Empty bit
0 Output buffer contains data that has not been transmitted
1 Output buffer is empty (writing data to the buffer will clear this bit)
ADC Analog-to-digital converter
AD1CON1ADC Control Register 1
Address
0xBF809000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
ADC Operating Mode bit
0 ADC module is not operating
1 ADC module is operating
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
FORM
10:8
Data Output Format bits
0 Integer 16-bit
1 Signed Integer 16-bit
2 Fractional 16-bit
3 Signed Fractional 16-bit
4 Integer 32-bit
5 Signed Integer 32-bit
6 Fractional 32-bit
7 Signed Fractional 32-bit
SSRC
7:5
Conversion Trigger Source Select bits
0 Clearing SAMP bit ends sampling and starts conversion
1 Active transition on INT0 pin ends sampling and starts conversion
2 Timer 3 period match ends sampling and starts conversion
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Internal counter ends sampling and starts conversion (auto convert)
CLRASAM
4
Stop Conversion Sequence bit (when the first ADC interrupt is generated)
0 Normal operation, buffer contents will be overwritten by the next conversion sequence
1 Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
ASAM
2
ADC Sample Auto-Start bit
0 Sampling begins when SAMP bit is set
1 Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
SAMP
1
ADC Sample Enable bit
0 The ADC sample/hold amplifier is holding
1 The ADC sample and hold amplifier is sampling
DONE
0
Analog-to-Digital Conversion Status bit
0 Analog-to-digital conversion is not done or has not started
1 Analog-to-digital conversion is done
AD1CON2ADC Control Register 2
Address
0xBF809010
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
VCFG
15:13
Voltage Reference Configuration bits
0 VREFH is AVDD and VREFL is AVSS
1 VREFH is Ext VREF + pin and VREFL is AVSS
2 VREFH is AVDD and VREFL is External VREF- pin
3 VREFH is External VREF+ pin and VREFL is External VREF- pin
4 VREFH is AVDD and VREFL is AVSS
5 VREFH is AVDD and VREFL is AVSS
6 VREFH is AVDD and VREFL is AVSS
7 VREFH is AVDD and VREFL is AVSS
OFFCAL
12
Input Offset Calibration Mode Select bit
0 Disable Offset Calibration mode; The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL
1 Enable Offset Calibration mode; Positive and negative inputs of the sample and hold amplifier are connected to VREFL
CSCNA
10
Input Scan Select bit
0 Do not scan inputs
1 Scan inputs
BUFS
7
Buffer Fill Status bit
0 ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
1 ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
SMPI
5:2
Sample/Convert Sequences Per Interrupt Selection bits
0 Interrupts at the completion of conversion for each sample/convert sequence
1 Interrupts at the completion of conversion for each 2nd sample/convert sequence
2 Interrupts at the completion of conversion for each 3rd sample/convert sequence
3 Interrupts at the completion of conversion for each 4th sample/convert sequence
4 Interrupts at the completion of conversion for each 5th sample/convert sequence
5 Interrupts at the completion of conversion for each 6th sample/convert sequence
6 Interrupts at the completion of conversion for each 7th sample/convert sequence
7 Interrupts at the completion of conversion for each 8th sample/convert sequence
8 Interrupts at the completion of conversion for each 9th sample/convert sequence
9 Interrupts at the completion of conversion for each 10th sample/convert sequence
10 Interrupts at the completion of conversion for each 11th sample/convert sequence
11 Interrupts at the completion of conversion for each 12th sample/convert sequence
12 Interrupts at the completion of conversion for each 13th sample/convert sequence
13 Interrupts at the completion of conversion for each 14th sample/convert sequence
14 Interrupts at the completion of conversion for each 15th sample/convert sequence
15 Interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM
1
ADC Result Buffer Mode Select bit
0 Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
1 Buffer configured as two 8-word buffers ADC1BUF7-ADC1BUF0 / ADC1BUFF-ADCBUF8
ALTS
0
Alternate Input Sample Mode Select bit
0 Always use Sample A input multiplexer settings
1 Uses Sample A input multiplexer settings for first sample then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples
AD1CON3ADC Control Register 3
Address
0xBF809020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ADRC
15
ADC Conversion Clock Source bit
0 Clock derived from Peripheral Bus Clock (PBCLK)
1 Clock derived from FRC
SAMC
12:8
Auto-Sample Time bits
1 1 TAD
2 2 TAD
3 3 TAD
4 4 TAD
5 5 TAD
6 6 TAD
7 7 TAD
8 8 TAD
9 9 TAD
10 10 TAD
11 11 TAD
12 12 TAD
13 13 TAD
14 14 TAD
15 15 TAD
16 16 TAD
17 17 TAD
18 18 TAD
19 19 TAD
20 20 TAD
21 21 TAD
22 22 TAD
23 23 TAD
24 24 TAD
25 25 TAD
26 26 TAD
27 27 TAD
28 28 TAD
29 29 TAD
30 30 TAD
31 31 TAD
ADCS
7:0
ADC Conversion Clock Select bits
0 2*TPB
1 4*TPB
2 6*TPB
3 8*TPB
4 10*TPB
5 12*TPB
6 14*TPB
7 16*TPB
8 18*TPB
9 20*TPB
10 22*TPB
11 24*TPB
12 26*TPB
13 28*TPB
14 30*TPB
15 32*TPB
16 34*TPB
17 36*TPB
18 38*TPB
19 40*TPB
20 42*TPB
21 44*TPB
22 46*TPB
23 48*TPB
24 50*TPB
25 52*TPB
26 54*TPB
27 56*TPB
28 58*TPB
29 60*TPB
30 62*TPB
31 64*TPB
32 66*TPB
33 68*TPB
34 70*TPB
35 72*TPB
36 74*TPB
37 76*TPB
38 78*TPB
39 80*TPB
40 82*TPB
41 84*TPB
42 86*TPB
43 88*TPB
44 90*TPB
45 92*TPB
46 94*TPB
47 96*TPB
48 98*TPB
49 100*TPB
50 102*TPB
51 104*TPB
52 106*TPB
53 108*TPB
54 110*TPB
55 112*TPB
56 114*TPB
57 116*TPB
58 118*TPB
59 120*TPB
60 122*TPB
61 124*TPB
62 126*TPB
63 128*TPB
64 130*TPB
65 132*TPB
66 134*TPB
67 136*TPB
68 138*TPB
69 140*TPB
70 142*TPB
71 144*TPB
72 146*TPB
73 148*TPB
74 150*TPB
75 152*TPB
76 154*TPB
77 156*TPB
78 158*TPB
79 160*TPB
80 162*TPB
81 164*TPB
82 166*TPB
83 168*TPB
84 170*TPB
85 172*TPB
86 174*TPB
87 176*TPB
88 178*TPB
89 180*TPB
90 182*TPB
91 184*TPB
92 186*TPB
93 188*TPB
94 190*TPB
95 192*TPB
96 194*TPB
97 196*TPB
98 198*TPB
99 200*TPB
100 202*TPB
101 204*TPB
102 206*TPB
103 208*TPB
104 210*TPB
105 212*TPB
106 214*TPB
107 216*TPB
108 218*TPB
109 220*TPB
110 222*TPB
111 224*TPB
112 226*TPB
113 228*TPB
114 230*TPB
115 232*TPB
116 234*TPB
117 236*TPB
118 238*TPB
119 240*TPB
120 242*TPB
121 244*TPB
122 246*TPB
123 248*TPB
124 250*TPB
125 252*TPB
126 254*TPB
127 256*TPB
128 258*TPB
129 260*TPB
130 262*TPB
131 264*TPB
132 266*TPB
133 268*TPB
134 270*TPB
135 272*TPB
136 274*TPB
137 276*TPB
138 278*TPB
139 280*TPB
140 282*TPB
141 284*TPB
142 286*TPB
143 288*TPB
144 290*TPB
145 292*TPB
146 294*TPB
147 296*TPB
148 298*TPB
149 300*TPB
150 302*TPB
151 304*TPB
152 306*TPB
153 308*TPB
154 310*TPB
155 312*TPB
156 314*TPB
157 316*TPB
158 318*TPB
159 320*TPB
160 322*TPB
161 324*TPB
162 326*TPB
163 328*TPB
164 330*TPB
165 332*TPB
166 334*TPB
167 336*TPB
168 338*TPB
169 340*TPB
170 342*TPB
171 344*TPB
172 346*TPB
173 348*TPB
174 350*TPB
175 352*TPB
176 354*TPB
177 356*TPB
178 358*TPB
179 360*TPB
180 362*TPB
181 364*TPB
182 366*TPB
183 368*TPB
184 370*TPB
185 372*TPB
186 374*TPB
187 376*TPB
188 378*TPB
189 380*TPB
190 382*TPB
191 384*TPB
192 386*TPB
193 388*TPB
194 390*TPB
195 392*TPB
196 394*TPB
197 396*TPB
198 398*TPB
199 400*TPB
200 402*TPB
201 404*TPB
202 406*TPB
203 408*TPB
204 410*TPB
205 412*TPB
206 414*TPB
207 416*TPB
208 418*TPB
209 420*TPB
210 422*TPB
211 424*TPB
212 426*TPB
213 428*TPB
214 430*TPB
215 432*TPB
216 434*TPB
217 436*TPB
218 438*TPB
219 440*TPB
220 442*TPB
221 444*TPB
222 446*TPB
223 448*TPB
224 450*TPB
225 452*TPB
226 454*TPB
227 456*TPB
228 458*TPB
229 460*TPB
230 462*TPB
231 464*TPB
232 466*TPB
233 468*TPB
234 470*TPB
235 472*TPB
236 474*TPB
237 476*TPB
238 478*TPB
239 480*TPB
240 482*TPB
241 484*TPB
242 486*TPB
243 488*TPB
244 490*TPB
245 492*TPB
246 494*TPB
247 496*TPB
248 498*TPB
249 500*TPB
250 502*TPB
251 504*TPB
252 506*TPB
253 508*TPB
254 510*TPB
255 512*TPB
AD1CHSADC Input Select Register
Address
0xBF809040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CH0SB
27:24
Positive Input Select bits for Sample B
0 Channel 0 positive input is AN0
1 Channel 0 positive input is AN1
2 Channel 0 positive input is AN2
3 Channel 0 positive input is AN3
4 Channel 0 positive input is AN4
5 Channel 0 positive input is AN5
6 Channel 0 positive input is AN6
7 Channel 0 positive input is AN7
8 Channel 0 positive input is AN8
9 Channel 0 positive input is AN9
10 Channel 0 positive input is AN10
11 Channel 0 positive input is AN11
12 Channel 0 positive input is AN12
13 Channel 0 positive input is AN13
14 Channel 0 positive input is AN14
15 Channel 0 positive input is AN15
CH0NA
23
Negative Input Select bit for Sample A Multiplexer Setting
0 Channel 0 negative input is VREFL
1 Channel 0 negative input is AN1
CH0SA
19:16
Positive Input Select bits for Sample A Multiplexer Setting
0 Channel 0 positive input is AN0
1 Channel 0 positive input is AN1
2 Channel 0 positive input is AN2
3 Channel 0 positive input is AN3
4 Channel 0 positive input is AN4
5 Channel 0 positive input is AN5
6 Channel 0 positive input is AN6
7 Channel 0 positive input is AN7
8 Channel 0 positive input is AN8
9 Channel 0 positive input is AN9
10 Channel 0 positive input is AN10
11 Channel 0 positive input is AN11
12 Channel 0 positive input is AN12
13 Channel 0 positive input is AN13
14 Channel 0 positive input is AN14
15 Channel 0 positive input is AN15
CH0NB
31
Negative Input Select bit for Sample B
0 Channel 0 negative input is VREFL
1 Channel 0 negative input is AN1
AD1CSSLADC Input Scan Select Register
Address
0xBF809050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CSSL
15:0
AD1PCFG
Address
0xBF809060
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PCFG
15:0
ADC1BUF0
Address
0xBF809070
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF1
Address
0xBF809080
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF2
Address
0xBF809090
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF3
Address
0xBF8090A0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF4
Address
0xBF8090B0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF5
Address
0xBF8090C0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF6
Address
0xBF8090D0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF7
Address
0xBF8090E0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF8
Address
0xBF8090F0
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUF9
Address
0xBF809100
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFA
Address
0xBF809110
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFB
Address
0xBF809120
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFC
Address
0xBF809130
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFD
Address
0xBF809140
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFE
Address
0xBF809150
Reset
0x00000000
Access
read only
Size
32-bit
ADC1BUFF
Address
0xBF809160
Reset
0x00000000
Access
read only
Size
32-bit
CVR Comparator voltage reference
CVRCONComparator Voltage Reference Control Register
Address
0xBF809800
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ON
15
Comparator Voltage Reference On bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in the register.
1 Module is enabled. Setting this bit does not affect other bits in the register.
CVROE
6
CVrefout Enable bit
0 Voltage level is disconnected from CVrefout pin
1 Voltage level is output on CVrefout pin
CVRR
5
CVref Range Selection bit
0 0.25 CVrsrc to 0.75 CVrsrc with CVrsrc/32 step size
1 0 to 0.67 CVrsrc with CVrsrc/24 step size
CVRSS
4
CVref Source Selection bit
0 Comparator voltage reference source CVrsrc = AVdd - AVss
1 Comparator voltage reference source CVrsrc = (Vref+) - (Vref-)
CVR
3:0
CVref Value Selection
0 (When CVRR is 1) CVREF is (0/24) * CVRSRC / (When CVRR is 0) CVREF is (8/32)*CVRSRC
1 (When CVRR is 1) CVREF is (1/24) * CVRSRC / (When CVRR is 0) CVREF is (9/32)*CVRSRC
2 (When CVRR is 1) CVREF is (2/24) * CVRSRC / (When CVRR is 0) CVREF is (10/32)*CVRSRC
3 (When CVRR is 1) CVREF is (3/24) * CVRSRC / (When CVRR is 0) CVREF is (11/32)*CVRSRC
4 (When CVRR is 1) CVREF is (4/24) * CVRSRC / (When CVRR is 0) CVREF is (12/32)*CVRSRC
5 (When CVRR is 1) CVREF is (5/24) * CVRSRC / (When CVRR is 0) CVREF is (13/32)*CVRSRC
6 (When CVRR is 1) CVREF is (6/24) * CVRSRC / (When CVRR is 0) CVREF is (14/32)*CVRSRC
7 (When CVRR is 1) CVREF is (7/24) * CVRSRC / (When CVRR is 0) CVREF is (15/32)*CVRSRC
8 (When CVRR is 1) CVREF is (8/24) * CVRSRC / (When CVRR is 0) CVREF is (16/32)*CVRSRC
9 (When CVRR is 1) CVREF is (9/24) * CVRSRC / (When CVRR is 0) CVREF is (17/32)*CVRSRC
10 (When CVRR is 1) CVREF is (10/24) * CVRSRC / (When CVRR is 0) CVREF is (18/32)*CVRSRC
11 (When CVRR is 1) CVREF is (11/24) * CVRSRC / (When CVRR is 0) CVREF is (19/32)*CVRSRC
12 (When CVRR is 1) CVREF is (12/24) * CVRSRC / (When CVRR is 0) CVREF is (20/32)*CVRSRC
13 (When CVRR is 1) CVREF is (13/24) * CVRSRC / (When CVRR is 0) CVREF is (21/32)*CVRSRC
14 (When CVRR is 1) CVREF is (14/24) * CVRSRC / (When CVRR is 0) CVREF is (22/32)*CVRSRC
15 (When CVRR is 1) CVREF is (15/24) * CVRSRC / (When CVRR is 0) CVREF is (23/32)*CVRSRC
CMP1 Comparator 1
CM1CONComparator Control Register
Address
0xBF80A000
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ON
15
Comparator ON bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
1 Module is enabled. Setting this bit does not affect the other bits in this register
COE
14
Comparator Output Enable bit
0 Comparator output is not driven on the output CxOUT pin
1 Comparator output is driven on the output CxOUT pin
CPOL
13
Comparator Output Inversion bit
0 Output is not inverted
1 Output is inverted
COUT
8
Comparator Output bit
0 Output of the Comparator is a 0
1 Output of the Comparator is a 1
EVPOL
7:6
Interrupt Event Polarity Select bits
0 Comparator interrupt generation is disabled
1 Comparator interrupt is generated on a low-to-high transition of the comparator output
2 Comparator interrupt is generated on a high-to-low transition of the comparator output
3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF
4
Comparator Positive Input Configure bit
0 Comparator non-inverting input is connected to the C1IN+ pin
1 Comparator non-inverting input is connected to the internal CVREF
CCH
1:0
Comparator Negative Input Select bits for Comparator
0 Comparator inverting input is connected to the C1IN- pin
1 Comparator inverting input is connected to the C1IN+ pin
2 Comparator inverting input is connected to the C2IN+ pin
3 Comparator inverting input is connected to the IVREF
CMP2 Comparator 2
CM2CONComparator Control Register
Address
0xBF80A010
Reset
0x000000C3
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ON
15
Comparator ON bit
0 Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register
1 Module is enabled. Setting this bit does not affect the other bits in this register
COE
14
Comparator Output Enable bit
0 Comparator output is not driven on the output CxOUT pin
1 Comparator output is driven on the output CxOUT pin
CPOL
13
Comparator Output Inversion bit
0 Output is not inverted
1 Output is inverted
COUT
8
Comparator Output bit
0 Output of the Comparator is a 0
1 Output of the Comparator is a 1
EVPOL
7:6
Interrupt Event Polarity Select bits
0 Comparator interrupt generation is disabled
1 Comparator interrupt is generated on a low-to-high transition of the comparator output
2 Comparator interrupt is generated on a high-to-low transition of the comparator output
3 Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
CREF
4
Comparator Positive Input Configure bit
0 Comparator non-inverting input is connected to the C2IN+ pin
1 Comparator non-inverting input is connected to the internal CVREF
CCH
1:0
Comparator Negative Input Select bits for Comparator
0 Comparator inverting input is connected to the C2IN- pin
1 Comparator inverting input is connected to the C2IN+ pin
2 Comparator inverting input is connected to the C1IN+ pin
3 Comparator inverting input is connected to the IVREF
CMP Comparator
CMSTATComparator Status Register
Address
0xBF80A060
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
SIDL
13
Stop in Idle Control bit
0 All Comparator modules continue to operate in the Idle mode
1 All Comparator modules are disabled in Idle mode
C2OUT
1
Comparator Output bit
0 Output of Comparator 2 is a 0
1 Output of Comparator 2 is a 1
C1OUT
0
Comparator Output bit
0 Output of Comparator 1 is a 0
1 Output of Comparator 1 is a 1
OSC Oscillator and clocks
OSCCONOscillator Control Register
Address
0xBF80F000
Reset
0x00000007
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
PLLODIV
29:27
Output Divider for PLL
0 PLL output divided by 1
1 PLL output divided by 2
2 PLL output divided by 4
3 PLL output divided by 8
4 PLL output divided by 16
5 PLL output divided by 32
6 PLL output divided by 64
7 PLL output divided by 256
FRCDIV
26:24
Internal Fast RC Oscillator Clock Divider bits
0 FRC divided by 1
1 FRC divided by 2 (default setting)
2 FRC divided by 4
3 FRC divided by 8
4 FRC divided by 16
5 FRC divided by 32
6 FRC divided by 64
7 FRC divided by 256
SOSCRDY
22
Secondary Oscillator (SOSC) Ready Indicator bit
0 Secondary Oscillator is still warming up or is turned off
1 Indicates that the Secondary Oscillator is running and is stable
PBDIV
20:19
Peripheral Bus Clock (PBCLK) Divisor bits
0 PBCLK is SYSCLK divided by 1
1 PBCLK is SYSCLK divided by 2
2 PBCLK is SYSCLK divided by 4
3 PBCLK is SYSCLK divided by 8 (default)
PLLMULT
18:16
Phase-Locked Loop (PLL) Multiplier bits
0 Clock is multiplied by 15
1 Clock is multiplied by 16
2 Clock is multiplied by 17
3 Clock is multiplied by 18
4 Clock is multiplied by 19
5 Clock is multiplied by 20
6 Clock is multiplied by 21
7 Clock is multiplied by 24
COSC
14:12
Current Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator
1 Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
2 Primary Oscillator (POSC) (XT/HS/EC)
3 Primary Oscillator (POSC) with PLL module (XTPLL/HSPLL/ECPLL)
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Internal Fast RC (FRC) Oscillator divided by 16
7 Internal Fast RC (FRC) Oscillator divided by OSCCON(FRCDIV) bits
NOSC
10:8
New Oscillator Selection bits
0 Internal Fast Internal RC Oscillator (FRC)
1 Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
2 Primary Oscillator (XT/HS/EC)
3 Primary Oscillator with PLL module (XTPLL/HSPLL/ECPLL)
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Internal Fast RC Oscillator (FRC) divided by 16
7 Internal Fast RC Oscillator (FRC) divided by OSCCON(FRCDIV) bits
CLKLOCK
7
Clock Selection Lock Enable bit
0 (If FCKSM(1:0) is 1x) Clock and PLL selections are not locked and may be modified / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
1 (If FCKSM(1:0) is 1x) Clock and PLL selections are locked / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
ULOCK
6
USB PLL Lock Status bit
0 Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled
1 Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
LOCK
5
PLL Lock Status bit
0 PLL module is out of lock
1 PLL module is in lock or PLL module start-up timer is satisfied
SLPEN
4
Sleep Mode Enable bit
0 Device will enter Idle mode when a WAIT instruction is executed
1 Device will enter Sleep mode when a WAIT instruction is executed
CF
3
Clock Fail Detect bit
0 No clock failure has been detected
1 FSCM has detected a clock failure
UFRCEN
2
USB FRC Clock Enable bit
0 Use the Primary Oscillator or USB PLL as the USB clock source
1 Enable FRC as the clock source for the USB clock source
SOSCEN
1
Secondary Oscillator Enable bit
0 Disable Secondary Oscillator
1 Enable Secondary Oscillator
OSWEN
0
Oscillator Switch Enable bit
0 Oscillator switch is complete
1 Initiate an oscillator switch to selection specified by NOSC(2:0) bits
OSCTUNFRC Tuning Register
Address
0xBF80F010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TUN
5:0
FRC Oscillator Tuning bits
0 Center frequency. Oscillator runs at minimal frequency (8 MHz)
31 Center frequency + 12.5%
32 Center frequency - 12.5%
CFG Configuration and pin control
DDPCON
Address
0xBF80F200
Reset
0x00000008
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
JTAGEN
3
JTAG Port Enable bit
0 Disable the JTAG port
1 Enable the JTAG port
TROEN
2
Trace Output Enable bit
0 Disable trace outputs and stop trace clock
1 Enable trace outputs and start trace clock (trace probe must be present)
DEVID
Address
0xBF80F220
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
VER
28
DEVID
27:0
SYSKEY
Address
0xBF80F230
Reset
0x00000000
Access
read only
Size
32-bit
NVM Flash controller (NVM)
NVMCONProgramming Control Register
Address
0xBF80F400
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
WR
15
Write Control bit
0 Flash operation complete or inactive
1 Initiate a Flash operation. Hardware clears this bit when the operation completes
WREN
14
Write Enable bit
0 Disable writes to WR bit and disables LVD circuit
1 Enable writes to WR bit and enables LVD circuit
WRERR
13
Write Error bit
0 Program or erase sequence completed normally
1 Program or erase sequence did not complete successfully
LVDERR
12
Low-Voltage Detect Error bit (LVD circuit must be enabled)
0 Voltage level is acceptable for programming
1 Low-voltage detected (possible data corruption if WRERR is set)
LVDSTAT
11
Low-Voltage Detect Status bit (LVD circuit must be enabled)
0 Low-voltage event NOT active
1 Low-voltage event active
NVMOP
3:0
NVM Operation bits
0 No operation
1 Word program operation: programs word selected by NVMADDR if it is not write-protected
2 No operation
3 Row program operation: programs row selected by NVMADDR if it is not write-protected
4 Page erase operation: erases page selected by NVMADDR if it is not write-protected
5 Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
6 No operation
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
NVMKEYProgramming Unlock Register
Address
0xBF80F410
Reset
0x00000000
Access
write only
Size
32-bit
NVMADDRFlash Address Register
Address
0xBF80F420
Reset
0x00000000
Access
read/write
Size
32-bit
NVMDATA
Address
0xBF80F430
Reset
0x00000000
Access
read/write
Size
32-bit
NVMSRCADDRSource Data Address Register
Address
0xBF80F440
Reset
0x00000000
Access
read/write
Size
32-bit
RCON Reset control
RCONReset Control Register
Address
0xBF80F600
Reset
0x00000003
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
CMR
9
Configuration Mismatch Reset Flag bit
0 Configuration mismatch Reset has not occurred
1 Configuration mismatch Reset has occurred
VREGS
8
Voltage Regulator Standby Enable bit
0 Regulator is set to standby tracking mode
1 Regulator is enabled and is on during Sleep mode
EXTR
7
External Reset (MCLR) Pin Flag bit
0 Master Clear (pin) Reset has not occurred
1 Master Clear (pin) Reset has occurred
SWR
6
Software Reset Flag bit
0 Software Reset as not executed
1 Software Reset was executed
WDTO
4
Watchdog Timer Time-out Flag bit
0 WDT Time-out has not occurred
1 WDT Time-out has occurred
SLEEP
3
Wake From Sleep Flag bit
0 Device was not in Sleep mode
1 Device was in Sleep mode
IDLE
2
Wake From Idle Flag bit
0 Device was not in Idle mode
1 Device was in Idle mode
BOR
1
Brown-out Reset Flag bit
0 Brown-out Reset has not occurred
1 Brown-out Reset has occurred
POR
0
Power-on Reset Flag bit
0 Power-on Reset has not occurred
1 Power-on Reset has occurred
RSWRSTSoftware Reset Register
Address
0xBF80F610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SWRST
0
Software Reset Trigger bit
0 No effect
1 Enable Software Reset event
DDPSTAT DDPSTAT
_DDPSTAT
Address
0xBF880140
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
STOV
16
APOOV
10
APIOV
9
STRFUL
3
APOFUL
2
APIFUL
1
_STROGeorge
Address
0xBF880170
Reset
0x00000000
Access
read/write
Size
32-bit
_APPOGeorge
Address
0xBF880180
Reset
0x00000000
Access
read/write
Size
32-bit
_APPIGeorge
Address
0xBF880190
Reset
0x00000000
Access
read/write
Size
32-bit
INT Interrupt controller
INTCONInterrupt Control Register
Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SS0
16
0 Single vector is not presented with a shadow register set
1 Single vector is presented with a shadow register set
MVEC
12
Multi Vector Configuration bit
0 Interrupt controller configured for Single-vectored mode
1 Interrupt controller configured for Multi-vectored mode
TPC
10:8
Interrupt Proximity Timer Control bits
0 Disables Interrupt Proximity timer
1 Interrupts of group priority 1 start the Interrupt Proximity timer
2 Interrupts of group priority 2 or lower start the Interrupt Proximity timer
3 Interrupts of group priority 3 or lower start the Interrupt Proximity timer
4 Interrupts of group priority 4 or lower start the Interrupt Proximity timer
5 Interrupts of group priority 5 or lower start the Interrupt Proximity timer
6 Interrupts of group priority 6 or lower start the Interrupt Proximity timer
7 Interrupts of group priority 7 or lower start the Interrupt Proximity timer
INT4EP
4
External Interrupt 4 Edge
0 Falling edge
1 Rising edge
INT3EP
3
External Interrupt 3 Edge
0 Falling edge
1 Rising edge
INT2EP
2
External Interrupt 2 Edge
0 Falling edge
1 Rising edge
INT1EP
1
External Interrupt 1 Edge
0 Falling edge
1 Rising edge
INT0EP
0
External Interrupt 0 Edge
0 Falling edge
1 Rising edge
INTSTAT
Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
RIPL
10:8
VEC
5:0
Interrupt Vector bits
0 The interrupt vector that is presented to the CPU is 0
1 The interrupt vector that is presented to the CPU is 1
2 The interrupt vector that is presented to the CPU is 2
3 The interrupt vector that is presented to the CPU is 3
4 The interrupt vector that is presented to the CPU is 4
5 The interrupt vector that is presented to the CPU is 5
6 The interrupt vector that is presented to the CPU is 6
7 The interrupt vector that is presented to the CPU is 7
8 The interrupt vector that is presented to the CPU is 8
9 The interrupt vector that is presented to the CPU is 9
10 The interrupt vector that is presented to the CPU is 10
11 The interrupt vector that is presented to the CPU is 11
12 The interrupt vector that is presented to the CPU is 12
13 The interrupt vector that is presented to the CPU is 13
14 The interrupt vector that is presented to the CPU is 14
15 The interrupt vector that is presented to the CPU is 15
16 The interrupt vector that is presented to the CPU is 16
17 The interrupt vector that is presented to the CPU is 17
18 The interrupt vector that is presented to the CPU is 18
19 The interrupt vector that is presented to the CPU is 19
20 The interrupt vector that is presented to the CPU is 20
21 The interrupt vector that is presented to the CPU is 21
22 The interrupt vector that is presented to the CPU is 22
23 The interrupt vector that is presented to the CPU is 23
24 The interrupt vector that is presented to the CPU is 24
25 The interrupt vector that is presented to the CPU is 25
26 The interrupt vector that is presented to the CPU is 26
27 The interrupt vector that is presented to the CPU is 27
28 The interrupt vector that is presented to the CPU is 28
29 The interrupt vector that is presented to the CPU is 29
30 The interrupt vector that is presented to the CPU is 30
31 The interrupt vector that is presented to the CPU is 31
IPTMR
Address
0xBF881020
Reset
0x00000000
Access
read/write
Size
32-bit
IFS0Interrupt Flag Status Register 0
Address
0xBF881030
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
I2C1SIF
30
I2C1BIF
29
U1TXIF
28
U1RXIF
27
U1EIF
26
SPI1RXIF
25
SPI1TXIF
24
SPI1EIF
23
OC5IF
22
IC5IF
21
T5IF
20
INT4IF
19
OC4IF
18
IC4IF
17
T4IF
16
INT3IF
15
OC3IF
14
IC3IF
13
T3IF
12
INT2IF
11
OC2IF
10
IC2IF
9
T2IF
8
INT1IF
7
OC1IF
6
IC1IF
5
T1IF
4
INT0IF
3
CS1IF
2
CS0IF
1
CTIF
0
I2C1MIF
31
IFS1
Address
0xBF881040
Reset
0x00000000
Access
read/write
Size
32-bit
21 fields
Field
Bits
What it does
FCEIF
24
DMA3IF
19
DMA2IF
18
DMA1IF
17
DMA0IF
16
RTCCIF
15
FSCMIF
14
I2C2MIF
13
I2C2SIF
12
I2C2BIF
11
U2TXIF
10
U2RXIF
9
U2EIF
8
SPI2RXIF
7
SPI2TXIF
6
SPI2EIF
5
CMP2IF
4
CMP1IF
3
PMPIF
2
AD1IF
1
CNIF
0
IEC0Interrupt Enable Control Register 0
Address
0xBF881060
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
I2C1SIE
30
I2C1BIE
29
U1TXIE
28
U1RXIE
27
U1EIE
26
SPI1RXIE
25
SPI1TXIE
24
SPI1EIE
23
OC5IE
22
IC5IE
21
T5IE
20
INT4IE
19
OC4IE
18
IC4IE
17
T4IE
16
INT3IE
15
OC3IE
14
IC3IE
13
T3IE
12
INT2IE
11
OC2IE
10
IC2IE
9
T2IE
8
INT1IE
7
OC1IE
6
IC1IE
5
T1IE
4
INT0IE
3
CS1IE
2
CS0IE
1
CTIE
0
I2C1MIE
31
IEC1nterrupt Enable Control Register 1
Address
0xBF881070
Reset
0x00000000
Access
read/write
Size
32-bit
21 fields
Field
Bits
What it does
FCEIE
24
DMA3IE
19
DMA2IE
18
DMA1IE
17
DMA0IE
16
RTCCIE
15
FSCMIE
14
I2C2MIE
13
I2C2SIE
12
I2C2BIE
11
U2TXIE
10
U2RXIE
9
U2EIE
8
SPI2RXIE
7
SPI2TXIE
6
SPI2EIE
5
CMP2IE
4
CMP1IE
3
PMPIE
2
AD1IE
1
CNIE
0
IPC0Interrupt Priority Control Register 0
Address
0xBF881090
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT0IP
28:26
INT0IS
25:24
CS1IP
20:18
CS1IS
17:16
CS0IP
12:10
CS0IS
9:8
CTIP
4:2
CTIS
1:0
IPC1Interrupt Priority Control Register 1
Address
0xBF8810A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT1IP
28:26
INT1IS
25:24
OC1IP
20:18
OC1IS
17:16
IC1IP
12:10
IC1IS
9:8
T1IP
4:2
T1IS
1:0
IPC2Interrupt Priority Control Register 2
Address
0xBF8810B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT2IP
28:26
INT2IS
25:24
OC2IP
20:18
OC2IS
17:16
IC2IP
12:10
IC2IS
9:8
T2IP
4:2
T2IS
1:0
IPC3Interrupt Priority Control Register 3
Address
0xBF8810C0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT3IP
28:26
INT3IS
25:24
OC3IP
20:18
OC3IS
17:16
IC3IP
12:10
IC3IS
9:8
T3IP
4:2
T3IS
1:0
IPC4Interrupt Priority Control Register 4
Address
0xBF8810D0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
INT4IP
28:26
INT4IS
25:24
OC4IP
20:18
OC4IS
17:16
IC4IP
12:10
IC4IS
9:8
T4IP
4:2
T4IS
1:0
IPC5Interrupt Priority Control Register 5
Address
0xBF8810E0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SPI1IP
28:26
SPI1IS
25:24
OC5IP
20:18
OC5IS
17:16
IC5IP
12:10
IC5IS
9:8
T5IP
4:2
T5IS
1:0
IPC6Interrupt Priority Control Register 6
Address
0xBF8810F0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
AD1IP
28:26
AD1IS
25:24
CNIP
20:18
CNIS
17:16
I2C1IP
12:10
I2C1IS
9:8
U1IP
4:2
U1IS
1:0
IPC7Interrupt Priority Control Register 7
Address
0xBF881100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SPI2IP
28:26
SPI2IS
25:24
CMP2IP
20:18
CMP2IS
17:16
CMP1IP
12:10
CMP1IS
9:8
PMPIP
4:2
PMPIS
1:0
IPC8Interrupt Priority Control Register 8
Address
0xBF881110
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RTCCIP
28:26
RTCCIS
25:24
FSCMIP
20:18
FSCMIS
17:16
I2C2IP
12:10
I2C2IS
9:8
U2IP
4:2
U2IS
1:0
IPC9Interrupt Priority Control Register 9
Address
0xBF881120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DMA3IP
28:26
DMA3IS
25:24
DMA2IP
20:18
DMA2IS
17:16
DMA1IP
12:10
DMA1IS
9:8
DMA0IP
4:2
DMA0IS
1:0
IPC11Interrupt Priority Control Register 11
Address
0xBF881140
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
FCEIP
4:2
FCEIS
1:0
BMX Bus matrix
BMXCONBus Matrix Configuration Register
Address
0xBF882000
Reset
0x001F0041
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BMXCHEDMA
26
BMX PFM Cacheability for DMA Accesses bit
0 Disable program Flash memory (data) cacheability for DMA accesses(hits are still read from the cache
1 Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled)
BMXERRIXI
20
Enable Bus Error from IXI bit
0 Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
1 Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD
19
Enable Bus Error from ICD Debug Unit bit
0 Disable bus error exceptions for unmapped address accesses initiated from ICD
1 Enable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA
18
Bus Error from DMA bit
0 Disable bus error exceptions for unmapped address accesses initiated from DMA
1 Enable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS
17
Bus Error from CPU Data Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU data access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS
16
Bus Error from CPU Instruction Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
BMXWSDRM
6
CPU Instruction or Data Access from Data RAM Wait State bit
0 Data RAM accesses from CPU have zero wait states for address setup
1 Data RAM accesses from CPU have one wait state for address setup
BMXARB
2:0
Bus Matrix Arbitration Mode bits
0 Arbitration Mode 0
1 Arbitration Mode 1 (default)
2 Arbitration Mode 2
3 Reserved (using these configuration modes will produce undefined behavior)
4 Reserved (using these configuration modes will produce undefined behavior)
5 Reserved (using these configuration modes will produce undefined behavior)
6 Reserved (using these configuration modes will produce undefined behavior)
7 Reserved (using these configuration modes will produce undefined behavior)
BMXDKPBAData RAM Kernel Program Base Address Register
Address
0xBF882010
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUDBAData RAM User Data Base Address Register
Address
0xBF882020
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUPBAData RAM User Program Base Address Register
Address
0xBF882030
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDRMSZData RAM Size Register
Address
0xBF882040
Reset
0x00020000
Access
read only
Size
32-bit
BMXPUPBAProgram Flash (PFM) User Program Base Address Register
Address
0xBF882050
Reset
0x00000000
Access
read/write
Size
32-bit
BMXPFMSZProgram Flash (PFM) Size Register
Address
0xBF882060
Reset
0x00080000
Access
read only
Size
32-bit
BMXBOOTSZBoot Flash (IFM) Size Register
Address
0xBF882070
Reset
0x00003000
Access
read only
Size
32-bit
DMAC DMA controller
DMACONDMA Controller Control Register
Address
0xBF883000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
DMA On bit
0 DMA module is disabled
1 DMA module is enabled
SIDL
13
SUSPEND
12
DMA Suspend bit
0 DMA operates normally
1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMASTAT
Address
0xBF883010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
RDWR
3
Read/Write Status bit
0 Last DMA bus access was a write
1 Last DMA bus access was a read
DMACH
1:0
DMAADDRDMA Address Register
Address
0xBF883020
Reset
0x00000000
Access
read only
Size
32-bit
DCRCCONDMA CRC Control Register
Address
0xBF883030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BYTO
29:28
CRC Byte Order Selection bits
0 No swapping (i.e. source byte order)
1 Endian byte swap on word boundaries (i.e. reverse source byte order)
2 Swap half-words on word boundaries (i.e. reverse source half-word order with source byte order per half-word)
3 Endian byte swap on half-word boundaries (i.e. source half-word order with reverse source byte order per half-word)
WBO
27
CRC Write Byte Order Selection bit
0 Source data is written to the destination unaltered
1 Source data is written to the destination re-ordered as defined by BYTO
BITO
24
CRC Bit Order Selection bit
0 (When CRCTYP is 1) The IP header checksum is calculated Most Significant bit (MSb) first (i.e. not reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Most Significant bit first (i.e. not reflected)
1 (When CRCTYP is 1) The IP header checksum is calculated Least Significant bit (LSb) first (i.e. reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Least Significant bit first (i.e. reflected)
PLEN
11:8
Polynomial Length bits
0 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 1
1 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 2
2 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 3
3 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 4
4 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 5
5 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 6
6 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 7
7 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 8
8 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 9
9 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 10
10 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 11
11 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 12
12 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 13
13 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 14
14 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 15
15 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 16
CRCEN
7
CRC Enable bit
0 CRC module is disabled and channel transfers proceed normally
1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP
6
CRC Append Mode bit
0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP
5
CRC Type Selection bit
0 The CRC module will calculate a LFSR CRC
1 The CRC module will calculate an IP header checksum
CRCCH
1:0
CRC Channel Select bits
0 CRC is assigned to Channel 0
1 CRC is assigned to Channel 1
2 CRC is assigned to Channel 2
3 CRC is assigned to Channel 3
DCRCDATADMA CRC Data Register
Address
0xBF883040
Reset
0x00000000
Access
read/write
Size
32-bit
DCRCXORDMA CRCXOR Enable Register
Address
0xBF883050
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0 DMA channel 0
DCH0CONDMA Channel x Control Register
Address
0xBF883060
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH0ECONDMA Channel x Event Control Register
Address
0xBF883070
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH0INTDMA Channel x Interrupt Control Register
Address
0xBF883080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH0SSADMA Channel x Source Start Address Register
Address
0xBF883090
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DSADMA Channel x Destination Start Address Register
Address
0xBF8830A0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0SSIZDMA Channel x Source Size Register
Address
0xBF8830B0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DSIZDMA Channel x Destination Size Register
Address
0xBF8830C0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0SPTRDMA Channel x Source Pointer Register
Address
0xBF8830D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DPTRDMA Channel x Destination Pointer Register
Address
0xBF8830E0
Reset
0x00000000
Access
read only
Size
32-bit
DCH0CSIZDMA Channel x Cell-Size Register
Address
0xBF8830F0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0CPTRDMA Channel x Cell Pointer Register
Address
0xBF883100
Reset
0x00000000
Access
read/write
Size
32-bit
DCH0DATDMA Channel x Pattern Data Register
Address
0xBF883110
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1 DMA channel 1
DCH1CONDMA Channel x Control Register
Address
0xBF883120
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH1ECONDMA Channel x Event Control Register
Address
0xBF883130
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH1INTDMA Channel x Interrupt Control Register
Address
0xBF883140
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH1SSADMA Channel x Source Start Address Register
Address
0xBF883150
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DSADMA Channel x Destination Start Address Register
Address
0xBF883160
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1SSIZDMA Channel x Source Size Register
Address
0xBF883170
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DSIZDMA Channel x Destination Size Register
Address
0xBF883180
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1SPTRDMA Channel x Source Pointer Register
Address
0xBF883190
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DPTRDMA Channel x Destination Pointer Register
Address
0xBF8831A0
Reset
0x00000000
Access
read only
Size
32-bit
DCH1CSIZDMA Channel x Cell-Size Register
Address
0xBF8831B0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1CPTRDMA Channel x Cell Pointer Register
Address
0xBF8831C0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH1DATDMA Channel x Pattern Data Register
Address
0xBF8831D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2 DMA channel 2
DCH2CONDMA Channel x Control Register
Address
0xBF8831E0
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH2ECONDMA Channel x Event Control Register
Address
0xBF8831F0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH2INTDMA Channel x Interrupt Control Register
Address
0xBF883200
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH2SSADMA Channel x Source Start Address Register
Address
0xBF883210
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DSADMA Channel x Destination Start Address Register
Address
0xBF883220
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2SSIZDMA Channel x Source Size Register
Address
0xBF883230
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DSIZDMA Channel x Destination Size Register
Address
0xBF883240
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2SPTRDMA Channel x Source Pointer Register
Address
0xBF883250
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DPTRDMA Channel x Destination Pointer Register
Address
0xBF883260
Reset
0x00000000
Access
read only
Size
32-bit
DCH2CSIZDMA Channel x Cell-Size Register
Address
0xBF883270
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2CPTRDMA Channel x Cell Pointer Register
Address
0xBF883280
Reset
0x00000000
Access
read/write
Size
32-bit
DCH2DATDMA Channel x Pattern Data Register
Address
0xBF883290
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3 DMA channel 3
DCH3CONDMA Channel x Control Register
Address
0xBF8832A0
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered even if the channel is disabled
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled and not automatically disabled after a block transfer is complete
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
DCH3ECONDMA Channel x Event Control Register
Address
0xBF8832B0
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
2 Interrupt 2 will abort any transfers in progress and set CHAIF flag
3 Interrupt 3 will abort any transfers in progress and set CHAIF flag
4 Interrupt 4 will abort any transfers in progress and set CHAIF flag
5 Interrupt 5 will abort any transfers in progress and set CHAIF flag
6 Interrupt 6 will abort any transfers in progress and set CHAIF flag
7 Interrupt 7 will abort any transfers in progress and set CHAIF flag
8 Interrupt 8 will abort any transfers in progress and set CHAIF flag
9 Interrupt 9 will abort any transfers in progress and set CHAIF flag
10 Interrupt 10 will abort any transfers in progress and set CHAIF flag
11 Interrupt 11 will abort any transfers in progress and set CHAIF flag
12 Interrupt 12 will abort any transfers in progress and set CHAIF flag
13 Interrupt 13 will abort any transfers in progress and set CHAIF flag
14 Interrupt 14 will abort any transfers in progress and set CHAIF flag
15 Interrupt 15 will abort any transfers in progress and set CHAIF flag
16 Interrupt 16 will abort any transfers in progress and set CHAIF flag
17 Interrupt 17 will abort any transfers in progress and set CHAIF flag
18 Interrupt 18 will abort any transfers in progress and set CHAIF flag
19 Interrupt 19 will abort any transfers in progress and set CHAIF flag
20 Interrupt 20 will abort any transfers in progress and set CHAIF flag
21 Interrupt 21 will abort any transfers in progress and set CHAIF flag
22 Interrupt 22 will abort any transfers in progress and set CHAIF flag
23 Interrupt 23 will abort any transfers in progress and set CHAIF flag
24 Interrupt 24 will abort any transfers in progress and set CHAIF flag
25 Interrupt 25 will abort any transfers in progress and set CHAIF flag
26 Interrupt 26 will abort any transfers in progress and set CHAIF flag
27 Interrupt 27 will abort any transfers in progress and set CHAIF flag
28 Interrupt 28 will abort any transfers in progress and set CHAIF flag
29 Interrupt 29 will abort any transfers in progress and set CHAIF flag
30 Interrupt 30 will abort any transfers in progress and set CHAIF flag
31 Interrupt 31 will abort any transfers in progress and set CHAIF flag
32 Interrupt 32 will abort any transfers in progress and set CHAIF flag
33 Interrupt 33 will abort any transfers in progress and set CHAIF flag
34 Interrupt 34 will abort any transfers in progress and set CHAIF flag
35 Interrupt 35 will abort any transfers in progress and set CHAIF flag
36 Interrupt 36 will abort any transfers in progress and set CHAIF flag
37 Interrupt 37 will abort any transfers in progress and set CHAIF flag
38 Interrupt 38 will abort any transfers in progress and set CHAIF flag
39 Interrupt 39 will abort any transfers in progress and set CHAIF flag
40 Interrupt 40 will abort any transfers in progress and set CHAIF flag
41 Interrupt 41 will abort any transfers in progress and set CHAIF flag
42 Interrupt 42 will abort any transfers in progress and set CHAIF flag
43 Interrupt 43 will abort any transfers in progress and set CHAIF flag
44 Interrupt 44 will abort any transfers in progress and set CHAIF flag
45 Interrupt 45 will abort any transfers in progress and set CHAIF flag
46 Interrupt 46 will abort any transfers in progress and set CHAIF flag
47 Interrupt 47 will abort any transfers in progress and set CHAIF flag
48 Interrupt 48 will abort any transfers in progress and set CHAIF flag
49 Interrupt 49 will abort any transfers in progress and set CHAIF flag
50 Interrupt 50 will abort any transfers in progress and set CHAIF flag
51 Interrupt 51 will abort any transfers in progress and set CHAIF flag
52 Interrupt 52 will abort any transfers in progress and set CHAIF flag
53 Interrupt 53 will abort any transfers in progress and set CHAIF flag
54 Interrupt 54 will abort any transfers in progress and set CHAIF flag
55 Interrupt 55 will abort any transfers in progress and set CHAIF flag
56 Interrupt 56 will abort any transfers in progress and set CHAIF flag
57 Interrupt 57 will abort any transfers in progress and set CHAIF flag
58 Interrupt 58 will abort any transfers in progress and set CHAIF flag
59 Interrupt 59 will abort any transfers in progress and set CHAIF flag
60 Interrupt 60 will abort any transfers in progress and set CHAIF flag
61 Interrupt 61 will abort any transfers in progress and set CHAIF flag
62 Interrupt 62 will abort any transfers in progress and set CHAIF flag
63 Interrupt 63 will abort any transfers in progress and set CHAIF flag
64 Interrupt 64 will abort any transfers in progress and set CHAIF flag
65 Interrupt 65 will abort any transfers in progress and set CHAIF flag
66 Interrupt 66 will abort any transfers in progress and set CHAIF flag
67 Interrupt 67 will abort any transfers in progress and set CHAIF flag
68 Interrupt 68 will abort any transfers in progress and set CHAIF flag
69 Interrupt 69 will abort any transfers in progress and set CHAIF flag
70 Interrupt 70 will abort any transfers in progress and set CHAIF flag
71 Interrupt 71 will abort any transfers in progress and set CHAIF flag
72 Interrupt 72 will abort any transfers in progress and set CHAIF flag
73 Interrupt 73 will abort any transfers in progress and set CHAIF flag
74 Interrupt 74 will abort any transfers in progress and set CHAIF flag
75 Interrupt 75 will abort any transfers in progress and set CHAIF flag
76 Interrupt 76 will abort any transfers in progress and set CHAIF flag
77 Interrupt 77 will abort any transfers in progress and set CHAIF flag
78 Interrupt 78 will abort any transfers in progress and set CHAIF flag
79 Interrupt 79 will abort any transfers in progress and set CHAIF flag
80 Interrupt 80 will abort any transfers in progress and set CHAIF flag
81 Interrupt 81 will abort any transfers in progress and set CHAIF flag
82 Interrupt 82 will abort any transfers in progress and set CHAIF flag
83 Interrupt 83 will abort any transfers in progress and set CHAIF flag
84 Interrupt 84 will abort any transfers in progress and set CHAIF flag
85 Interrupt 85 will abort any transfers in progress and set CHAIF flag
86 Interrupt 86 will abort any transfers in progress and set CHAIF flag
87 Interrupt 87 will abort any transfers in progress and set CHAIF flag
88 Interrupt 88 will abort any transfers in progress and set CHAIF flag
89 Interrupt 89 will abort any transfers in progress and set CHAIF flag
90 Interrupt 90 will abort any transfers in progress and set CHAIF flag
91 Interrupt 91 will abort any transfers in progress and set CHAIF flag
92 Interrupt 92 will abort any transfers in progress and set CHAIF flag
93 Interrupt 93 will abort any transfers in progress and set CHAIF flag
94 Interrupt 94 will abort any transfers in progress and set CHAIF flag
95 Interrupt 95 will abort any transfers in progress and set CHAIF flag
96 Interrupt 96 will abort any transfers in progress and set CHAIF flag
97 Interrupt 97 will abort any transfers in progress and set CHAIF flag
98 Interrupt 98 will abort any transfers in progress and set CHAIF flag
99 Interrupt 99 will abort any transfers in progress and set CHAIF flag
100 Interrupt 100 will abort any transfers in progress and set CHAIF flag
101 Interrupt 101 will abort any transfers in progress and set CHAIF flag
102 Interrupt 102 will abort any transfers in progress and set CHAIF flag
103 Interrupt 103 will abort any transfers in progress and set CHAIF flag
104 Interrupt 104 will abort any transfers in progress and set CHAIF flag
105 Interrupt 105 will abort any transfers in progress and set CHAIF flag
106 Interrupt 106 will abort any transfers in progress and set CHAIF flag
107 Interrupt 107 will abort any transfers in progress and set CHAIF flag
108 Interrupt 108 will abort any transfers in progress and set CHAIF flag
109 Interrupt 109 will abort any transfers in progress and set CHAIF flag
110 Interrupt 110 will abort any transfers in progress and set CHAIF flag
111 Interrupt 111 will abort any transfers in progress and set CHAIF flag
112 Interrupt 112 will abort any transfers in progress and set CHAIF flag
113 Interrupt 113 will abort any transfers in progress and set CHAIF flag
114 Interrupt 114 will abort any transfers in progress and set CHAIF flag
115 Interrupt 115 will abort any transfers in progress and set CHAIF flag
116 Interrupt 116 will abort any transfers in progress and set CHAIF flag
117 Interrupt 117 will abort any transfers in progress and set CHAIF flag
118 Interrupt 118 will abort any transfers in progress and set CHAIF flag
119 Interrupt 119 will abort any transfers in progress and set CHAIF flag
120 Interrupt 120 will abort any transfers in progress and set CHAIF flag
121 Interrupt 121 will abort any transfers in progress and set CHAIF flag
122 Interrupt 122 will abort any transfers in progress and set CHAIF flag
123 Interrupt 123 will abort any transfers in progress and set CHAIF flag
124 Interrupt 124 will abort any transfers in progress and set CHAIF flag
125 Interrupt 125 will abort any transfers in progress and set CHAIF flag
126 Interrupt 126 will abort any transfers in progress and set CHAIF flag
127 Interrupt 127 will abort any transfers in progress and set CHAIF flag
128 Interrupt 128 will abort any transfers in progress and set CHAIF flag
129 Interrupt 129 will abort any transfers in progress and set CHAIF flag
130 Interrupt 130 will abort any transfers in progress and set CHAIF flag
131 Interrupt 131 will abort any transfers in progress and set CHAIF flag
132 Interrupt 132 will abort any transfers in progress and set CHAIF flag
133 Interrupt 133 will abort any transfers in progress and set CHAIF flag
134 Interrupt 134 will abort any transfers in progress and set CHAIF flag
135 Interrupt 135 will abort any transfers in progress and set CHAIF flag
136 Interrupt 136 will abort any transfers in progress and set CHAIF flag
137 Interrupt 137 will abort any transfers in progress and set CHAIF flag
138 Interrupt 138 will abort any transfers in progress and set CHAIF flag
139 Interrupt 139 will abort any transfers in progress and set CHAIF flag
140 Interrupt 140 will abort any transfers in progress and set CHAIF flag
141 Interrupt 141 will abort any transfers in progress and set CHAIF flag
142 Interrupt 142 will abort any transfers in progress and set CHAIF flag
143 Interrupt 143 will abort any transfers in progress and set CHAIF flag
144 Interrupt 144 will abort any transfers in progress and set CHAIF flag
145 Interrupt 145 will abort any transfers in progress and set CHAIF flag
146 Interrupt 146 will abort any transfers in progress and set CHAIF flag
147 Interrupt 147 will abort any transfers in progress and set CHAIF flag
148 Interrupt 148 will abort any transfers in progress and set CHAIF flag
149 Interrupt 149 will abort any transfers in progress and set CHAIF flag
150 Interrupt 150 will abort any transfers in progress and set CHAIF flag
151 Interrupt 151 will abort any transfers in progress and set CHAIF flag
152 Interrupt 152 will abort any transfers in progress and set CHAIF flag
153 Interrupt 153 will abort any transfers in progress and set CHAIF flag
154 Interrupt 154 will abort any transfers in progress and set CHAIF flag
155 Interrupt 155 will abort any transfers in progress and set CHAIF flag
156 Interrupt 156 will abort any transfers in progress and set CHAIF flag
157 Interrupt 157 will abort any transfers in progress and set CHAIF flag
158 Interrupt 158 will abort any transfers in progress and set CHAIF flag
159 Interrupt 159 will abort any transfers in progress and set CHAIF flag
160 Interrupt 160 will abort any transfers in progress and set CHAIF flag
161 Interrupt 161 will abort any transfers in progress and set CHAIF flag
162 Interrupt 162 will abort any transfers in progress and set CHAIF flag
163 Interrupt 163 will abort any transfers in progress and set CHAIF flag
164 Interrupt 164 will abort any transfers in progress and set CHAIF flag
165 Interrupt 165 will abort any transfers in progress and set CHAIF flag
166 Interrupt 166 will abort any transfers in progress and set CHAIF flag
167 Interrupt 167 will abort any transfers in progress and set CHAIF flag
168 Interrupt 168 will abort any transfers in progress and set CHAIF flag
169 Interrupt 169 will abort any transfers in progress and set CHAIF flag
170 Interrupt 170 will abort any transfers in progress and set CHAIF flag
171 Interrupt 171 will abort any transfers in progress and set CHAIF flag
172 Interrupt 172 will abort any transfers in progress and set CHAIF flag
173 Interrupt 173 will abort any transfers in progress and set CHAIF flag
174 Interrupt 174 will abort any transfers in progress and set CHAIF flag
175 Interrupt 175 will abort any transfers in progress and set CHAIF flag
176 Interrupt 176 will abort any transfers in progress and set CHAIF flag
177 Interrupt 177 will abort any transfers in progress and set CHAIF flag
178 Interrupt 178 will abort any transfers in progress and set CHAIF flag
179 Interrupt 179 will abort any transfers in progress and set CHAIF flag
180 Interrupt 180 will abort any transfers in progress and set CHAIF flag
181 Interrupt 181 will abort any transfers in progress and set CHAIF flag
182 Interrupt 182 will abort any transfers in progress and set CHAIF flag
183 Interrupt 183 will abort any transfers in progress and set CHAIF flag
184 Interrupt 184 will abort any transfers in progress and set CHAIF flag
185 Interrupt 185 will abort any transfers in progress and set CHAIF flag
186 Interrupt 186 will abort any transfers in progress and set CHAIF flag
187 Interrupt 187 will abort any transfers in progress and set CHAIF flag
188 Interrupt 188 will abort any transfers in progress and set CHAIF flag
189 Interrupt 189 will abort any transfers in progress and set CHAIF flag
190 Interrupt 190 will abort any transfers in progress and set CHAIF flag
191 Interrupt 191 will abort any transfers in progress and set CHAIF flag
192 Interrupt 192 will abort any transfers in progress and set CHAIF flag
193 Interrupt 193 will abort any transfers in progress and set CHAIF flag
194 Interrupt 194 will abort any transfers in progress and set CHAIF flag
195 Interrupt 195 will abort any transfers in progress and set CHAIF flag
196 Interrupt 196 will abort any transfers in progress and set CHAIF flag
197 Interrupt 197 will abort any transfers in progress and set CHAIF flag
198 Interrupt 198 will abort any transfers in progress and set CHAIF flag
199 Interrupt 199 will abort any transfers in progress and set CHAIF flag
200 Interrupt 200 will abort any transfers in progress and set CHAIF flag
201 Interrupt 201 will abort any transfers in progress and set CHAIF flag
202 Interrupt 202 will abort any transfers in progress and set CHAIF flag
203 Interrupt 203 will abort any transfers in progress and set CHAIF flag
204 Interrupt 204 will abort any transfers in progress and set CHAIF flag
205 Interrupt 205 will abort any transfers in progress and set CHAIF flag
206 Interrupt 206 will abort any transfers in progress and set CHAIF flag
207 Interrupt 207 will abort any transfers in progress and set CHAIF flag
208 Interrupt 208 will abort any transfers in progress and set CHAIF flag
209 Interrupt 209 will abort any transfers in progress and set CHAIF flag
210 Interrupt 210 will abort any transfers in progress and set CHAIF flag
211 Interrupt 211 will abort any transfers in progress and set CHAIF flag
212 Interrupt 212 will abort any transfers in progress and set CHAIF flag
213 Interrupt 213 will abort any transfers in progress and set CHAIF flag
214 Interrupt 214 will abort any transfers in progress and set CHAIF flag
215 Interrupt 215 will abort any transfers in progress and set CHAIF flag
216 Interrupt 216 will abort any transfers in progress and set CHAIF flag
217 Interrupt 217 will abort any transfers in progress and set CHAIF flag
218 Interrupt 218 will abort any transfers in progress and set CHAIF flag
219 Interrupt 219 will abort any transfers in progress and set CHAIF flag
220 Interrupt 220 will abort any transfers in progress and set CHAIF flag
221 Interrupt 221 will abort any transfers in progress and set CHAIF flag
222 Interrupt 222 will abort any transfers in progress and set CHAIF flag
223 Interrupt 223 will abort any transfers in progress and set CHAIF flag
224 Interrupt 224 will abort any transfers in progress and set CHAIF flag
225 Interrupt 225 will abort any transfers in progress and set CHAIF flag
226 Interrupt 226 will abort any transfers in progress and set CHAIF flag
227 Interrupt 227 will abort any transfers in progress and set CHAIF flag
228 Interrupt 228 will abort any transfers in progress and set CHAIF flag
229 Interrupt 229 will abort any transfers in progress and set CHAIF flag
230 Interrupt 230 will abort any transfers in progress and set CHAIF flag
231 Interrupt 231 will abort any transfers in progress and set CHAIF flag
232 Interrupt 232 will abort any transfers in progress and set CHAIF flag
233 Interrupt 233 will abort any transfers in progress and set CHAIF flag
234 Interrupt 234 will abort any transfers in progress and set CHAIF flag
235 Interrupt 235 will abort any transfers in progress and set CHAIF flag
236 Interrupt 236 will abort any transfers in progress and set CHAIF flag
237 Interrupt 237 will abort any transfers in progress and set CHAIF flag
238 Interrupt 238 will abort any transfers in progress and set CHAIF flag
239 Interrupt 239 will abort any transfers in progress and set CHAIF flag
240 Interrupt 240 will abort any transfers in progress and set CHAIF flag
241 Interrupt 241 will abort any transfers in progress and set CHAIF flag
242 Interrupt 242 will abort any transfers in progress and set CHAIF flag
243 Interrupt 243 will abort any transfers in progress and set CHAIF flag
244 Interrupt 244 will abort any transfers in progress and set CHAIF flag
245 Interrupt 245 will abort any transfers in progress and set CHAIF flag
246 Interrupt 246 will abort any transfers in progress and set CHAIF flag
247 Interrupt 247 will abort any transfers in progress and set CHAIF flag
248 Interrupt 248 will abort any transfers in progress and set CHAIF flag
249 Interrupt 249 will abort any transfers in progress and set CHAIF flag
250 Interrupt 250 will abort any transfers in progress and set CHAIF flag
251 Interrupt 251 will abort any transfers in progress and set CHAIF flag
252 Interrupt 252 will abort any transfers in progress and set CHAIF flag
253 Interrupt 253 will abort any transfers in progress and set CHAIF flag
254 Interrupt 254 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
2 Interrupt 2 will initiate a DMA transfer
3 Interrupt 3 will initiate a DMA transfer
4 Interrupt 4 will initiate a DMA transfer
5 Interrupt 5 will initiate a DMA transfer
6 Interrupt 6 will initiate a DMA transfer
7 Interrupt 7 will initiate a DMA transfer
8 Interrupt 8 will initiate a DMA transfer
9 Interrupt 9 will initiate a DMA transfer
10 Interrupt 10 will initiate a DMA transfer
11 Interrupt 11 will initiate a DMA transfer
12 Interrupt 12 will initiate a DMA transfer
13 Interrupt 13 will initiate a DMA transfer
14 Interrupt 14 will initiate a DMA transfer
15 Interrupt 15 will initiate a DMA transfer
16 Interrupt 16 will initiate a DMA transfer
17 Interrupt 17 will initiate a DMA transfer
18 Interrupt 18 will initiate a DMA transfer
19 Interrupt 19 will initiate a DMA transfer
20 Interrupt 20 will initiate a DMA transfer
21 Interrupt 21 will initiate a DMA transfer
22 Interrupt 22 will initiate a DMA transfer
23 Interrupt 23 will initiate a DMA transfer
24 Interrupt 24 will initiate a DMA transfer
25 Interrupt 25 will initiate a DMA transfer
26 Interrupt 26 will initiate a DMA transfer
27 Interrupt 27 will initiate a DMA transfer
28 Interrupt 28 will initiate a DMA transfer
29 Interrupt 29 will initiate a DMA transfer
30 Interrupt 30 will initiate a DMA transfer
31 Interrupt 31 will initiate a DMA transfer
32 Interrupt 32 will initiate a DMA transfer
33 Interrupt 33 will initiate a DMA transfer
34 Interrupt 34 will initiate a DMA transfer
35 Interrupt 35 will initiate a DMA transfer
36 Interrupt 36 will initiate a DMA transfer
37 Interrupt 37 will initiate a DMA transfer
38 Interrupt 38 will initiate a DMA transfer
39 Interrupt 39 will initiate a DMA transfer
40 Interrupt 40 will initiate a DMA transfer
41 Interrupt 41 will initiate a DMA transfer
42 Interrupt 42 will initiate a DMA transfer
43 Interrupt 43 will initiate a DMA transfer
44 Interrupt 44 will initiate a DMA transfer
45 Interrupt 45 will initiate a DMA transfer
46 Interrupt 46 will initiate a DMA transfer
47 Interrupt 47 will initiate a DMA transfer
48 Interrupt 48 will initiate a DMA transfer
49 Interrupt 49 will initiate a DMA transfer
50 Interrupt 50 will initiate a DMA transfer
51 Interrupt 51 will initiate a DMA transfer
52 Interrupt 52 will initiate a DMA transfer
53 Interrupt 53 will initiate a DMA transfer
54 Interrupt 54 will initiate a DMA transfer
55 Interrupt 55 will initiate a DMA transfer
56 Interrupt 56 will initiate a DMA transfer
57 Interrupt 57 will initiate a DMA transfer
58 Interrupt 58 will initiate a DMA transfer
59 Interrupt 59 will initiate a DMA transfer
60 Interrupt 60 will initiate a DMA transfer
61 Interrupt 61 will initiate a DMA transfer
62 Interrupt 62 will initiate a DMA transfer
63 Interrupt 63 will initiate a DMA transfer
64 Interrupt 64 will initiate a DMA transfer
65 Interrupt 65 will initiate a DMA transfer
66 Interrupt 66 will initiate a DMA transfer
67 Interrupt 67 will initiate a DMA transfer
68 Interrupt 68 will initiate a DMA transfer
69 Interrupt 69 will initiate a DMA transfer
70 Interrupt 70 will initiate a DMA transfer
71 Interrupt 71 will initiate a DMA transfer
72 Interrupt 72 will initiate a DMA transfer
73 Interrupt 73 will initiate a DMA transfer
74 Interrupt 74 will initiate a DMA transfer
75 Interrupt 75 will initiate a DMA transfer
76 Interrupt 76 will initiate a DMA transfer
77 Interrupt 77 will initiate a DMA transfer
78 Interrupt 78 will initiate a DMA transfer
79 Interrupt 79 will initiate a DMA transfer
80 Interrupt 80 will initiate a DMA transfer
81 Interrupt 81 will initiate a DMA transfer
82 Interrupt 82 will initiate a DMA transfer
83 Interrupt 83 will initiate a DMA transfer
84 Interrupt 84 will initiate a DMA transfer
85 Interrupt 85 will initiate a DMA transfer
86 Interrupt 86 will initiate a DMA transfer
87 Interrupt 87 will initiate a DMA transfer
88 Interrupt 88 will initiate a DMA transfer
89 Interrupt 89 will initiate a DMA transfer
90 Interrupt 90 will initiate a DMA transfer
91 Interrupt 91 will initiate a DMA transfer
92 Interrupt 92 will initiate a DMA transfer
93 Interrupt 93 will initiate a DMA transfer
94 Interrupt 94 will initiate a DMA transfer
95 Interrupt 95 will initiate a DMA transfer
96 Interrupt 96 will initiate a DMA transfer
97 Interrupt 97 will initiate a DMA transfer
98 Interrupt 98 will initiate a DMA transfer
99 Interrupt 99 will initiate a DMA transfer
100 Interrupt 100 will initiate a DMA transfer
101 Interrupt 101 will initiate a DMA transfer
102 Interrupt 102 will initiate a DMA transfer
103 Interrupt 103 will initiate a DMA transfer
104 Interrupt 104 will initiate a DMA transfer
105 Interrupt 105 will initiate a DMA transfer
106 Interrupt 106 will initiate a DMA transfer
107 Interrupt 107 will initiate a DMA transfer
108 Interrupt 108 will initiate a DMA transfer
109 Interrupt 109 will initiate a DMA transfer
110 Interrupt 110 will initiate a DMA transfer
111 Interrupt 111 will initiate a DMA transfer
112 Interrupt 112 will initiate a DMA transfer
113 Interrupt 113 will initiate a DMA transfer
114 Interrupt 114 will initiate a DMA transfer
115 Interrupt 115 will initiate a DMA transfer
116 Interrupt 116 will initiate a DMA transfer
117 Interrupt 117 will initiate a DMA transfer
118 Interrupt 118 will initiate a DMA transfer
119 Interrupt 119 will initiate a DMA transfer
120 Interrupt 120 will initiate a DMA transfer
121 Interrupt 121 will initiate a DMA transfer
122 Interrupt 122 will initiate a DMA transfer
123 Interrupt 123 will initiate a DMA transfer
124 Interrupt 124 will initiate a DMA transfer
125 Interrupt 125 will initiate a DMA transfer
126 Interrupt 126 will initiate a DMA transfer
127 Interrupt 127 will initiate a DMA transfer
128 Interrupt 128 will initiate a DMA transfer
129 Interrupt 129 will initiate a DMA transfer
130 Interrupt 130 will initiate a DMA transfer
131 Interrupt 131 will initiate a DMA transfer
132 Interrupt 132 will initiate a DMA transfer
133 Interrupt 133 will initiate a DMA transfer
134 Interrupt 134 will initiate a DMA transfer
135 Interrupt 135 will initiate a DMA transfer
136 Interrupt 136 will initiate a DMA transfer
137 Interrupt 137 will initiate a DMA transfer
138 Interrupt 138 will initiate a DMA transfer
139 Interrupt 139 will initiate a DMA transfer
140 Interrupt 140 will initiate a DMA transfer
141 Interrupt 141 will initiate a DMA transfer
142 Interrupt 142 will initiate a DMA transfer
143 Interrupt 143 will initiate a DMA transfer
144 Interrupt 144 will initiate a DMA transfer
145 Interrupt 145 will initiate a DMA transfer
146 Interrupt 146 will initiate a DMA transfer
147 Interrupt 147 will initiate a DMA transfer
148 Interrupt 148 will initiate a DMA transfer
149 Interrupt 149 will initiate a DMA transfer
150 Interrupt 150 will initiate a DMA transfer
151 Interrupt 151 will initiate a DMA transfer
152 Interrupt 152 will initiate a DMA transfer
153 Interrupt 153 will initiate a DMA transfer
154 Interrupt 154 will initiate a DMA transfer
155 Interrupt 155 will initiate a DMA transfer
156 Interrupt 156 will initiate a DMA transfer
157 Interrupt 157 will initiate a DMA transfer
158 Interrupt 158 will initiate a DMA transfer
159 Interrupt 159 will initiate a DMA transfer
160 Interrupt 160 will initiate a DMA transfer
161 Interrupt 161 will initiate a DMA transfer
162 Interrupt 162 will initiate a DMA transfer
163 Interrupt 163 will initiate a DMA transfer
164 Interrupt 164 will initiate a DMA transfer
165 Interrupt 165 will initiate a DMA transfer
166 Interrupt 166 will initiate a DMA transfer
167 Interrupt 167 will initiate a DMA transfer
168 Interrupt 168 will initiate a DMA transfer
169 Interrupt 169 will initiate a DMA transfer
170 Interrupt 170 will initiate a DMA transfer
171 Interrupt 171 will initiate a DMA transfer
172 Interrupt 172 will initiate a DMA transfer
173 Interrupt 173 will initiate a DMA transfer
174 Interrupt 174 will initiate a DMA transfer
175 Interrupt 175 will initiate a DMA transfer
176 Interrupt 176 will initiate a DMA transfer
177 Interrupt 177 will initiate a DMA transfer
178 Interrupt 178 will initiate a DMA transfer
179 Interrupt 179 will initiate a DMA transfer
180 Interrupt 180 will initiate a DMA transfer
181 Interrupt 181 will initiate a DMA transfer
182 Interrupt 182 will initiate a DMA transfer
183 Interrupt 183 will initiate a DMA transfer
184 Interrupt 184 will initiate a DMA transfer
185 Interrupt 185 will initiate a DMA transfer
186 Interrupt 186 will initiate a DMA transfer
187 Interrupt 187 will initiate a DMA transfer
188 Interrupt 188 will initiate a DMA transfer
189 Interrupt 189 will initiate a DMA transfer
190 Interrupt 190 will initiate a DMA transfer
191 Interrupt 191 will initiate a DMA transfer
192 Interrupt 192 will initiate a DMA transfer
193 Interrupt 193 will initiate a DMA transfer
194 Interrupt 194 will initiate a DMA transfer
195 Interrupt 195 will initiate a DMA transfer
196 Interrupt 196 will initiate a DMA transfer
197 Interrupt 197 will initiate a DMA transfer
198 Interrupt 198 will initiate a DMA transfer
199 Interrupt 199 will initiate a DMA transfer
200 Interrupt 200 will initiate a DMA transfer
201 Interrupt 201 will initiate a DMA transfer
202 Interrupt 202 will initiate a DMA transfer
203 Interrupt 203 will initiate a DMA transfer
204 Interrupt 204 will initiate a DMA transfer
205 Interrupt 205 will initiate a DMA transfer
206 Interrupt 206 will initiate a DMA transfer
207 Interrupt 207 will initiate a DMA transfer
208 Interrupt 208 will initiate a DMA transfer
209 Interrupt 209 will initiate a DMA transfer
210 Interrupt 210 will initiate a DMA transfer
211 Interrupt 211 will initiate a DMA transfer
212 Interrupt 212 will initiate a DMA transfer
213 Interrupt 213 will initiate a DMA transfer
214 Interrupt 214 will initiate a DMA transfer
215 Interrupt 215 will initiate a DMA transfer
216 Interrupt 216 will initiate a DMA transfer
217 Interrupt 217 will initiate a DMA transfer
218 Interrupt 218 will initiate a DMA transfer
219 Interrupt 219 will initiate a DMA transfer
220 Interrupt 220 will initiate a DMA transfer
221 Interrupt 221 will initiate a DMA transfer
222 Interrupt 222 will initiate a DMA transfer
223 Interrupt 223 will initiate a DMA transfer
224 Interrupt 224 will initiate a DMA transfer
225 Interrupt 225 will initiate a DMA transfer
226 Interrupt 226 will initiate a DMA transfer
227 Interrupt 227 will initiate a DMA transfer
228 Interrupt 228 will initiate a DMA transfer
229 Interrupt 229 will initiate a DMA transfer
230 Interrupt 230 will initiate a DMA transfer
231 Interrupt 231 will initiate a DMA transfer
232 Interrupt 232 will initiate a DMA transfer
233 Interrupt 233 will initiate a DMA transfer
234 Interrupt 234 will initiate a DMA transfer
235 Interrupt 235 will initiate a DMA transfer
236 Interrupt 236 will initiate a DMA transfer
237 Interrupt 237 will initiate a DMA transfer
238 Interrupt 238 will initiate a DMA transfer
239 Interrupt 239 will initiate a DMA transfer
240 Interrupt 240 will initiate a DMA transfer
241 Interrupt 241 will initiate a DMA transfer
242 Interrupt 242 will initiate a DMA transfer
243 Interrupt 243 will initiate a DMA transfer
244 Interrupt 244 will initiate a DMA transfer
245 Interrupt 245 will initiate a DMA transfer
246 Interrupt 246 will initiate a DMA transfer
247 Interrupt 247 will initiate a DMA transfer
248 Interrupt 248 will initiate a DMA transfer
249 Interrupt 249 will initiate a DMA transfer
250 Interrupt 250 will initiate a DMA transfer
251 Interrupt 251 will initiate a DMA transfer
252 Interrupt 252 will initiate a DMA transfer
253 Interrupt 253 will initiate a DMA transfer
254 Interrupt 254 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH3INTDMA Channel x Interrupt Control Register
Address
0xBF8832C0
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred) or a pattern match event occurs
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected. Either the source or the destination address is invalid.
DCH3SSADMA Channel x Source Start Address Register
Address
0xBF8832D0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DSADMA Channel x Destination Start Address Register
Address
0xBF8832E0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3SSIZDMA Channel x Source Size Register
Address
0xBF8832F0
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DSIZDMA Channel x Destination Size Register
Address
0xBF883300
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3SPTRDMA Channel x Source Pointer Register
Address
0xBF883310
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DPTRDMA Channel x Destination Pointer Register
Address
0xBF883320
Reset
0x00000000
Access
read only
Size
32-bit
DCH3CSIZDMA Channel x Cell-Size Register
Address
0xBF883330
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3CPTRDMA Channel x Cell Pointer Register
Address
0xBF883340
Reset
0x00000000
Access
read/write
Size
32-bit
DCH3DATDMA Channel x Pattern Data Register
Address
0xBF883350
Reset
0x00000000
Access
read/write
Size
32-bit
PCACHE Prefetch cache
CHECONCache Control Register
Address
0xBF884000
Reset
0x00000007
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CHECOH
16
Cache Coherency Setting on a PFM Program Cycle bit
0 Invalidate all data lines and instruction lines that are not locked
1 Invalidate all data and instruction lines
DCSZ
9:8
Data Cache Size in Lines bits
0 Disable data caching
1 Enable data caching with a size of 1 Line
2 Enable data caching with a size of 2 Lines
3 Enable data caching with a size of 4 Lines
PREFEN
5:4
Predictive Prefetch Enable bits
0 Disable predictive prefetch
1 Enable predictive prefetch for cacheable regions only
2 Enable predictive prefetch for non-cacheable regions only
3 Enable predictive prefetch for both cacheable and non-cacheable regions
PFMWS
2:0
PFM Access Time Defined in Terms of SYSLK Wait States bits
0 Zero Wait state
1 One Wait state
2 Two Wait states
3 Three Wait states
4 Four Wait states
5 Five Wait states
6 Six Wait states
7 Seven Wait states
CHEACCCache Access Register
Address
0xBF884010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CHEIDX
3:0
Cache Line Index bits
0 Select cache line 0 for reading or writing
1 Select cache line 1 for reading or writing
2 Select cache line 2 for reading or writing
3 Select cache line 3 for reading or writing
4 Select cache line 4 for reading or writing
5 Select cache line 5 for reading or writing
6 Select cache line 6 for reading or writing
7 Select cache line 7 for reading or writing
8 Select cache line 8 for reading or writing
9 Select cache line 9 for reading or writing
10 Select cache line 10 for reading or writing
11 Select cache line 11 for reading or writing
12 Select cache line 12 for reading or writing
13 Select cache line 13 for reading or writing
14 Select cache line 14 for reading or writing
15 Select cache line 15 for reading or writing
CHEWEN
31
Cache Access Enable bits for registers CHETAG
0 The cache line selected by CHEIDX(3:0) is not writeable
1 The cache line selected by CHEIDX(3:0) is writeable
CHETAGCache TAG Register
Address
0xBF884020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
LTAG
4
LVALID
3
Line Valid bit
0 The line is not valid and is not compared to the physical address for hit detection
1 The line is valid and is compared to the physical address for hit detection
LLOCK
2
Line Lock bit
0 The line is not locked and can be replaced
1 The line is locked and will not be replaced
LTYPE
1
Line Type bit
0 The line caches data words
1 The line caches instruction words
LTAGBOOT
31
Line TAG Address Boot bit
0 The line is in the 0x1FC00000 (physical) area of memory
1 The line is in the 0x1D000000 (physical) area of memory
CHEMSKCache TAG Mask Register
Address
0xBF884030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LMASK
15:5
Line Mask bits
0 Only writeable for values of CHEIDX(3:0) bits (CHEACC(3:0)) equal to 0x0A and 0x0B. Disables mask logic.
1 Enables mask logic to force a match on the corresponding bit position in the LTAG(19:0) bits (CHETAG(23:4)) and the physical address.
BETA