The 22 registers of INT (Interrupt controller), from 0xBF881000, with their reset value and every field. The PIC32MX775F256H has 774 registers in 64 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
INT Interrupt controller
INTCONInterrupt Control Register
Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
SS0
16
0 Single vector is not presented with a shadow register set
1 Single vector is presented with a shadow register set
FRZ
14
MVEC
12
Multi Vector Configuration bit
0 Interrupt controller configured for Single-vectored mode
1 Interrupt controller configured for Multi-vectored mode
TPC
10:8
Interrupt Proximity Timer Control bits
0 Disables Interrupt Proximity timer
1 Interrupts of group priority 1 start the Interrupt Proximity timer
2 Interrupts of group priority 2 or lower start the Interrupt Proximity timer
3 Interrupts of group priority 3 or lower start the Interrupt Proximity timer
4 Interrupts of group priority 4 or lower start the Interrupt Proximity timer
5 Interrupts of group priority 5 or lower start the Interrupt Proximity timer
6 Interrupts of group priority 6 or lower start the Interrupt Proximity timer
7 Interrupts of group priority 7 or lower start the Interrupt Proximity timer
INT4EP
4
External Interrupt 4 Edge
0 Falling edge
1 Rising edge
INT3EP
3
External Interrupt 3 Edge
0 Falling edge
1 Rising edge
INT2EP
2
External Interrupt 2 Edge
0 Falling edge
1 Rising edge
INT1EP
1
External Interrupt 1 Edge
0 Falling edge
1 Rising edge
INT0EP
0
External Interrupt 0 Edge
0 Falling edge
1 Rising edge
INTSTATInterrupt Status Register
Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
SRIPL
10:8
Requested Priority Level bits
0 The priority level of the latest interrupt presented to the CPU is 0
1 The priority level of the latest interrupt presented to the CPU is 1
2 The priority level of the latest interrupt presented to the CPU is 2
3 The priority level of the latest interrupt presented to the CPU is 3
4 The priority level of the latest interrupt presented to the CPU is 4
5 The priority level of the latest interrupt presented to the CPU is 5
6 The priority level of the latest interrupt presented to the CPU is 6
7 The priority level of the latest interrupt presented to the CPU is 7
VEC
5:0
Interrupt Vector bits
0 The interrupt vector that is presented to the CPU is 0
1 The interrupt vector that is presented to the CPU is 1
2 The interrupt vector that is presented to the CPU is 2
3 The interrupt vector that is presented to the CPU is 3
4 The interrupt vector that is presented to the CPU is 4
5 The interrupt vector that is presented to the CPU is 5
6 The interrupt vector that is presented to the CPU is 6
7 The interrupt vector that is presented to the CPU is 7
8 The interrupt vector that is presented to the CPU is 8
9 The interrupt vector that is presented to the CPU is 9
10 The interrupt vector that is presented to the CPU is 10
11 The interrupt vector that is presented to the CPU is 11
12 The interrupt vector that is presented to the CPU is 12
13 The interrupt vector that is presented to the CPU is 13
14 The interrupt vector that is presented to the CPU is 14
15 The interrupt vector that is presented to the CPU is 15
16 The interrupt vector that is presented to the CPU is 16
17 The interrupt vector that is presented to the CPU is 17
18 The interrupt vector that is presented to the CPU is 18
19 The interrupt vector that is presented to the CPU is 19
20 The interrupt vector that is presented to the CPU is 20
21 The interrupt vector that is presented to the CPU is 21
22 The interrupt vector that is presented to the CPU is 22
23 The interrupt vector that is presented to the CPU is 23
24 The interrupt vector that is presented to the CPU is 24
25 The interrupt vector that is presented to the CPU is 25
26 The interrupt vector that is presented to the CPU is 26
27 The interrupt vector that is presented to the CPU is 27
28 The interrupt vector that is presented to the CPU is 28
29 The interrupt vector that is presented to the CPU is 29
30 The interrupt vector that is presented to the CPU is 30
31 The interrupt vector that is presented to the CPU is 31
BETA