PIC32MZ1025W104132 CFG registers

The 9 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MZ1025W104132 has 1091 registers in 66 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CFG Configuration and pin control

CFGCON0

Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
23 fields
FieldBitsWhat it does
ETHTPSF30Ethernet Tx SOF enabled for CTR measurements
  • 0 RPSF is enabled in CTR measurement
  • 1 TPSF is enabled in CTR measurement
FECCCON29:28Flash ECC Control
  • 0 ECC Enabled (NVMOP = Word Programming disabled)
  • 1 Dynamically ECC Enabled
  • 2 ECC and Dynamically ECC Disabled
ETHPLLHWMD27EWPLL HW Control Mode for PWDN and RESET
  • 0 PWDN and RESET are generated by SW using corresponding PLLCON register bits
  • 1 PWDN and RESET are generated by HW
BTPLLHWMD26BTPLL HW Control Mode for PWDN and RESET
  • 0 PWDN and RESET are generated by SW using corresponding PLLCON register bits
  • 1 PWDN and RESET are generated by HW
SPLLHWMD25SPLL HW Control Mode for PWDN and RESET
  • 0 PWDN and RESET are generated by SW using corresponding PLLCON register bits
  • 1 PWDN and RESET are generated by HW
UPLLHWMD24UPLL HW Control Mode for PWDN and RESET
  • 0 PWDN and RESET are generated by SW using corresponding PLLCON register bits
  • 1 PWDN and RESET are generated by HW
PCM23PCHE I/D Cacheable Mode
  • 0 The cache-ability is controlled by the MIPS CPU via HPROT[3]. This feature is not available on all the MIPS cores.
  • 1 Always enabled from outside. Can be further enabled/disabled by PCHE SFR registers.
CANFDDIV21:20CAN-FD divider control
  • 0 Divide-by 2
  • 2 Divide-by 4
  • 3 Divide-by 8
IC_ACLK17ICAP Alternate Clock Selection
  • 0 All ICAP Modules use TMR2/TMR3 as their timebase clock
  • 1 ICAP Modules use an alternative TMR pair as their timebase clock
OC_ACLK16OCMP Alternate Clock Selection
  • 0 All OCMP Modules use TMR2/TMR3 as their timebase clock
  • 1 OCMP Modules use an alternative TMR pair as their timebase clock
CFGLOCK15:14Configuration Register Lock
  • 0 All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are not locked and can be written - CFGLOCK value can be changed
  • 2 All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and can not be written - CFGLOCK value can be changed.
  • 3 All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and can not be written - CFGLOCK value can not be changed
IOLOCK13IO LOCK
  • 0 IO Remap SFR are not locked and can be modified
  • 1 IO Remap SFR bits are locked and cannot be modified
PMDLOCK12Peripheral Module Disable (PMD) LOCK
  • 0 PMDx SFR bits are not locked and can be modified
  • 1 PMDx SFR bits are locked and cannot be modified
PGLOCK11Permission Group LOCK
  • 0 CFGPG SFR bits are not locked and can be modified
  • 1 CFGPG SFR bits are locked and cannot be modified
PMULOCK10PMU Controller Register LOCK
  • 0 PMU SFR bits are not locked and can be modified
  • 1 PMU SFR bits are locked and cannot be modified
USBSSEN8USB Suspend Sleep Enable
  • 0 USB FREF clock continues to run when suspend mode is active.
  • 1 USB FREF clock is shut down when suspend mode is active.
EXLPRI7CPU arbitration Priority to SRAM when servicing an Interrupt
  • 0 CPU uses Least Recently Serviced Arbitration (same as other initiators)
  • 1 CPU gets High Priority access to SRAM1, SRAM2
DMAPRI6DMAR and DMAW arbitration Priority to SRAM
  • 0 DMA uses Least Recently Serviced Arbitration (same as other initiators)
  • 1 DMA gets High Priority access to SRAM1, SRAM2
FCPRI5FC arbitration Priority to SRAM
  • 0 FC uses Least Recently Serviced Arbitration (same as other initiators)
  • 1 FC gets High Priority access to SRAM1, SRAM2
JTAGEN3JTAG control bit
  • 0 JTAG Port Disabled
  • 1 JTAG Port Enabled
TROEN2Trace clock control bit
  • 0 Stop Trace Clock and disable Trace Outputs
  • 1 Start Trace Clock and enable Trace Outputs (Trace Probe must be present)
TDOEN0TDO control for 2 wire JTAG protocol
  • 0 2-wire JTAG protocol does not use TDO (Two phase (Half Duplex) Protocol)
  • 1 2-wire JTAG protocol uses TDO (Four phase (Full Duplex) Protocol)
EPGMCLK31External Programming Clock enable
  • 0 In ICSP (TMOD0) mode, the FRC clock is always driven by the FRC oscillator
  • 1 In ICSP (TMOD0) mode, enable the FRC clock to be driven by the TSTFRC Pin Function

CFGCON1CONFIGURATION CONTROL REGISTER 1

Address
0xBF800010
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
WDTPS28:24
USBDPTRIM23:20USB DM Rise/Fall Trim fuse bits
USBDMTRIM19:16USB DP Rise/Fall Trim fuse bits
HSUARTEN15UART1 High Speed Mode Enable
  • 0 UART1 is driven through PPS (I/O remap) resulting in a lower maximum baud rate
  • 1 UART1 is driven from/to dedicated pins resulting in the highest possible maximum baud rate
SMCLR14Selects CRU handling of MCLR Control
  • 0 MCLR causes a faux POR
  • 1 Legacy mode (system clear does not reset all state of device)
HSSPIEN13High Speed Mode Enable (SPI-1)
  • 0 SPI1 is driven through PPS (I/O remap) resulting in a lower interface speed
  • 1 SPI1 is driven from/to dedicated pins resulting in the highest interface speed
VBUSIO12USB VBUS_ON Selection bit
  • 0 VBUS_ON pin is controlled by the Port Function
  • 1 VBUS_ON pin is controlled by the USB Module
USBIDIO11USB USBID Selection bit
  • 0 USBID pin is controlled by the Port Function
  • 1 USBID pin is controlled by the USB Module
CLASSBDIS10Disable CLASSB Device Functionality
  • 0 CLASSB functions enabled
  • 1 CLASSB functions disabled
ETHEXEREF9Exclusive Ethernet PYHY reference clock Enable
  • 0 ETH_CLK_OUT will be used as PHY reference clock if needed (Refer IOM)
  • 1 PHY reference clock is made available on ETH_EXCLK_OUT (Refer IOM)
FMIIEN8Ethernet1 MII Enable
  • 0 10-pin 50MHz Reduced Media Independent Interface is enabled
  • 1 18-pin 25MHz Media Independent Interface is enabled
TRCEN5Trace Enable
  • 0 Trace features in the CPU are disabled
  • 1 Trace features in the CPU are enabled
ICESEL4:3EMUC/EMUD Communication Channel Select
  • 0 ICE EMUC4/EMUD4 pins are shared with PGC4/PGD4
  • 1 ICE EMUC3/EMUD3 pins are shared with PGC3/PGD3 (Not used on this device)
  • 2 ICE EMUC2/EMUD2 pins are shared with PGC2/PGD2
  • 3 ICE EMUC1/EMUD1 pins are shared with PGC1/PGD1
DEBUG1:0Background Debugger Access Selection
  • 0 EMUC/EMUD Enabled - 4-wire JTAG I/F Disabled - ICD Module Enabled
  • 1 EMUC/EMUD Enabled - 4-wire JTAG I/F Disabled - ICD Module Disabled
  • 2 4-wire JTAG I/F Enabled - EMUC/EMUD Disabled - ICD Module Enabled
  • 3 4-wire JTAG I/F Enabled - EMUC/EMUD Disabled - ICD Module Disabled

CFGCON2CONFIGURATION CONTROL REGISTER 2

Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
DMTCNT30:26Dead Man Timer Count Select bits
  • 0 Counter value is 2^8 for cfg_dmt_cnt[31-0]
  • 1 Counter value is 2^9 for cfg_dmt_cnt[31-0]
  • 2 Counter value is 2^10 for cfg_dmt_cnt[31-0]
  • 3 Counter value is 2^11 for cfg_dmt_cnt[31-0]
  • 4 Counter value is 2^12 for cfg_dmt_cnt[31-0]
  • 5 Counter value is 2^13 for cfg_dmt_cnt[31-0]
  • 6 Counter value is 2^14 for cfg_dmt_cnt[31-0]
  • 7 Counter value is 2^15 for cfg_dmt_cnt[31-0]
  • 8 Counter value is 2^16 for cfg_dmt_cnt[31-0]
  • 9 Counter value is 2^17 for cfg_dmt_cnt[31-0]
  • 10 Counter value is 2^18 for cfg_dmt_cnt[31-0]
  • 11 Counter value is 2^19 for cfg_dmt_cnt[31-0]
  • 12 Counter value is 2^20 for cfg_dmt_cnt[31-0]
  • 13 Counter value is 2^21 for cfg_dmt_cnt[31-0]
  • 14 Counter value is 2^22 for cfg_dmt_cnt[31-0]
  • 15 Counter value is 2^23 for cfg_dmt_cnt[31-0]
  • 16 Counter value is 2^24 for cfg_dmt_cnt[31-0]
  • 17 Counter value is 2^25 for cfg_dmt_cnt[31-0]
  • 18 Counter value is 2^26 for cfg_dmt_cnt[31-0]
  • 19 Counter value is 2^27 for cfg_dmt_cnt[31-0]
  • 20 Counter value is 2^28 for cfg_dmt_cnt[31-0]
  • 21 Counter value is 2^29 for cfg_dmt_cnt[31-0]
  • 22 Counter value is 2^30 for cfg_dmt_cnt[31-0]
  • 23 Counter value is 2^31 for cfg_dmt_cnt[31-0]
WDTWINSZ25:24Watchdog Timer Window Size bits
  • 0 Window size is 75%
  • 1 Window size is 50%
  • 2 Window size is 37.5%
  • 3 Window size is 25%
WDTEN23Watchdog Timer Enable bit
  • 0 WDT disabled (control is placed on the SWDTEN bit)
  • 1 WDT enabled
WINDIS22Windowed Watchdog Timer Disable bit
  • 0 Windowed WDT enabled
  • 1 Standard WDT selected; windowed WDT disabled
WDTSPGM21Watchdog Timer Stop during Flash Programming bit
  • 0 The WDT runs during NVR programming (for read/execute while programming flash systems)
  • 1 The WDT stops during NVR programming (legacy)
WDTPS20:16
FSCMEN15Fail-Safe Clock Monitor Enable
  • 0 FSCM Disabled
  • 1 FSCM Enabled
CKSWEN14Software Clock Switching Enable
  • 0 Software Clock Switching Disabled
  • 1 Software Clock Switching Enabled
WAKE2SPD132-Speed startup enabled in Sleep mode bit
  • 0 When the device EXITS Sleep Mode, the sys_clk will be from the selected clock.
  • 1 When the device EXITS Sleep Mode, the sys_clk will be from FRC until the selected clock is ready
SOSCSEL12SOSC Selection Configuration bit
  • 0 Digital (SCLKI) mode
  • 1 Crystal (SOSCI/SOSCO) mode
WDTRMCS11:10WDT RUN Mode Clock Select
  • 0 Module PB Clock
  • 3 LPRC
POSCMOD9:8Primary Oscillator Configuration bits
  • 2 HS oscillator mode selected
  • 3 Primary oscillator disabled
DMTINTV5:3Dead Man Timer Count Window Interval bits
  • 0 Window/Interval value is Counter value for cfg_dmt_intv[31-0]
  • 1 Window/Interval value is 1/2 Counter value for cfg_dmt_intv[31-0]
  • 2 Window/Interval value is 1/4 Counter value for cfg_dmt_intv[31-0]
  • 3 Window/Interval value is 1/8 Counter value for cfg_dmt_intv[31-0]
  • 4 Window/Interval value is 1/16 Counter value for cfg_dmt_intv[31-0]
  • 5 Window/Interval value is 1/32 Counter value for cfg_dmt_intv[31-0]
  • 6 Window/Interval value is 1/64 Counter value for cfg_dmt_intv[31-0]
  • 7 Window/Interval value is 1/128 Counter value for cfg_dmt_intv[31-0]
DMTEN31Dead Man Timer Enable bit
  • 0 DMT disabled (control is placed on the DMTCON.ON bit)
  • 1 DMT enabled

CFGCON3CONFIGURATION CONTROL REGISTER 3

Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
BTPLLPOSTDIV217:12BTPLL Post Divider bits for controlling auxiliary second PLL clock output.
  • 1 Divide by 1
  • 2 Divide by 2
  • 3 Divide by 3
  • 4 Divide by 4
  • 5 Divide by 5
  • 6 Divide by 6
  • 7 Divide by 7
  • 8 Divide by 8
  • 9 Divide by 9
  • 10 Divide by 10
  • 11 Divide by 11
  • 12 Divide by 12
  • 13 Divide by 13
  • 14 Divide by 14
  • 15 Divide by 15
  • 16 Divide by 16
  • 17 Divide by 17
  • 18 Divide by 18
  • 19 Divide by 19
  • 20 Divide by 20
  • 21 Divide by 21
  • 22 Divide by 22
  • 23 Divide by 23
  • 24 Divide by 24
  • 25 Divide by 25
  • 26 Divide by 26
  • 27 Divide by 27
  • 28 Divide by 28
  • 29 Divide by 29
  • 30 Divide by 30
  • 31 Divide by 31
  • 32 Divide by 32
  • 33 Divide by 33
  • 34 Divide by 34
  • 35 Divide by 35
  • 36 Divide by 36
  • 37 Divide by 37
  • 38 Divide by 38
  • 39 Divide by 39
  • 40 Divide by 40
  • 41 Divide by 41
  • 42 Divide by 42
  • 43 Divide by 43
  • 44 Divide by 44
  • 45 Divide by 45
  • 46 Divide by 46
  • 47 Divide by 47
  • 48 Divide by 48
  • 49 Divide by 49
  • 50 Divide by 50
  • 51 Divide by 51
  • 52 Divide by 52
  • 53 Divide by 53
  • 54 Divide by 54
  • 55 Divide by 55
  • 56 Divide by 56
  • 57 Divide by 57
  • 58 Divide by 58
  • 59 Divide by 59
  • 60 Divide by 60
  • 61 Divide by 61
  • 62 Divide by 62
  • 63 Divide by 63
SPLLPOSTDIV211:6SPLL Post Divider bits for controlling auxiliary second PLL clock output.
  • 1 Divide by 1
  • 2 Divide by 2
  • 3 Divide by 3
  • 4 Divide by 4
  • 5 Divide by 5
  • 6 Divide by 6
  • 7 Divide by 7
  • 8 Divide by 8
  • 9 Divide by 9
  • 10 Divide by 10
  • 11 Divide by 11
  • 12 Divide by 12
  • 13 Divide by 13
  • 14 Divide by 14
  • 15 Divide by 15
  • 16 Divide by 16
  • 17 Divide by 17
  • 18 Divide by 18
  • 19 Divide by 19
  • 20 Divide by 20
  • 21 Divide by 21
  • 22 Divide by 22
  • 23 Divide by 23
  • 24 Divide by 24
  • 25 Divide by 25
  • 26 Divide by 26
  • 27 Divide by 27
  • 28 Divide by 28
  • 29 Divide by 29
  • 30 Divide by 30
  • 31 Divide by 31
  • 32 Divide by 32
  • 33 Divide by 33
  • 34 Divide by 34
  • 35 Divide by 35
  • 36 Divide by 36
  • 37 Divide by 37
  • 38 Divide by 38
  • 39 Divide by 39
  • 40 Divide by 40
  • 41 Divide by 41
  • 42 Divide by 42
  • 43 Divide by 43
  • 44 Divide by 44
  • 45 Divide by 45
  • 46 Divide by 46
  • 47 Divide by 47
  • 48 Divide by 48
  • 49 Divide by 49
  • 50 Divide by 50
  • 51 Divide by 51
  • 52 Divide by 52
  • 53 Divide by 53
  • 54 Divide by 54
  • 55 Divide by 55
  • 56 Divide by 56
  • 57 Divide by 57
  • 58 Divide by 58
  • 59 Divide by 59
  • 60 Divide by 60
  • 61 Divide by 61
  • 62 Divide by 62
  • 63 Divide by 63
ETHPLLPOSTDIV25:0EWPLL Post Divider bits for controlling second PLL clock output for WiFI
  • 1 Divide by 1
  • 2 Divide by 2
  • 3 Divide by 3
  • 4 Divide by 4
  • 5 Divide by 5
  • 6 Divide by 6
  • 7 Divide by 7
  • 8 Divide by 8
  • 9 Divide by 9
  • 10 Divide by 10
  • 11 Divide by 11
  • 12 Divide by 12
  • 13 Divide by 13
  • 14 Divide by 14
  • 15 Divide by 15
  • 16 Divide by 16
  • 17 Divide by 17
  • 18 Divide by 18
  • 19 Divide by 19
  • 20 Divide by 20
  • 21 Divide by 21
  • 22 Divide by 22
  • 23 Divide by 23
  • 24 Divide by 24
  • 25 Divide by 25
  • 26 Divide by 26
  • 27 Divide by 27
  • 28 Divide by 28
  • 29 Divide by 29
  • 30 Divide by 30
  • 31 Divide by 31
  • 32 Divide by 32
  • 33 Divide by 33
  • 34 Divide by 34
  • 35 Divide by 35
  • 36 Divide by 36
  • 37 Divide by 37
  • 38 Divide by 38
  • 39 Divide by 39
  • 40 Divide by 40
  • 41 Divide by 41
  • 42 Divide by 42
  • 43 Divide by 43
  • 44 Divide by 44
  • 45 Divide by 45
  • 46 Divide by 46
  • 47 Divide by 47
  • 48 Divide by 48
  • 49 Divide by 49
  • 50 Divide by 50
  • 51 Divide by 51
  • 52 Divide by 52
  • 53 Divide by 53
  • 54 Divide by 54
  • 55 Divide by 55
  • 56 Divide by 56
  • 57 Divide by 57
  • 58 Divide by 58
  • 59 Divide by 59
  • 60 Divide by 60
  • 61 Divide by 61
  • 62 Divide by 62
  • 63 Divide by 63

CFGCON4CONFIGURATION CONTROL REGISTER 4

Address
0xBF800040
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
SOSCEN30Low Power (Secondary) Oscillator Enable bit
  • 0 Disable Low Power (Secondary) Oscillator
  • 1 Enable Low Power (Secondary) Oscillator - also at reset
DSEN28Deep Sleep Bit Enable bit
  • 0 Disable DSEN Bit in DSCON
  • 1 Enable DSEN Bit in DSCON
DSWDTEN27Deep Sleep Watchdog Timer Enable bit
  • 0 Disable DSWDT during Deep Sleep
  • 1 Enable DSWDT during Deep Sleep
DSWDTOSC26Deep Sleep Watchdog Timer Reference Clock Select bit
  • 0 Select SOSC as DSWDT reference clock
  • 1 Select LPRC as DSWDT reference clock
DSWDTPS25:21Deep Sleep Watchdog Timer Postscale Select bits
  • 0 1:32 (1 ms)
  • 1 1:64 (2.1 ms)
  • 2 1:128 (4.1 ms)
  • 3 1:256 (8.3 ms)
  • 4 1:512 (16.5 ms)
  • 5 1:1024 (33 ms)
  • 6 1:2048 (66.1 ms)
  • 7 1:4096 (132.1 ms)
  • 8 1:8192 (264.3 ms)
  • 9 1:16384 (528.5 ms)
  • 10 1:32768 (1.057 s)
  • 11 1:65536 (2.114 s)
  • 12 1:217 (4.228 s)
  • 13 1:218 (8.456 s)
  • 14 1:219 (16.912 s)
  • 15 1:220 (33.825 s)
  • 16 1:221 (67.7 s)
  • 17 1:222 (135.3 s)
  • 18 1:223 (4.5 minutes)
  • 19 1:224 (9.0 minutes)
  • 20 1:225 (18.0 minutes)
  • 21 1:226 (36.1 minutes)
  • 22 1:227 (72.2 minutes)
  • 23 1:228 (2.4 hours)
  • 24 1:229 (4.8 hours)
  • 25 1:230 (9.6 hours)
  • 26 1:231 (19.2 hours)
  • 27 1:232 (38.5 hours)
  • 28 1:233 (77.0 hours)
  • 29 1:234 (6.4 days)
  • 30 1:235 (12.8 days)
  • 31 1:236 (25.7 days)
DSZPBOREN20Deep Sleep Zero-Power BOR Enable bit
  • 0 Disable ZPBOR during deep sleep
  • 1 Enable ZPBOR during deep sleep
VBZPBOREN19VBAT Zero-Power BOR Enable bit
  • 0 Disable ZPBOR during VBAT mode
  • 1 Enable ZPBOR during VBAT mode
SOSCCFG7:0SOSC Configuration Bits

CFGPGPERMISSION GROUP CONFIGURATION REGISTER

Address
0xBF800050
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
USBPG23:22USB Permission Group- drive directly the inputs cfg_usb_pg[1-0] to the SSX
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
SQIPG21:20SQI Permission Group- drive directly the inputs cfg_sqi_pg[1-0] to the SSX
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
ETHPG19:18ETH Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
CRY1PG17:16CRY1 Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
CAN2PG15:14CAN2 Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
CAN1PG13:12CAN1 Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
ADCPG11:10ADC Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
WIFIPG9:8WIFI Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
ICDJPG7:6ICD-JTAG Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
DMAPG5:4DMA Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
FCPG3:2FC Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)
CPUPG1:0CPU (Code) Permission Group
  • 0 Read Access if RDPER[0] is 1- Write Access if WRPER[0] is 1 (Perm. Grp. 0)
  • 1 Read Access if RDPER[1] is 1- Write Access if WRPER[1] is 1 (Perm. Grp. 1)
  • 2 Read Access if RDPER[2] is 1- Write Access if WRPER[2] is 1 (Perm. Grp. 2)
  • 3 Read Access if RDPER[3] is 1- Write Access if WRPER[3] is 1 (Perm. Grp. 3)

DEVID

Address
0xBF800060
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
DEVID27:0
VER31:28

USERIDUSER UNIQUE ID REGISTER

Address
0xBF800070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
USERID15:0USER ID

SYSKEYSYSTEM KEY REGISTER

Address
0xBF800080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SYSKEY31:0