WBZ450 RCON registers

The 12 registers of RCON, from 0x44000A30, with their reset value and every field. The WBZ450 has 1802 registers in 52 peripherals, one page each.

RCON

RCONRESET CONTROL REGISTER

Address
0x44000A30
Reset
0x00000003
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
PORCORE30Core Voltage POR Flag bit
  • 0 A Power-up Reset has not occurred due to Core Voltage.
  • 1 A Power-up Reset has occurred due to Core Voltage.
BCFGERR27BCFG Error Flag Bit
  • 0 A BCFG Error has not occurred.
  • 1 A BCFG Error has occurred.
BCFGFAIL26BCFG Failure Flag Bit
  • 0 A BCFG Failure has not occurred.
  • 1 A BCFG Failure has occurred.
NVMLTA25NVM Life Time Alert Flag Bit
  • 0 A NVM LTA Error has not occurred.
  • 1 A NVM LTA Error has occurred.
NVMEOL24NVM End of Life Flag Bit
  • 0 A NVM EOL Failure has not occurred.
  • 1 A NVM EOL Failure has occurred.
DPSLP10DPSLP Deep Sleep Mode Flag Bit
  • 0 Deep Sleep Mode has not occurred.
  • 1 Deep Sleep Mode has occurred.
CMR9Configuration Mismatch Flag bit
  • 0 A Configuration Mismatch Reset Event has not occurred.
  • 1 A Configuration Mismatch Reset Event has occurred.
EXTR7External Reset (MCLR) Status bit
  • 0 A Master Clear (pin) Reset has not occurred.
  • 1 A Master Clear (pin) Reset has occurred.
SWR6Software Reset Flag bit
  • 0 A Software Commanded Reset has not occurred.
  • 1 A Software Commanded Reset has occurred.
DMTO5Deadman Timer Time-Out Flag bit
  • 0 DMT Time-out has not occurred.
  • 1 DMT Time-out has occurred and caused a reset.
WDTO4Watchdog Timer Time-Out Flag bit
  • 0 WDT Time-out has not occurred.
  • 1 WDT Time-out has occurred and caused a reset.
SLEEP3Wake from Sleep Flag bit
  • 0 Device has not been in Sleep mode.
  • 1 Device has been in Sleep mode.
IDLE2Wake from Idle Flag bit
  • 0 Device was not in Idle mode.
  • 1 Device was in Idle mode.
BOR1Brown-out Reset Flag bit
  • 0 A Brown-out Reset has not occurred.
  • 1 A Brown-out Reset has occurred.
POR0Power-On Reset Flag bit
  • 0 A Power-up Reset has not occurred.
  • 1 A Power-up Reset has occurred.
PORIO31IO Voltage POR Flag bit
  • 0 A Power-up Reset has not occurred due to IO Voltage.
  • 1 A Power-up Reset has occurred due to IO Voltage.

RCONCLR

Address
0x44000A34
Reset
0x00000000
Access
read/write
Size
32-bit

RCONSET

Address
0x44000A38
Reset
0x00000000
Access
read/write
Size
32-bit

RCONINV

Address
0x44000A3C
Reset
0x00000000
Access
read/write
Size
32-bit

RSWRSTSOFTWARE RESET REGISTER

Address
0x44000A40
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
SWRST0Software Reset Trigger
  • 0 Do not enable software reset event
  • 1 Enable software reset event

RSWRSTCLR

Address
0x44000A44
Reset
0x00000000
Access
read/write
Size
32-bit

RSWRSTSET

Address
0x44000A48
Reset
0x00000000
Access
read/write
Size
32-bit

RSWRSTINV

Address
0x44000A4C
Reset
0x00000000
Access
read/write
Size
32-bit

RNMICONNMI CONTROL REGISTER

Address
0x44000A50
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DMTO25Deadman Timer Time-Out Flag bit
  • 0 DMT Time-out has not occurred.
  • 1 DMT Time-out has occurred and caused a NMI.
WDTR24Watchdog Timer Time-Out in Run Flag bit
  • 0 WDT Time-out has not occurred.
  • 1 WDT Time-out has occurred and caused a NMI.
SWNMI23Software NMI Trigger
  • 0 Writing a 0 to this bit will have no effect.
  • 1 Writing a 1 to this bit will cause an NMI to be generated
GNMI19External / Generic NMI Event
  • 0 A general NMI event has not been detected.
  • 1 A general NMI event has been detected and caused an NMI
LVD18Programmable Low Voltage Detect Event
  • 0 PLVD has not detected a low voltage condition
  • 1 PLVD has detected a low voltage condition and caused an NMI
CF17Clock Fail Detect bit
  • 0 FSCM has not detected clock failure
  • 1 FSCM has detected clock failure and caused an NMI
WDTS16Watch-Dog Timer Time-Out in Sleep Flag bit
  • 0 WDT Time-out has not occurred during sleep_mode.
  • 1 WDT Time-out has occurred during sleep_mode and caused a wake-up from sleep.
NMICNT15:0NMI Reset counter value
  • 0 No delay between NMI assertion and device reset event
  • 1 1 sys_clk cycle that Software has to clear the NMI event before a device reset is performed.
  • 2 2 sys_clk cycles that Software has to clear the NMI event before a device reset is performed.
  • 65535 65535 sys_clk cycles that Software has to clear the NMI event before a device reset is performed.

RNMICONCLR

Address
0x44000A54
Reset
0x00000000
Access
read/write
Size
32-bit

RNMICONSET

Address
0x44000A58
Reset
0x00000000
Access
read/write
Size
32-bit

RNMICONINV

Address
0x44000A5C
Reset
0x00000000
Access
read/write
Size
32-bit