WFI32E03 configuration bits
The configuration words (DEVCFG0 to DEVCFG3, and on the newer chips the code-protect, signature and boot words) sit in boot flash and set the oscillator and PLL, the watchdog, the debugger pins, code protection and the peripheral options the chip starts with. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file, and an erased bit reads 1. In XC32 each setting is a #pragma config FNOSC = FRCPLL line.
FUSERID · 0xBFC55F88 0x0000FFFF default 0x0000FFFF USERID User ID DEVCFG4 · 0xBFC55F8C 0x04180000 default 0x04180000 SOSCEN Secondary Oscillator Enable Disabled Enabled DSEN Deep Sleep Enable Disabled Enabled DSWDTEN Deep Sleep Watchdog Timer Enable Disabled Enabled DSWDTOSC Deep Sleep WDT Reference Clock Selection Select SOSC as DSWDT Reference Clock Select LPRC as DSWDT Reference Clock DSWDTPS Deep Sleep Watchdog Timer Postscaler 1:2^5 1:2^6 1:2^7 1:2^8 1:2^9 1:2^10 1:2^11 1:2^12 1:2^13 1:2^14 1:2^15 1:2^16 1:2^17 1:2^18 1:2^19 1:2^20 1:2^21 1:2^22 1:2^23 1:2^24 1:2^25 1:2^26 1:2^27 1:2^28 1:2^29 1:2^30 1:2^31 1:2^32 1:2^33 1:2^34 1:2^35 1:2^36 DSZPBOREN Deep Sleep Zero-Power BOR Enable bit Disabled Enabled VBZPBOREN VBAT Zero-Power BOR Enable bit Disabled Enabled SOSCCFG SOSC Configuration Bits DEVCFG2 · 0xBFC55F90 0x037FFE30 default 0x037FFE30 DMTCNT Dead Man Timer Count Select bits 2^8 (256) 2^9 (512) 2^10 (1024) 2^11 (2048) 2^12 (4096) 2^13 (8192) 2^14 (16384) 2^15 (32768) 2^16 (65536) 2^17 (131072) 2^18 (262144) 2^19 (524288) 2^20 (1048576) 2^21 (2097152) 2^22 (4194304) 2^23 (8388608) 2^24 (16777216) 2^25 (33554432) 2^26 (67108864) 2^27 (134217728) 2^28 (268435456) 2^29 (536870912) 2^30 (1073741824) 2^31 (2147483648) WINSZ Watchdog Timer Window Size Window size is 75% Window size is 50% Window size is 37.5% Window size is 25% WDTEN Watchdog Timer Enable bit WDT Disabled WDT Enabled WINDIS Watchdog Timer Window Mode Watchdog Timer is in Window mode Watchdog Timer is in non-Window mode WDTSPGM Watchdog Timer Stop During Flash Programming WDT runs during Flash programming WDT stops during Flash programming WDTPS Run mode watchdog timer postscaler 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 31 (not named) FSCMEN Fail safe clock monitor enabled FSCM Disabled FSCM Enabled CKSWEN software clock switching enable Software Clock Switching Disabled Software Clock Switching Enabled WAKE2SPD 2 speed startup control for sleep mode the sys_clk will be from the selected clock on wakeup the sys_clk will be from FRC until the selected clock is ready on wakeup SOSCSEL Secondary Oscillator selection Digital (SCLKI) mode Crystal (SOSCI/SOSCO) mode WDTRMCS WDT Run mode clock selection Peripheral bus clock used as WDT run mode clock source LPRC used as WDT run mode clock source POSCMOD Primary Oscillator Configuration HS oscillator mode selected Primary oscillator disabled DMTINTV DMT Count Window Interval Window/Interval value is zero Window/Interval value is 1/2 counter value Window/Interval value is 3/4 counter value Window/Interval value is 7/8 counter value Window/Interval value is 15/16 counter value Window/Interval value is 31/32 counter value Window/Interval value is 63/64 counter value Window/Interval value is 127/128 counter value DMTEN Deadman Timer Enable Deadman Timer is disabled Deadman Timer is enabled DEVCFG1 · 0xBFC55F94 0x00005C3B default 0x00005C3B WDTPSS Watchdog Timer Post-scale Select Sleep bits 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1:1048576 USBDPTRIM USB DP Rise/Fall Trim fuse bits USBDMTRIM USB DM Rise/Fall Trim fuse bits HSUARTEN UART1 High Speed Mode Enable UART1 is driven through PPS (I/O remap), resulting in a lower maximum baud rate UART1 is driven from/to dedicated pins, resulting in the highest possible maximum baud rate SMCLR Selects CRU handling of MCLR Control MCLR causes a faux POR Legacy mode (system clear does not reset all state of device) HSSPIEN SPI1 High Speed Mode Enable SPI1 is driven through PPS (I/O remap), resulting in a lower interface speed SPI1 is driven from/to dedicated pins, resulting in the highest interface speed VBUSIO USB VBUS_ON Selection bit VBUS_ON pin is controlled by the Port Function VBUS_ON pin is controlled by the USB Module USBIDIO USB USBID Selection bit USBID pin is controlled by the Port Function USBID pin is controlled by the USB Module CLASSBDIS Disable CLASSB Device Functionality CLASSB functions enabled CLASSB functions disabled ETHEXEREF Exclusive Ethernet PYHY reference clock Enable ETH CLK out will be used as PHY reference clock if needed PHY reference clock is made available on ETH EXCLK out FMIIEN Ethernet RMII/MII Enable RMII Enabled MII Enabled TRCEN Trace Enable Trace features in the CPU are disabled Trace features in the CPU are enabled ICESEL EMUC/EMUD Communication Channel Select ICE EMUC4/EMUD4 pins are shared with PGC4/PGD4 ICE EMUC3/EMUD3 pins are shared with PGC3/PGD3 ICE EMUC2/EMUD2 pins are shared with PGC2/PGD2 ICE EMUC1/EMUD1 pins are shared with PGC1/PGD1 DEBUG Background Debugger Access Selection EMUC/EMUD Enabled - 4-wire JTAG I/F Disabled - ICD Module Enabled EMUC/EMUD Enabled - 4-wire JTAG I/F Disabled - ICD Module Disabled 4-wire JTAG I/F Enabled - EMUC/EMUD Disabled - ICD Module Enabled 4-wire JTAG I/F Enabled - EMUC/EMUD Disabled - ICD Module Disabled DEVCFG0 · 0xBFC55F98 0x20800009 default 0x20800009 ETHTPSF Ethernet Tx SOF control for CTR measurements RPSF is enabled in CTR measurement TPSF is enabled in CTR measurement FECCCON Dynamic Flash ECC Configuration Flash ECC is enabled Dynamic Flash ECC is enabled ECC and Dynamic ECC are disabled ETHPLLHWMD Ethernet PLL HW Control Mode for power down and RESET ETHPLL PWDN and RESET are generated by SW using corresponding PLLCON register bits ETHPLL PWDN and RESET are generated by HW BTPLLHWMD BTPLL HW Control Mode for power down and RESET BTPLL PWDN and RESET are generated by SW using corresponding PLLCON register bits BTPLL PWDN and RESET are generated by HW SPLLHWMD SPLL HW Control Mode for power down and RESET SPLL PWDN and RESET are generated by SW using corresponding PLLCON register bits SPLL PWDN and RESET are generated by HW UPLLHWMD UPLL HW Control Mode for power down and RESET UPLL PWDN and RESET are generated by SW using corresponding PLLCON register bits UPLL PWDN and RESET are generated by HW PCM P-Cache cache-ability control PCHE cache-ability is controlled by CPU PCHE cache-ability is controled by SFR CANFDDIV CAN-FD divider control IC_ACLK ICAP Alternate Clock Selection All ICAP Modules use TMR2/TMR3 as their timebase clock ICAP module use an alternative TMR pair as their timebase clock OC_ACLK OCMP Alternate Clock Selection All OCMP Modules use TMR2/TMR3 as their timebase clock OCMP module use an alternative TMR pair as their timebase clock CFGLOCK Configuration Register Lock All NVR memory self-writes, BCFG0 and System Config registers, are not locked and can be written - CFGLOCK value can be changed All NVR memory self-writes, BCFG0 and System Config registers, are locked and can not be written - CFGLOCK value can be changed All NVR memory self-writes, BCFG0 and System Config registers, are locked and can not be written - CFGLOCK value can not be changed IOLOCK IO LOCK IO Remap SFR are not locked and can be modified IO Remap SFR bits are locked and cannot be modified PMDLOCK Peripheral Module Disable (PMD) LOCK PMDx SFR bits are not locked and can be modified PMDx SFR bits are locked and cannot be modified PGLOCK Permission Group LOCK CFGPG SFR bits are not locked and can be modified CFGPG SFR bits are locked and cannot be modified PMULOCK PMU Controller Register LOCK PMU SFR bits are not locked and can be modified PMU SFR bits are locked and cannot be modified USBSSEN USB Suspend Sleep Enable USB FREF clock continues to run when suspend mode is active USB FREF clock is shut down when suspend mode is active EXLPRI CPU RAM access priority CPU gets least recently used arbitration to RAM CPU gets high priority access to RAM DMAPRI DMA RAM access priority DMA gets least recently used arbitration to RAM DMA gets High Priority access to SRAM FCPRI Flash controller RAMa ccess priority flash gets least recently used arbitration to RAM flash gets higher priority access to RAM JTAGEN JTAG control bit JTAG port disabled JTAG port enabled TROEN Trace clock control bit Stop Trace Clock and disable Trace Outputs Start Trace Clock and enable Trace Outputs (Trace Probe must be present) TDOEN TDO control for 2 wire JTAG protocol 2-wire JTAG protocol does not use TDO 2-wire JTAG protocol uses TDO EPGMCLK External Programming Clock enable In ICSP (TMOD0) mode, the FRC clock is always driven by the FRC oscillator In ICSP (TMOD0) mode, enable the FRC clock to be driven by the TSTFRC Pin Function FBCFG0 · 0xBFC55F9C 0x00000009 default 0x00000009 BOOTISA Boot and exception code mode Boot code and Exception code is microMIPS Boot code and Exception code is MIPS32 PCSCMODE PCache Single cache Mode PCHE ICache and DCache. CPU opcodes go to PCEHE ICache port and data goes to PCHE PCHE ICache Only.CPU Instructions (code, data) go to PCHE ONLY. BUHSWEN Buck mode switching control Buck switching is disabled in HW at POR. Enable from SW Buck mode is switched in HW at POR before CPU is allowed to boot FCPN0 · 0xBFC55FBC 0xFFFFFFFF default 0xFFFFFFFF CP Code Protect Code protection enabled Code protection disabled 
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