Real View
ADC08048-bit parallel SAR ADC
Measure an analog voltage. Read an eight-bit result.
ADC0804 is an 8-bit successive-approximation analog-to-digital converter with a parallel data bus. It measures VIN+ relative to VIN− and stores a code from 0 to 255, which a controller reads using active-LOW chip-select and read signals. A conversion starts with a write strobe, and the interrupt output signals completion. The reference at VREF/2 sets half the input span; leaving it open derives the span from the supply. A nominal 5 V span gives a 19.53125 mV ideal step. This page shows the documented ADC0804LCN PDIP-20 and ADC0804LCWM/NOPB wide SOIC-20 forms. The current TI ordering table lists SOIC variants; the through-hole view remains useful for existing boards. Reference values here use the commercial 0–70°C grades.
Clock & controlData & statusAnalog inputs & referenceSupply & grounds
ADC0804PDIP-20Top view
ADC0804SOIC-20 wideTop view
Click a lead or use the arrow keys. Top view
PIN 1 · Clock & control
Active-LOW chip select/CS
Function
Enables the read and conversion-control interface when LOW.
How to connect
Connect to the controller chip-select output.
PIN 2 · Clock & control
Active-LOW read/RD
Function
With /CS LOW, enables the stored conversion result on DB0–DB7.
How to connect
Controller read strobe; keep HIGH outside a read.
Electrical note
Outputs are high impedance when /CS or /RD is HIGH.
PIN 3 · Clock & control
Active-LOW conversion strobe/WR
Function
With /CS LOW, pulse LOW then HIGH to start a conversion.
How to connect
Controller output; allow the conversion to finish before restarting.
Electrical note
Holding /CS and /WR LOW holds the converter in reset; an early restart does not update the previous result.
PIN 4 · Clock & control
Clock inputCLK IN
Function
External clock input or the RC clock timing node.
How to connect
Apply a clean 640 kHz, 0–5 V clock for the example.
Electrical note
Use the separate clock thresholds; they differ from /CS, /RD and /WR.
PIN 5 · Data & status
Active-LOW completion/INTR
Function
Goes LOW after a completed conversion. Read/start control clears it according to the device timing.
How to connect
Connect to a controller input.
Electrical note
Wait for completion before reading; follow the manufacturer read/write timing.
PIN 6 · Analog inputs & reference
Positive analog inputVIN+
Function
Positive input of the differential converter.
How to connect
Apply a low-impedance, stable 0–5 V signal.
Electrical note
Keep both analog inputs inside the supply rails for the teaching circuit.
PIN 7 · Analog inputs & reference
Negative analog inputVIN−
Function
Subtracts a fixed offset from VIN+.
How to connect
Ground for a zero-based measurement.
Electrical note
VIN+ ≤ VIN− produces code zero; this is a unipolar converter, not a signed-output ADC.
PIN 8 · Supply & grounds
Analog groundA GND
Function
Return for the analog ladder and signal reference.
How to connect
Join to D GND with a low-noise ground layout.
PIN 9 · Analog inputs & reference
Half-span referenceVREF/2
Function
Sets the nominal input span to twice the applied reference voltage.
How to connect
Leave open for supply-derived reference, or use a suitable low-impedance reference.
Electrical note
For ADC0804LCN/LCWM, input resistance is 1.1 kΩ typical, 0.75 kΩ minimum; account for reference loading.
PIN 10 · Supply & grounds
Digital groundD GND
Function
Return for digital logic and outputs.
How to connect
Connect to ground and A GND.
PIN 11 · Data & status
Tri-state data outputDB7
Function
Bit 7 of the latched 8-bit conversion result; weight 128.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 12 · Data & status
Tri-state data outputDB6
Function
Bit 6 of the latched 8-bit conversion result; weight 64.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 13 · Data & status
Tri-state data outputDB5
Function
Bit 5 of the latched 8-bit conversion result; weight 32.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 14 · Data & status
Tri-state data outputDB4
Function
Bit 4 of the latched 8-bit conversion result; weight 16.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 15 · Data & status
Tri-state data outputDB3
Function
Bit 3 of the latched 8-bit conversion result; weight 8.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 16 · Data & status
Tri-state data outputDB2
Function
Bit 2 of the latched 8-bit conversion result; weight 4.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 17 · Data & status
Tri-state data outputDB1
Function
Bit 1 of the latched 8-bit conversion result; weight 2.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 18 · Data & status
Tri-state data outputDB0
Function
Bit 0 of the latched 8-bit conversion result; weight 1.
How to connect
Connect to the matching controller data input.
Electrical note
Read only with /CS and /RD LOW. High impedance is not logic zero.
PIN 19 · Data & status
RC clock feedback outputCLK R
Function
Feedback connection for the optional resistor to CLK IN.
How to connect
Leave open when using the external clock example.
Electrical note
Avoid heavy loading; do not treat this as a general-purpose logic output.
PIN 20 · Supply & grounds
Positive supply and ladder referenceVCC
Function
Supplies the converter and sets the default span when VREF/2 is open.
How to connect
Regulated +5 V with local 100 nF bypass.
Electrical note
Recommended supply section specifies 4.5–5.5 V.
At a glance
8-bit parallel SAR ADC
A comparator and ladder test successive trial values. The output latch holds the completed code, while /CS and /RD decide whether it drives the data bus.
8 bits · 256 codesResolution
5 VNominal supply
103 µs · 640 kHz clockTypical conversion
0–70 °CCommercial ambient
Operating profile
ADC0804LCN
Supply and input range
Key parameters and their test conditions
- Recommended supply
- 4.5–5.5 VConditions / notes: Recommended operating conditions section; 5 V example
- Commercial temperature
- 0–70°CConditions / notes: LCN and LCWM grades
- Differential input
- VIN+ − VIN−Conditions / notes: Both pins must stay within the permitted common-mode range
- Analog pin range
- GND − 0.05 to VCC + 0.05 VConditions / notes: Manufacturer rating; example stays between GND and VCC
- Reference span
- 2 × VREF/2Conditions / notes: Open reference pin gives a supply-derived span
- Negative differential input
- Code 0Conditions / notes: Unipolar result, not signed arithmetic
Package details
Follows the selected physical package
- Manufacturer
- Texas Instruments
- Part number
- ADC0804LCN
- Package
- PDIP-20
- Connections
- 20 pins
- Mounting
- Through-hole
- Lead pitch
- 2.54 mm
- Package code
- dip
- Thermal reference
- Board and package dependent; see manufacturer data
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Clock & control4 pins
Data & status10 pins
Analog inputs & reference3 pins
Supply & grounds3 pins
Clock & control4 pins
Data & status10 pins
Analog inputs & reference3 pins
Supply & grounds3 pins
Define the input span
Use VIN− as the offset reference. Twice VREF/2 sets the nominal span; an open VREF/2 uses the supply-derived reference.
Start and wait
With /CS LOW, pulse /WR LOW then HIGH. The SAR compares trial ladder levels and /INTR goes LOW on completion.
Read the stored byte
Take /RD LOW while /CS is LOW. Read DB7–DB0, then release /RD. The bus returns to high impedance without erasing the stored code.
Resolution, accuracy and conversion time are different limits. Eight bits provide 256 ideal codes; ADC0804 has a specified ±1 LSB total unadjusted error under the stated reference conditions. The teaching explorer shows an ideal transfer, not a timed conversion.
Turn voltage into eight bits
Explore differential input, reference span and the tri-state read bus.
The ideal code updates immediately. Both /CS and /RD must be LOW to enable the eight data outputs. Conversion handshaking is explained in the reference tables.
IDEAL DECIMAL CODE128
0x8010000000
Data bus enabled.Input difference2.5000 V
Reference span5.000 V
One LSB19.5313 mV
Code-centre voltage2.5000 V
DB7Pin 11HIGH · 1
DB6Pin 12LOW · 0
DB5Pin 13LOW · 0
DB4Pin 14LOW · 0
DB3Pin 15LOW · 0
DB2Pin 16LOW · 0
DB1Pin 17LOW · 0
DB0Pin 18LOW · 0
Ideal static transfer with half-LSB transitions and saturation to codes 0–255. It excludes conversion timing, analog noise and device error. Code-centre voltage is a nominal reconstructed value, not the exact measured input. Reference/2 is bounded to 0.5–2.5 V here for exploration.
Pin reference
Select a pin to explore its function and connection.
20 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| /CS | Active-LOW chip select | Enables the read and conversion-control interface when LOW. | |
| /RD | Active-LOW read | With /CS LOW, enables the stored conversion result on DB0–DB7. | |
| /WR | Active-LOW conversion strobe | With /CS LOW, pulse LOW then HIGH to start a conversion. | |
| CLK IN | Clock input | External clock input or the RC clock timing node. | |
| /INTR | Active-LOW completion | Goes LOW after a completed conversion. Read/start control clears it according to the device timing. | |
| VIN+ | Positive analog input | Positive input of the differential converter. | |
| VIN− | Negative analog input | Subtracts a fixed offset from VIN+. | |
| A GND | Analog ground | Return for the analog ladder and signal reference. | |
| VREF/2 | Half-span reference | Sets the nominal input span to twice the applied reference voltage. | |
| D GND | Digital ground | Return for digital logic and outputs. | |
| DB7 | Tri-state data output | Bit 7 of the latched 8-bit conversion result; weight 128. | |
| DB6 | Tri-state data output | Bit 6 of the latched 8-bit conversion result; weight 64. | |
| DB5 | Tri-state data output | Bit 5 of the latched 8-bit conversion result; weight 32. | |
| DB4 | Tri-state data output | Bit 4 of the latched 8-bit conversion result; weight 16. | |
| DB3 | Tri-state data output | Bit 3 of the latched 8-bit conversion result; weight 8. | |
| DB2 | Tri-state data output | Bit 2 of the latched 8-bit conversion result; weight 4. | |
| DB1 | Tri-state data output | Bit 1 of the latched 8-bit conversion result; weight 2. | |
| DB0 | Tri-state data output | Bit 0 of the latched 8-bit conversion result; weight 1. | |
| CLK R | RC clock feedback output | Feedback connection for the optional resistor to CLK IN. | |
| VCC | Positive supply and ladder reference | Supplies the converter and sets the default span when VREF/2 is open. |
No pins match. Try a signal name or choose All pins.
Supply and input range
ADC0804LCN / ADC0804LCWM
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Recommended supply | 4.5–5.5 V | Recommended operating conditions section; 5 V example |
| Commercial temperature | 0–70°C | LCN and LCWM grades |
| Differential input | VIN+ − VIN− | Both pins must stay within the permitted common-mode range |
| Analog pin range | GND − 0.05 to VCC + 0.05 V | Manufacturer rating; example stays between GND and VCC |
| Reference span | 2 × VREF/2 | Open reference pin gives a supply-derived span |
| Negative differential input | Code 0 | Unipolar result, not signed arithmetic |
No specifications match. Try a parameter name or a unit.
The legacy operating-ratings table also lists 6.3 V; this page follows the recommended 4.5–5.5 V supply section.
Conversion and accuracy
5 V · 640 kHz unless noted
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Resolution | 8 bits / 256 codes | Output codes 0–255 |
| Ideal LSB at 5 V span | 19.53125 mV | 5 V / 256 |
| Total unadjusted error | ±1 LSB | ADC0804; VREF/2 = 2.500 V |
| Conversion time | 103 µs typical; 114 µs maximum | Specified temperature range |
| Clock periods per conversion | 66 typical; 73 maximum | Asynchronous start timing included |
| Clock range | 100–1460 kHz | Accuracy specified at 640 kHz |
| Clock duty cycle | 40–60% | At specified clock conditions |
No specifications match. Try a parameter name or a unit.
Do not substitute ADC0801 or ADC0802 accuracy grades. Faster clocks can reduce accuracy.
Read and write controls
Active-LOW parallel interface
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| /CS HIGH | Data bus Hi-Z | Read and conversion-control interface not selected |
| /CS LOW, /WR LOW | Reset/start request | Hold for at least the required strobe width |
| /WR rising with /CS LOW | Start conversion | Wait for /INTR LOW |
| /CS LOW, /RD LOW | Drive stored DB7–DB0 | Read after conversion completion |
| /RD HIGH or /CS HIGH | Data bus Hi-Z | Stored result remains latched |
| Minimum /WR LOW pulse | 100 ns | /CS LOW |
| Read access delay | 135 ns typical; 200 ns maximum | CL = 100 pF |
| Data release to Hi-Z | 125 ns typical; 200 ns maximum | CL = 10 pF; RL = 10 kΩ |
No specifications match. Try a parameter name or a unit.
Restarting before completion preserves the previous result. The explorer displays settled transfer and bus-enable behavior only.
Reference, logic and power
Manufacturer test conditions
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Control input HIGH / LOW | ≥ 2.0 V / ≤ 0.8 V | Excludes CLK IN; see specified supply test conditions |
| CLK IN rising threshold | 2.7 / 3.1 / 3.5 V | Minimum / typical / maximum |
| CLK IN falling threshold | 1.5 / 1.8 / 2.1 V | Minimum / typical / maximum |
| Data-output LOW | ≤ 0.4 V at 1.6 mA | VCC = 4.75 V |
| Output HIGH | ≥ 2.4 V at −360 µA | ≥ 4.5 V at −10 µA; VCC = 4.75 V |
| Reference/2 resistance | 0.75 kΩ minimum; 1.1 kΩ typical | LCN/LCWM reference loading |
| Supply current | 1.9 mA typical; 2.5 mA maximum | 25°C, 640 kHz, VREF/2 open, /CS = 5 V |
No specifications match. Try a parameter name or a unit.
Logic output voltages depend on load; do not assume every HIGH equals VCC.
Controller interface circuit
External clock · supply-derived span
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Analog source | Stable 0–5 V into VIN+6 | Low impedance; VIN−7 to GND |
| Reference pin9 | Open | Uses supply-derived reference; no external reference is shown |
| External clock | 640 kHz into CLK IN4 | 0–5 V, 50% duty; CLK R19 open |
| Control signals | /CS1, /RD2, /WR3 | Controller outputs with defined idle states |
| Completion signal | /INTR5 | Controller input |
| Data byte | DB0 pin18 through DB7 pin11 | Controller input bus; bit order matters |
| Ground and bypass | A GND8 / D GND10 / VCC20 | Common ground; 100 nF close to supply pins |
No specifications match. Try a parameter name or a unit.
For each measurement, assert /CS, pulse /WR, wait for /INTR LOW, then read with /RD LOW. This is not the separate free-running connection.
Absolute maximum ratings
Stress limits, not operating settings
Manufacturer specifications 5 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply voltage | 6.5 V maximum | Use recommended supply for operation |
| Logic control inputs | −0.3 to +18 V | Stress rating; not the example drive voltage |
| Other input/output pins | −0.3 to VCC + 0.3 V | Includes analog inputs |
| Package dissipation at 25°C | 875 mW | Thermal conditions and derating apply |
| Storage temperature | −65 to +150°C | Unpowered storage |
No specifications match. Try a parameter name or a unit.
Stay within recommended operating and input conditions during normal use.
Sensor digitization
Convert conditioned analog sensor voltages into a parallel byte.
Manufacturer application guideLegacy controller interfaces
Connect an 8-bit microprocessor bus with chip-select, read, write and interrupt timing.
Manufacturer application guideReference-span experiments
Explore resolution, offset and saturation while keeping both analog inputs in range.
Manufacturer application guideTake it into ProTech
Find ADC0804 in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech