Real View
CD4017BDecade counter / divider
One clock. Ten steps. A visible sequence.
CD4017B is a decade counter with ten decoded outputs. Each accepted rising clock edge advances the HIGH output from Q0 through Q9, then returns to Q0. It uses a five-stage Johnson counter and decode logic inside one 16-pin IC. RESET is asynchronous and active HIGH. CLOCK INHIBIT holds the count when HIGH; the carry output is HIGH during counts 0–4 and LOW during counts 5–9. Reset the real device after power-up to establish a known starting state. This reference covers CD4017BE through-hole and CD4017BM96 surface-mount packages. The explorer starts from an applied reset and shows settled logic states; the circuit uses a clean 5 V clock and low-current LED indicators.
Decoded outputs & carrySupply & returnClock & control
CD4017BEPDIP-16Top view
CD4017BM96SOIC-16Top view
Click a lead or use the arrow keys. Top view
PIN 1 · Decoded outputs & carry
Decoded push-pull outputQ5
Function
HIGH at count 5; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 2 · Decoded outputs & carry
Decoded push-pull outputQ1
Function
HIGH at count 1; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Connect through 10 kΩ to a high-efficiency red LED, with its cathode to ground.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 3 · Decoded outputs & carry
Decoded push-pull outputQ0
Function
HIGH at count 0; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Connect through 10 kΩ to a high-efficiency red LED, with its cathode to ground.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 4 · Decoded outputs & carry
Decoded push-pull outputQ2
Function
HIGH at count 2; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Connect through 10 kΩ to a high-efficiency red LED, with its cathode to ground.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 5 · Decoded outputs & carry
Decoded push-pull outputQ6
Function
HIGH at count 6; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 6 · Decoded outputs & carry
Decoded push-pull outputQ7
Function
HIGH at count 7; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 7 · Decoded outputs & carry
Decoded push-pull outputQ3
Function
HIGH at count 3; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 8 · Supply & return
Ground returnVSS
Function
Common return for the logic and output loads.
How to connect
Connect to supply negative and the bypass return.
PIN 9 · Decoded outputs & carry
Decoded push-pull outputQ8
Function
HIGH at count 8; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 10 · Decoded outputs & carry
Decoded push-pull outputQ4
Function
HIGH at count 4; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 11 · Decoded outputs & carry
Decoded push-pull outputQ9
Function
HIGH at count 9; LOW in the other nine states. Only one decoded output is HIGH at a time.
How to connect
Leave open in the three-LED example.
Electrical note
Output drive is limited and depends on supply voltage and temperature.
PIN 12 · Decoded outputs & carry
Divide-by-ten outputCARRY
Function
HIGH for counts 0–4 and LOW for counts 5–9. It completes one cycle for every ten input pulses.
How to connect
Leave open in the LED example; use a reviewed cascade connection for additional decades.
Electrical note
Carry is a five-count-wide state, not a narrow pulse at Q9.
PIN 13 · Clock & control
Clock inhibitINHIBIT
Function
HIGH prevents advancement from clock pin 14. LOW allows counting.
How to connect
Connect to ground for continuous counting.
Electrical note
A HIGH-to-LOW transition here can count if clock14 is held HIGH; keep inhibit stable around clock edges.
PIN 14 · Clock & control
Schmitt clock inputCLOCK
Function
A LOW-to-HIGH clock transition advances the count when inhibit is LOW and reset is LOW.
How to connect
Use a clean 0–5 V, 1 Hz logic clock in the example.
Electrical note
Schmitt action permits slow clock edges; it does not remove mechanical switch bounce.
PIN 15 · Clock & control
Asynchronous active-HIGH resetRESET
Function
HIGH selects count zero immediately: Q0 HIGH, Q1–Q9 LOW and carry HIGH.
How to connect
Use a momentary switch to +5 V and a 10 kΩ pull-down. Pulse it after power-up.
Electrical note
Hold LOW while counting. A deterministic starting state requires reset.
PIN 16 · Supply & return
Positive supplyVDD
Function
Supplies the counter, decoder and output buffers.
How to connect
Use regulated +5 V and a local 100 nF capacitor to VSS8.
Electrical note
Recommended operating supply: 3–18 V.
At a glance
Decade counter / divider
A clean clock advances the decoded HIGH output. Reset returns to Q0, while inhibit freezes the count. Carry supplies a divide-by-ten waveform.
10 One HIGH outputDecoded states
3–18 VOperating supply
16 PDIP or SOICPackage leads
−55–125 °CAmbient range
Operating profile
CD4017BE
Decoded output sequence
Key parameters and their test conditions
- Count 0
- Q0 HIGH · pin 3Conditions / notes: All other Q outputs LOW; carry HIGH
- Count 1
- Q1 HIGH · pin 2Conditions / notes: All other Q outputs LOW; carry HIGH
- Count 2
- Q2 HIGH · pin 4Conditions / notes: All other Q outputs LOW; carry HIGH
- Count 3
- Q3 HIGH · pin 7Conditions / notes: All other Q outputs LOW; carry HIGH
- Count 4
- Q4 HIGH · pin 10Conditions / notes: All other Q outputs LOW; carry HIGH
- Count 5
- Q5 HIGH · pin 1Conditions / notes: All other Q outputs LOW; carry LOW
Package details
Follows the selected physical package
- Manufacturer
- Texas Instruments
- Part number
- CD4017BE
- Package
- PDIP-16
- Connections
- 16 pins
- Mounting
- Through-hole
- Lead pitch
- 2.54 mm
- Package code
- dip
- Thermal reference
- Board and package dependent; see manufacturer data
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Decoded outputs & carry11 pins
Supply & return2 pins
Clock & control3 pins
Decoded outputs & carry11 pins
Supply & return2 pins
Clock & control3 pins
Establish the start
Pulse RESET HIGH after power-up, then return it LOW. Q0 becomes HIGH and carry is HIGH.
Advance on a clock edge
With INHIBIT LOW, each rising edge on CLOCK advances to the next output. Q9 wraps back to Q0.
Hold or cascade
Set INHIBIT HIGH to hold. Carry is HIGH for the first five states and LOW for the next five, providing divide-by-ten timing.
CD4017B stores a count, so the current output depends on previous clock edges. Reset establishes Q0, inhibit holds the state and carry divides the accepted clock by ten. It is not a binary-output counter.
Walk through ten output states
Pulse the clock, hold the count or reset immediately to Q0.
Pulse sends LOW → HIGH → LOW. With inhibit HIGH, clock pulses hold the count. Reset HIGH immediately selects Q0 and keeps it selected.
Releasing inhibit while the clock is already HIGH also advances the hardware counter. Try it with the individual controls.
COUNT0Q0 selected · ready for a rising clock edge
CARRY OUT · Pin 12HIGH · 1
Q0Pin 3HIGH
Q1Pin 2LOW
Q2Pin 4LOW
Q3Pin 7LOW
Q4Pin 10LOW
Q5Pin 1LOW
Q6Pin 5LOW
Q7Pin 6LOW
Q8Pin 9LOW
Q9Pin 11LOW
Starts after an applied reset. Shows settled logic only; propagation delay, switch bounce, analog thresholds and output loading are not simulated. Carry is HIGH for counts 0–4, LOW for counts 5–9.
Pin reference
Select a pin to explore its function and connection.
16 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| Q5 | Decoded push-pull output | HIGH at count 5; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q1 | Decoded push-pull output | HIGH at count 1; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q0 | Decoded push-pull output | HIGH at count 0; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q2 | Decoded push-pull output | HIGH at count 2; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q6 | Decoded push-pull output | HIGH at count 6; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q7 | Decoded push-pull output | HIGH at count 7; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q3 | Decoded push-pull output | HIGH at count 3; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| VSS | Ground return | Common return for the logic and output loads. | |
| Q8 | Decoded push-pull output | HIGH at count 8; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q4 | Decoded push-pull output | HIGH at count 4; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| Q9 | Decoded push-pull output | HIGH at count 9; LOW in the other nine states. Only one decoded output is HIGH at a time. | |
| CARRY | Divide-by-ten output | HIGH for counts 0–4 and LOW for counts 5–9. It completes one cycle for every ten input pulses. | |
| INHIBIT | Clock inhibit | HIGH prevents advancement from clock pin 14. LOW allows counting. | |
| CLOCK | Schmitt clock input | A LOW-to-HIGH clock transition advances the count when inhibit is LOW and reset is LOW. | |
| RESET | Asynchronous active-HIGH reset | HIGH selects count zero immediately: Q0 HIGH, Q1–Q9 LOW and carry HIGH. | |
| VDD | Positive supply | Supplies the counter, decoder and output buffers. |
No pins match. Try a signal name or choose All pins.
Decoded output sequence
RESET establishes state zero
Manufacturer specifications 10 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Count 0 | Q0 HIGH · pin 3 | All other Q outputs LOW; carry HIGH |
| Count 1 | Q1 HIGH · pin 2 | All other Q outputs LOW; carry HIGH |
| Count 2 | Q2 HIGH · pin 4 | All other Q outputs LOW; carry HIGH |
| Count 3 | Q3 HIGH · pin 7 | All other Q outputs LOW; carry HIGH |
| Count 4 | Q4 HIGH · pin 10 | All other Q outputs LOW; carry HIGH |
| Count 5 | Q5 HIGH · pin 1 | All other Q outputs LOW; carry LOW |
| Count 6 | Q6 HIGH · pin 5 | All other Q outputs LOW; carry LOW |
| Count 7 | Q7 HIGH · pin 6 | All other Q outputs LOW; carry LOW |
| Count 8 | Q8 HIGH · pin 9 | All other Q outputs LOW; carry LOW |
| Count 9 | Q9 HIGH · pin 11 | All other Q outputs LOW; carry LOW |
No specifications match. Try a parameter name or a unit.
After Q9, the next accepted clock edge returns to Q0.
Supply and control conditions
CD4017BE / CD4017BM96
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Operating supply | 3–18 V | 5 V in the example |
| Operating temperature | −55 to +125°C | Selected package grades |
| HIGH input at 5 V | At least 3.5 V | Manufacturer static test conditions |
| LOW input at 5 V | At most 1.5 V | Manufacturer static test conditions |
| Clock input | Rising-edge counting | INHIBIT LOW; RESET LOW |
| Reset input | HIGH selects Q0 | Asynchronous; no clock required |
| Clock inhibit | HIGH holds the count | Falling inhibit can count if CLOCK is HIGH |
| Clock14 rise / fall time | No specified limit | Schmitt action on CLOCK14; not a debounce function |
No specifications match. Try a parameter name or a unit.
The alternate clock use of pin13 has different transition requirements; see the manufacturer footnote.
Electrical reference
5 V supply unless stated
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Source at VOH = 4.6 V | 0.51 mA minimum at 25°C | 0.36 mA minimum at 125°C; manufacturer test |
| Sink at VOL = 0.4 V | 0.51 mA minimum at 25°C | 0.36 mA minimum at 125°C; manufacturer test |
| No-load output HIGH | At least 4.95 V | 5 V supply |
| No-load output LOW | At most 0.05 V | 5 V supply |
| Quiescent current | 0.04 µA typical; 5 µA maximum | 25°C, 5 V, inputs at supply rails |
| Quiescent current over temperature | 150 µA maximum at 5 V | 85°C and 125°C entries |
| Input capacitance | 5 pF typical | Any input |
No specifications match. Try a parameter name or a unit.
Do not read output current from the absolute stress limits. LED loads lower the HIGH level and increase current consumption.
Clock and reset timing
25°C · CL = 50 pF · RL = 200 kΩ
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Clock-to-decoded output | 325 ns typical; 650 ns maximum | 5 V; input transitions 20 ns |
| Clock-to-carry output | 300 ns typical; 600 ns maximum | 5 V; input transitions 20 ns |
| Clock frequency capability | 2.5 MHz minimum; 5 MHz typical | 5 V; measured with carry output |
| Minimum clock pulse width | 200 ns | 5 V recommended condition |
| Inhibit setup time | 230 ns | 5 V before the clock edge |
| Reset pulse width | 260 ns minimum | 5 V recommended condition |
| Reset removal time | 400 ns minimum | 5 V recommended condition |
No specifications match. Try a parameter name or a unit.
Typical speed is not a guarantee for every supply, load and temperature. The manual explorer does not reproduce these delays.
Three-LED sequence circuit
A clean 1 Hz, 0–5 V clock
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Clock input | Pin 14 | Common-ground logic clock |
| Clock inhibit | Pin 13 → GND | Allows counting |
| Reset network | Pin 15 → 10 kΩ → GND | Momentary switch to +5 V; pulse at startup |
| LED channels | Q0 pin 3, Q1 pin 2, Q2 pin 4 | One 10 kΩ series resistor per LED |
| LED current estimate | About 0.3 mA per active LED | Ideal 5 V HIGH and 2 V red LED |
| Supply bypass | 100 nF between pins 16 and 8 | Place close to the IC |
| Unused outputs and carry | Leave open | Counts 3–9 have no lit LED in this example |
No specifications match. Try a parameter name or a unit.
Use high-efficiency LEDs for this small drive current, or external drivers for bright/multiple loads. A manual clock switch requires debouncing.
Absolute maximum ratings
Stress limits, not operating settings
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply voltage | −0.5 to +20 V | Recommended operation is 3–18 V |
| Input voltage | −0.5 V to VDD + 0.5 V | Referenced to VSS |
| Input current | ±10 mA | Any one input |
| Package dissipation | 500 mW through 100°C | Derate 12 mW/°C to 200 mW at 125°C |
| Output-transistor dissipation | 100 mW | Per output transistor |
| Storage temperature | −65 to +150°C | Unpowered storage |
No specifications match. Try a parameter name or a unit.
Supply and thermal stress ratings do not establish a safe output load.
LED sequencing
Light successive indicators with a clean clock and suitable current limiting.
Manufacturer application guideDivide-by-ten timing
Use the carry waveform to obtain one cycle for ten accepted clock pulses.
Manufacturer application guideSequence control
Use the decoded states as logic selections; buffer loads that exceed the available output drive.
Manufacturer application guideTake it into ProTech
Find CD4017B in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech