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CD4046BCMOS phase-locked loop with VCO
Compare phase. Control frequency. Build a feedback loop.
CD4046B combines a voltage-controlled oscillator and two different phase comparators in a 16-pin CMOS IC. External resistors and a capacitor establish the oscillator range; an analog control voltage changes its frequency. With feedback and an external low-pass filter, the oscillator can follow an incoming signal. Comparator I uses XOR logic, while comparator II compares rising edges and can leave its output in high impedance. Their capture behavior and phase relationships are different. Start with the illustrated 5 V oscillator: a potentiometer controls pin 9, a 10 nF capacitor joins pins 6 and 7, and 100 kΩ sets R1. The package switch compares CD4046BE PDIP-16 and CD4046BPWR TSSOP-16 with matching physical pin numbers.
Oscillator and comparator outputsPhase-comparator inputsOscillator controlTiming and analog signalsSupply and reference
CD4046BEPDIP-16Top view
CD4046BPWRTSSOP-16Top view
Click a lead or use the arrow keys. Top view
PIN 1 · Oscillator and comparator outputs
Phase-comparator-II indicatorPHASE PULSES
Function
Phase-pulse output associated with comparator II; HIGH when the two rising edges coincide in lock.
How to connect
Leave open in the standalone VCO circuit.
Electrical note
This is not a universal lock detector; interpret its pulses in the complete loop.
PIN 2 · Oscillator and comparator outputs
Exclusive-OR comparator outputPC I OUT
Function
Logic XOR of the conditioned signal and comparator inputs. Its average depends on phase and duty cycle.
How to connect
Leave open in the VCO circuit; use an appropriate external low-pass filter for PLL operation.
PIN 3 · Phase-comparator inputs
Feedback comparator inputCOMP IN
Function
Receives VCO output directly or through a divider in a PLL.
How to connect
Ground in the standalone VCO example.
Electrical note
Do not tie it to an output while also grounding it.
PIN 4 · Oscillator and comparator outputs
Oscillator outputVCO OUT
Function
CMOS square-wave output from the voltage-controlled oscillator.
How to connect
Connect to a high-impedance oscilloscope or counter.
Electrical note
Use a buffer for substantial loads; this is not a power output.
PIN 5 · Oscillator control
Active-HIGH VCO inhibitINHIBIT
Function
LOW enables the oscillator. HIGH stops the VCO and associated source follower.
How to connect
Tie to GND for continuous oscillation.
PIN 6 · Timing and analog signals
Timing capacitor contactC1 A
Function
First terminal of the external VCO timing capacitor.
How to connect
Connect a 10 nF non-polar capacitor between pins 6 and 7.
Electrical note
The capacitor goes between these pins, not from either pin to ground.
PIN 7 · Timing and analog signals
Timing capacitor contactC1 B
Function
Second terminal of the external VCO timing capacitor.
How to connect
Connect to the other end of the 10 nF timing capacitor.
PIN 8 · Supply and reference
Ground referenceVSS
Function
Lower supply rail and common signal reference.
How to connect
Connect to supply return, scope ground, potentiometer return and bypass capacitor.
PIN 9 · Timing and analog signals
Oscillator control voltageVCO IN
Function
High-impedance analog input that controls VCO frequency.
How to connect
Connect to the wiper of a 10 kΩ potentiometer across 5 V and GND.
Electrical note
Keep inside the supply rails; avoid floating wiper connections.
PIN 10 · Timing and analog signals
Buffered control voltageDEMOD OUT
Function
Source-follower output related to VCO IN, with a substantial voltage offset.
How to connect
Leave open when unused; when used connect at least 10 kΩ load resistance to VSS.
Electrical note
It is not an exact unity-gain or rail-to-rail copy of pin 9.
PIN 11 · Timing and analog signals
Frequency-range resistorR1
Function
External R1 with C1 establishes the VCO frequency range.
How to connect
Connect 100 kΩ from pin 11 to GND.
PIN 12 · Timing and analog signals
Frequency-offset resistorR2
Function
Optional R2 to VSS adds a minimum-frequency offset.
How to connect
Leave open in the no-offset example.
Electrical note
Open means no R2; do not replace it with a short to ground.
PIN 13 · Oscillator and comparator outputs
Edge-controlled comparator outputPC II OUT
Function
Sources, sinks or enters high impedance according to the relative rising edges of the two inputs.
How to connect
Leave open in the VCO circuit; connect through a designed loop filter in a PLL.
PIN 14 · Phase-comparator inputs
Reference signal inputSIGNAL IN
Function
Common signal input for both phase comparators, with a self-biasing input stage for suitable AC coupling.
How to connect
Ground in the standalone VCO circuit.
Electrical note
A DC-coupled 5 V signal must meet the stated CMOS input thresholds.
PIN 15 · Supply and reference
Optional shunt referenceZENER
Function
Contact for the internal zener diode, intended for a properly current-limited supply arrangement.
How to connect
Leave open with the regulated 5 V supply in this example.
Electrical note
Do not connect directly across an unrestricted supply.
PIN 16 · Supply and reference
Positive supplyVDD
Function
Supplies the oscillator and phase-comparator sections.
How to connect
Use regulated 5 V; place 100 nF directly between pins 16 and 8.
At a glance
CMOS phase-locked loop with VCO
The VCO works independently, or becomes part of a PLL with the chosen comparator and an external loop filter.
5–18 V · recommendedPLL supply
2 XOR and edge-controlledPhase comparators
−55–125 °C · selected partsOperating range
R + C External componentsVCO timing
Operating profile
CD4046BE
Operating conditions
Key parameters and their test conditions
- PLL operation
- 5–18 VConditions / notes: Recommended range
- Standalone fixed oscillator / comparators
- 3–18 VConditions / notes: Separate manufacturer operating entries
- Ambient temperature
- −55 to +125°CConditions / notes: Selected PDIP and TSSOP orderables
- 5 V logic LOW / HIGH
- ≤1.5 V / ≥3.5 VConditions / notes: DC-coupled comparator inputs
- Timing resistors
- 5 kΩ to 1 MΩConditions / notes: Manufacturer design guidance
- Timing capacitor at ≥5 V
- At least 100 pFConditions / notes: At ≥10 V guidance permits 50 pF
Package details
Follows the selected physical package
- Manufacturer
- Texas Instruments
- Part number
- CD4046BE
- Package
- PDIP-16
- Connections
- 16 pins
- Mounting
- Through-hole
- Lead pitch
- 2.54 mm
- Package code
- dip
- Thermal reference
- Board and package dependent; see manufacturer data
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Oscillator and comparator outputs4 pins
Phase-comparator inputs2 pins
Oscillator control1 pins
Timing and analog signals6 pins
Supply and reference3 pins
Oscillator and comparator outputs4 pins
Phase-comparator inputs2 pins
Oscillator control1 pins
Timing and analog signals6 pins
Supply and reference3 pins
Set the timing range
C1 connects between pins 6 and 7. R1 connects pin 11 to VSS; an optional R2 at pin 12 sets the lower-frequency offset.
Control the oscillator
With INHIBIT LOW, changing VCO IN changes the square-wave frequency. Observe pin 4 with a high-impedance scope.
Close a PLL when required
Feed pin 4 back to COMP IN, apply the reference to SIGNAL IN, and return the selected comparator output through a designed low-pass filter to VCO IN.
The example demonstrates VCO control, not a closed PLL. A useful PLL also needs a reviewed loop filter, input levels and tuning range.
Pin reference
Select a pin to explore its function and connection.
16 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| PHASE PULSES | Phase-comparator-II indicator | Phase-pulse output associated with comparator II; HIGH when the two rising edges coincide in lock. | |
| PC I OUT | Exclusive-OR comparator output | Logic XOR of the conditioned signal and comparator inputs. Its average depends on phase and duty cycle. | |
| COMP IN | Feedback comparator input | Receives VCO output directly or through a divider in a PLL. | |
| VCO OUT | Oscillator output | CMOS square-wave output from the voltage-controlled oscillator. | |
| INHIBIT | Active-HIGH VCO inhibit | LOW enables the oscillator. HIGH stops the VCO and associated source follower. | |
| C1 A | Timing capacitor contact | First terminal of the external VCO timing capacitor. | |
| C1 B | Timing capacitor contact | Second terminal of the external VCO timing capacitor. | |
| VSS | Ground reference | Lower supply rail and common signal reference. | |
| VCO IN | Oscillator control voltage | High-impedance analog input that controls VCO frequency. | |
| DEMOD OUT | Buffered control voltage | Source-follower output related to VCO IN, with a substantial voltage offset. | |
| R1 | Frequency-range resistor | External R1 with C1 establishes the VCO frequency range. | |
| R2 | Frequency-offset resistor | Optional R2 to VSS adds a minimum-frequency offset. | |
| PC II OUT | Edge-controlled comparator output | Sources, sinks or enters high impedance according to the relative rising edges of the two inputs. | |
| SIGNAL IN | Reference signal input | Common signal input for both phase comparators, with a self-biasing input stage for suitable AC coupling. | |
| ZENER | Optional shunt reference | Contact for the internal zener diode, intended for a properly current-limited supply arrangement. | |
| VDD | Positive supply | Supplies the oscillator and phase-comparator sections. |
No pins match. Try a signal name or choose All pins.
Operating conditions
Use the correct supply for the intended mode
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| PLL operation | 5–18 V | Recommended range |
| Standalone fixed oscillator / comparators | 3–18 V | Separate manufacturer operating entries |
| Ambient temperature | −55 to +125°C | Selected PDIP and TSSOP orderables |
| 5 V logic LOW / HIGH | ≤1.5 V / ≥3.5 V | DC-coupled comparator inputs |
| Timing resistors | 5 kΩ to 1 MΩ | Manufacturer design guidance |
| Timing capacitor at ≥5 V | At least 100 pF | At ≥10 V guidance permits 50 pF |
No specifications match. Try a parameter name or a unit.
Nominal operating conditions are distinct from absolute maximum stress limits.
Choosing a phase comparator
The two outputs are not interchangeable
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Comparator I | XOR output at pin 2 | Duty-cycle dependent; use 50% input duty for maximum lock range |
| Comparator I at center frequency | About 90° phase difference | Nominal locked condition |
| Comparator II | Edge-controlled output at pin 13 | Uses positive transitions; source / sink / high-Z |
| Comparator II in lock | Nominal zero phase difference | Ideal aligned edges; filter retains control voltage |
| Harmonic lock | Possible with comparator I | Comparator II avoids the stated harmonic-center lock behavior |
| No reference input | I tends toward center; II toward minimum | As described for the respective complete loops |
No specifications match. Try a parameter name or a unit.
Actual acquisition, ripple and stability depend on the external filter and signal conditions.
Essential connection groups
Complete sixteen-pin device
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Power | VDD16 / VSS8 | Local 100 nF bypass |
| VCO | OUT4 / IN9 / INHIBIT5 | Control and oscillator output |
| Timing | C1 across 6–7; R1 at11; R2 at12 | Resistors return to VSS |
| Reference / feedback | SIGNAL IN14 / COMP IN3 | Shared by both comparators |
| Comparator outputs | PC I2 / PC II13 / phase pulses1 | Select the correct feedback path |
| Auxiliary | DEMOD10 / ZENER15 | Leave open when unused |
No specifications match. Try a parameter name or a unit.
Package switching retains these signal assignments.
Oscillator characteristics
Typical performance requires its stated setup
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Output duty cycle | 50% typical | Specified at 5, 10 and 15 V |
| Typical maximum frequency | 1.4 MHz | 10 V, R1 5 kΩ, C1 50 pF, R2 open, VCO IN=VDD |
| Power example | 70 µW typical | 5 V, 10 kHz, R1 1 MΩ, R2 open, VCO IN=VDD/2 |
| Range adjustment | R1 and C1 | Use manufacturer curves; calibrate the built circuit |
| Frequency offset | R2 to VSS | Omit R2 for the no-offset configuration |
| Inhibit | LOW enables; HIGH disables | Also switches off the associated source follower |
No specifications match. Try a parameter name or a unit.
The 1.4 MHz point is not a guaranteed frequency for the 5 V example.
Potentiometer-controlled VCO
A clear starting circuit, not a closed PLL
Manufacturer specifications 9 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply | 5 V; 100 nF bypass | VDD16 to VSS8 |
| Control | 10 kΩ potentiometer across rails | Wiper to VCO IN9; start near 2.5 V |
| Timing capacitor | 10 nF non-polar | Between pins 6 and 7 |
| Range resistor | 100 kΩ | Pin 11 to GND |
| Offset resistor | Not fitted | Pin 12 remains open |
| Enable | Pin 5 to GND | VCO runs |
| Unused comparator inputs | Pins 3 and 14 to GND | Defined inputs |
| Unused outputs / reference | Pins 1, 2, 10, 13 and 15 open | Do not ground output pins |
| Measurement | Pin 4 to high-impedance scope | Scope ground to VSS |
No specifications match. Try a parameter name or a unit.
Sweep slowly, observe the measured frequency and avoid loading timing nodes.
Readings and interpretation
Illustrative setup values
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Potentiometer midpoint | About 2.5 V | 5 V supply; unloaded ideal midpoint |
| Potentiometer current | 5 V / 10 kΩ = 0.5 mA | External control network only |
| Increasing control voltage | Frequency increases over the useful tuning range | Endpoint behavior and exact slope are device-dependent |
| Period measurement | f = 1 / T | Measure consecutive equivalent edges on pin 4 |
| Example measured period | 1 ms means 1 kHz | Unit conversion only, not a prediction for the shown RC |
| PLL lock | Not applicable to this standalone circuit | No comparator feedback filter is connected |
No specifications match. Try a parameter name or a unit.
Calculated setup quantities are not live simulation results.
Package and stress reference
CD4046BE · PDIP-16
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| PDIP | CD4046BE · 16 pins | 2.54 mm lead pitch |
| TSSOP | CD4046BPWR · 16 pins | 0.65 mm pitch; TI PW0016A |
| SOP alternative | CD4046BNSR | Different body and land pattern; not the selected TSSOP |
| Supply stress limit | 20 V absolute maximum | Recommended operation remains at or below 18 V |
| Input voltage stress | VSS−0.5 to VDD+0.5 V | Not a valid operating signal range |
| Input current stress | ±10 mA absolute maximum | Do not design for continuous clamp injection |
| Storage temperature | −65 to +150°C | Unpowered |
No specifications match. Try a parameter name or a unit.
Use the selected package drawing and review fabrication tolerances before making a PCB.
Frequency tracking
Use a designed PLL to track a compatible periodic signal.
Manufacturer application guideFrequency synthesis
Add a feedback divider and a properly compensated loop.
Manufacturer application guideFM and FSK experiments
Explore modulation and demodulation with specified deviation and filtering.
Manufacturer application guideTake it into ProTech
Find CD4046B in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech