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CD4051BEight-channel bidirectional analog multiplexer

Route one of eight analog signals to a shared connection.

Manufacturer-referenced

Texas Instruments · CD4051BE

PDIP-16SCHS047O · May 2026

CD4051B connects one of eight analog channels to a common terminal. Three digital inputs select the channel, and a separate inhibit input opens all paths. Signals can travel in either direction through the selected switch; the IC does not amplify or regenerate them. The analog range is set by VEE and VDD, while select and inhibit controls are referenced to VSS and VDD. In the 5 V single-supply circuit, VEE and VSS are both grounded, so all analog signals stay between 0 V and 5 V. Negative signals require a suitable negative VEE rail and a compatible complete circuit. The example routes either a 1 V or 4 V low-impedance source into a high-impedance ADC. Switch resistance, source impedance and sampling capacitance determine settling and error. Firmware selects the channel, waits for acquisition to settle and only then records a conversion.

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Real View

CD4051BE black package with silver leads and readable markings.
CD4051BE · PDIP-16Package illustration

Pinout

CD4051BEPDIP-16Top view
Select a pin to see its functionPDIP-16 · 16 pins

PCB Footprint

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Finding PDIP-16 packageTop view · mm
Bidirectional signal pathsSelect & inhibitAnalog rails & logic ground
CD4051BEPDIP-16Top view

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1
PIN 1 · Bidirectional signal paths

CH4

Bidirectional analog

Function

Channel 4 connects to COM when INH is LOW and CBA selects 4.

How to connect

Tie unused channels to GND in this example.

Electrical note

Keep the signal within VEE–VDD. The enabled channel has finite, signal-dependent resistance.

At a glance

Eight-channel bidirectional analog multiplexer

A decoder controls eight transmission gates. One channel reaches COM when enabled; a HIGH inhibit signal disconnects all eight.

8 One common terminalSignal channels
5 V · VEE and VSS groundedExample supply
−55–125 °CSelected variants
470 Ω at 5 V / 25°CTypical ON resistance

Operating profile

CD4051BE

Selected package
PDIP-16CD4051BE
Signal direction
BidirectionalNo gain or output buffer
INH = HIGH
All paths openCOM can float

Channel-selection map

Key parameters and their test conditions

CBA = 000
CH0 · pin 13Conditions / notes: Connected bidirectionally to COM pin 3
CBA = 001
CH1 · pin 14Conditions / notes: Connected bidirectionally to COM pin 3
CBA = 010
CH2 · pin 15Conditions / notes: Connected bidirectionally to COM pin 3
CBA = 011
CH3 · pin 12Conditions / notes: Connected bidirectionally to COM pin 3
CBA = 100
CH4 · pin 1Conditions / notes: Connected bidirectionally to COM pin 3
CBA = 101
CH5 · pin 5Conditions / notes: Connected bidirectionally to COM pin 3

Package details

Follows the selected physical package

Manufacturer
Texas Instruments
Part number
CD4051BE
Package
PDIP-16
Connections
16 pins
Mounting
Through-hole
Lead pitch
2.54 mm
Package code
dip
Thermal reference
Board and package dependent; see manufacturer data

Connections by function

Select a pin to open its function, electrical notes and wiring guidance.

Bidirectional signal paths9 pins

Select & inhibit4 pins

Analog rails & logic ground3 pins

Values apply to the stated grade and conditions. Absolute maximum ratings are stress limits.SCHS047O · May 2026

Keep signals inside the rails

Use VEE and VDD as the analog boundaries; all example signals remain within 0–5 V.

Select the channel

Hold INH LOW and present CBA. A is weight 1, B weight 2 and C weight 4.

Wait and sample

Allow the selected source to settle at the ADC before taking a reading. A disabled common pin is not a defined zero.

An analog multiplexer is a switch, not an ADC or an amplifier. Check rail limits and control thresholds, then budget acquisition time for the switch and source resistance.

Compact CD4051B cutaway with CBA address decoder, inhibit logic, eight analog switches and common signal bus.
Functional architecture; the signal path is bidirectional and unbuffered.
Real-looking CD4051BE package with two bounded voltage sources, 5V ADC controller, bypass and explicitly grounded unused channels.
A LOW selects 1 V; A HIGH selects 4 V. The ADC and select GPIO use compatible 5 V levels.

Pin reference

Select a pin to explore its function and connection.

16 pins
PinSignalTypeFunction
CH4Bidirectional analogChannel 4 connects to COM when INH is LOW and CBA selects 4.
CH6Bidirectional analogChannel 6 connects to COM when INH is LOW and CBA selects 6.
COMBidirectional commonShared terminal of the selected analog channel; may be used as input or output.
CH7Bidirectional analogChannel 7 connects to COM when INH is LOW and CBA selects 7.
CH5Bidirectional analogChannel 5 connects to COM when INH is LOW and CBA selects 5.
INHActive-HIGH inhibitHIGH opens every signal path, regardless of address.
VEEAnalog lower railLowest allowed analog signal level.
VSSLogic groundDigital control reference and supply return.
CDigital select inputBinary channel-selection weight 4; A is the least significant bit.
BDigital select inputBinary channel-selection weight 2; A is the least significant bit.
ADigital select inputBinary channel-selection weight 1; A is the least significant bit.
CH3Bidirectional analogChannel 3 connects to COM when INH is LOW and CBA selects 3.
CH0Bidirectional analogChannel 0 connects to COM when INH is LOW and CBA selects 0.
CH1Bidirectional analogChannel 1 connects to COM when INH is LOW and CBA selects 1.
CH2Bidirectional analogChannel 2 connects to COM when INH is LOW and CBA selects 2.
VDDPositive supplyUpper analog rail and positive logic supply.
PDIP-16 · Top view · Select a pin number to inspect its connection.

Channel-selection map

INH LOW enables selection

ParameterValueConditions / notes
CBA = 000CH0 · pin 13Connected bidirectionally to COM pin 3
CBA = 001CH1 · pin 14Connected bidirectionally to COM pin 3
CBA = 010CH2 · pin 15Connected bidirectionally to COM pin 3
CBA = 011CH3 · pin 12Connected bidirectionally to COM pin 3
CBA = 100CH4 · pin 1Connected bidirectionally to COM pin 3
CBA = 101CH5 · pin 5Connected bidirectionally to COM pin 3
CBA = 110CH6 · pin 2Connected bidirectionally to COM pin 3
CBA = 111CH7 · pin 4Connected bidirectionally to COM pin 3

INH HIGH opens all paths, independent of CBA.

Rails and control levels

5 V single-supply example

ParameterValueConditions / notes
VDD / VSS / VEE+5 V / 0 V / 0 VPins 16 / 8 / 7
Analog terminal rangeVEE to VDD0–5 V in this example
Control HIGH3.5 V minimum at VDD 5 VSelect and inhibit inputs
Control LOW0.8 V maximumCurrent SCHS047O specification
3.3 V controller at 5 V supplyHIGH is not guaranteedUse suitable level translation
Negative analog signalsRequire an appropriate negative VEEDo not apply below ground with VEE grounded

Digital and analog voltage domains are related but have different lower references.

Switch resistance

TA 25°C; VEE = VSS = 0 V

ParameterValueConditions / notes
At VDD 5 V470 Ω typical; 1050 Ω maximumAcross the specified signal range
At VDD 10 V180 Ω typical; 400 Ω maximumSpecified test conditions
At VDD 15 V125 Ω typical; 240 Ω maximumSpecified test conditions
At 5 V / +125°C1300 Ω maximumTemperature changes resistance
Channel-to-channel difference15 Ω typical at 5 VNot the absolute channel resistance
Load interactionCreates a divider with the loadKeep source and load conditions explicit

The typical 125 Ω headline belongs to 15 V operation; it is not a 5 V value.

Propagation and acquisition

Timing is not the same as ADC settling

ParameterValueConditions / notes
Signal path at 5 V30 ns typical; 60 ns maximumRL 200 kΩ, CL 50 pF, TA 25°C
Address-to-output at 5 V450 ns typical; 720 ns maximumRL 10 kΩ, CL 50 pF, 20 ns edges
Inhibit-to-ON at 5 V400 ns typical; 720 ns maximumRL 1 kΩ, CL 50 pF, 20 ns edges
Inhibit-to-OFF at 5 V200 ns typical; 450 ns maximumRL 10 kΩ, CL 50 pF, 20 ns edges
ADC acquisitionDepends on source, switch and sampling capacitorUse the ADC manufacturer timing requirements
Simple RC estimateτ = (Rsource + RON) × COnly a first-order model

Propagation specifications do not promise a precision ADC result immediately after selection.

Two-source ADC wiring

Same 5 V logic and analog domain

ParameterValueConditions / notes
PowerVDD16 +5 V; VSS8 and VEE7 GND100 nF local bypass
CH0 pin131 V low-impedance sourceSelect with A LOW
CH1 pin144 V low-impedance sourceSelect with A HIGH
COM pin3High-impedance ADC inputWait for acquisition settling
SelectB10 and C9 groundedA11 driven by a 0/5 V GPIO
EnableINH6 groundedOptional GPIO can inhibit between readings
Unused channelsPins 15, 12, 1, 5, 2 and 4 groundedNo unused digital input is left floating

Named source labels refer to the same nets throughout the illustration.

Expected readings and loading

Illustrative calculation; not live measurement

ParameterValueConditions / notes
A = 0, B = C = 0Approximately 1 V at COMHigh-impedance load after settling
A = 1, B = C = 0Approximately 4 V at COMHigh-impedance load after settling
INH = 1No defined COM voltageLeakage and stored charge remain
4 V into a 10 kΩ load4 × 10000 / (10000 + 470) = 3.82 VAssumes zero source resistance and 470 Ω RON
Loading error in that estimateAbout −4.49%Actual RON changes with voltage and temperature
High-impedance samplingReduces static loadingAcquisition capacitance still needs charging time

Do not confuse the ideal selected-source value with a guaranteed loaded output voltage.

Package and practical limits

CD4051BE · PDIP-16

ParameterValueConditions / notes
Through-holeCD4051BE · PDIP-162.54 mm pin pitch
Surface-mountCD4051BM96 · SOIC-161.27 mm pitch; 3.9 mm body
Operating temperature−55 to +125°CSelected orderables
Storage temperature−65 to +150°CUnpowered
Rail sequencingPrevent signals driving an unpowered deviceConsider source current and clamp paths
Unused control inputsTie to a valid logic levelDo not rely on floating CMOS inputs

This reference follows the current TI revision and a conservative 5 V example; consult the full datasheet for other supply arrangements.

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