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LM13700Dual operational transconductance amplifier

Control an analog gain with a small bias current.

Manufacturer-referenced

Texas Instruments · LM13700N

PDIP-16SNOSBW2F · November 2015

LM13700 contains two operational transconductance amplifiers, or OTAs. Each turns a small differential input voltage into an output current, with its conversion factor set by an external amplifier-bias current. An external load converts that current into a voltage. Input-linearizing diodes support wider signal ranges when correctly biased, and separate Darlington buffers can drive a following stage. These buffers need external connections and bias loads. This reference uses a ±15 V, low-amplitude bench circuit to make the gain-control principle visible. SOIC-16 is listed in the current ordering appendix; PDIP-16 is retained as the documented legacy LM13700N package. Both share the same 16-pin function map.

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LM13700N black PDIP-16 package with silver contacts and readable marking.
LM13700N · PDIP-16Package illustration

Pinout

LM13700NPDIP-16Top view
Select a pin to see its functionPDIP-16 · 16 pins

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16Physical pins LM13700NPDIP-16 Manufacturer-referencedTexas Instruments

Pin diagram

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Package map
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LM13700NPDIP-16Top view

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1
PIN 1 · Gain-control current

IABC A

Channel A bias current

Function

Sets channel A transconductance through an externally supplied current.

How to connect

For the example, connect a 150 kΩ resistor from circuit GND to this pin.

Electrical note

The pin sits approximately two diode drops above V−; do not drive it directly from a voltage source. Absolute maximum is 2 mA.

Key specifications

The OTA controls output current. A load resistor supplies the current-to-voltage conversion; the optional buffer is a separate stage.

Independent OTAs2 plus two separate buffers
Recommended total rail span9.5–32 V
Typical transconductance9.6 mS at IABC = 500 µA
Operating grade0–70 °C

Operating profile

Supply, signals and operating conditions

LM13700 operating profile
ParameterValueConditions / notes
Selected packagePDIP-16LM13700N
Example differential signal±2mV peak
Example gain≈17.4V/V · typical calculation
Use these values with the stated grade and test conditions.

Package details

LM13700N · PDIP-16

Selected package
Selected LM13700 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberLM13700N
PackagePDIP-16
Connections16 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codePDIP-16
Thermal referenceSee operating and package limits

Supplies and limits

Recommended conditions and absolute ratings

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ParameterValueConditions / notes
Recommended total supply9.5–32 VSingle-supply configuration
Recommended split supplies±4.75 to ±16 VSymmetric dual-supply configuration
Example supply+15 V / GND / −15 V30 V total rail span
Operating temperature0 to +70°CCommercial grade
Absolute supply limit36 V total / ±18 VStress limit, not the operating target
Absolute IABC / diode current2 mA eachExternal current limiting is required
Absolute buffer output current20 mAAlso constrained by package dissipation

Circuit GND is the midpoint of the split supply; it is not the V− pin.

OTA characteristics

±15 V, 25°C, IABC = 500 µA unless noted

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ParameterValueConditions / notes
Forward transconductance6.7–13 mS; 9.6 mS typical5.4 mS minimum over specified temperature
Channel gm tracking0.3 dB typicalManufacturer reference conditions
Input offset0.4 mV typical; 4 mV maximumManufacturer specified-temperature condition
Input bias current0.4 µA typical; 5 µA maximum1 µA typical / 8 µA maximum over temperature
Input resistance26 kΩ typical; 10 kΩ minimumReference test conditions
Common-mode input range±12 V minimum; ±13.5 V typicalWith ±15 V rails
Peak output current500 µA typical; 350–650 µAIABC = 500 µA, RL = 0
Supply current2.6 mA typicalBoth channels, IABC = 500 µA

Typical transconductance and example gain are not guaranteed exact values.

Signal behavior

OTA and buffer are different stages

Scroll sideways to see all columns.

ParameterValueConditions / notes
Small-signal equationIOUT ≈ gm × (VIN+ − VIN−)Without the linearizing diodes, use a few millivolts differential
Typical gm at 25°CApproximately 19.2 × IABCIABC in amperes gives gm in siemens
Current-to-voltage conversionVOUT ≈ IOUT × RLValid while output swing and current remain in range
Open-loop bandwidth2 MHz typicalNot a guaranteed closed-loop bandwidth for every circuit
Slew rate50 V/µs typicalUnity-gain compensated test
Separate buffersDarlington emitter followersInput must be connected externally; output has a level shift
Buffer loadBias toward V− when usedManufacturer buffer test uses 5 kΩ to V−

The LM13700 is not a pin-compatible replacement for a conventional dual voltage op amp.

Small-signal gain experiment

One OTA with an unbuffered resistive output

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ParameterValueConditions / notes
V+11 / V−6+15 V / −15 V100 nF bypass from each rail to GND
IABC A1150 kΩ to GNDApproximately 90.7 µA at the assumed bias voltage
IN+ A3 / IN− A4±2 mV sine / GND1 kHz, zero DC offset
OUT A510 kΩ to GND plus high-impedance scopeScope input capacitance affects high-frequency response
DIODE A2 and B15OpenLinearizing diodes unused in this experiment
BUF IN A7 and B10GNDBUF OUT A8 and B9 left open
Unused channel BIN−13 and IN+14 to GNDIABC B16 and OUT B12 open
All source returnsCircuit GNDThe split-supply midpoint, not −15 V

This is an explanatory circuit, not a running simulation. Offset and bias currents may add a DC output offset.

Gain calculation

Nominal 25°C example

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ParameterValueConditions / notes
Bias pin estimateV− + 2 VBE ≈ −13.6 VAssume VBE ≈ 0.7 V
Bias current13.6 V / 150 kΩ ≈ 90.7 µAResistor goes from GND to IABC A1
Transconductance19.2 × 90.7 µA ≈ 1.74 mSTypical small-signal approximation
Voltage gain1.74 mS × 10 kΩ ≈ 17.4 V/VAbout 24.8 dB
Signal output2 mV peak × 17.4 ≈ 34.8 mV peakExcludes DC offset and tolerances
Use 300 kΩ insteadApproximately 8.7 V/VLower bias reduces gain
Use 100 kΩ insteadApproximately 26.1 V/VHigher bias increases gain

Changing temperature, resistor tolerance, junction voltage or the actual gm changes these results.

Using the linearizing diodes

Advanced input conditioning

Scroll sideways to see all columns.

ParameterValueConditions / notes
PurposeReduce transfer nonlinearityThe diodes must be biased with current
Diode current requirementID greater than twice input signal currentUse the manufacturer circuit and input attenuation
Manufacturer VCA exampleAbout 1 mA diode bias13 kΩ from +15 V, approximate 0.7 V diode node
Input amplitudeAttenuate before the OTAA large differential voltage clips or distorts without suitable conditioning
Control-voltage conversionResistor feeds IABC from a control voltageInclude the V− + 2 VBE bias-pin offset
Buffer wiringOUT5 to BUF IN7 only when intendedThis connection is external, not inside the IC

The simple illustrated circuit deliberately leaves the diodes and buffers unused to isolate the gm principle.

Packages and ordering

LM13700N · PDIP-16

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ParameterValueConditions / notes
SOIC-16LM13700M/NOPB; LM13700MX/NOPBListed in TI ordering appendix dated 10 November 2025
PDIP-16LM13700NHistorical package documented in the datasheet; not listed in that current appendix
Pin mapSame 16 physical functionsTop view, pin 1 at the notch end
Body / pitchPDIP: 19.304 × 6.35 mm / 2.54 mmSOIC: 9.90 × 3.91 mm / 1.27 mm
Footprint provenanceOriginal TEP editable land patternsVerify the exact mechanical drawing and assembly process

Legacy package visualization is not a claim of current availability.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Gain-control current2 pins

Linearizing diodes2 pins

Differential input4 pins

OTA current output2 pins

Supply2 pins

Independent buffers4 pins

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

LM13700 at a glance

Follow the labeled connections and functional stages

LM13700 working principle: illustrated functional stages, basic circuit and connections
Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Establish a bias current

A 150 kΩ resistor from GND to IABC A1 supplies roughly 90.7 µA with ±15 V rails and the typical two-junction bias voltage.

Step 2 / 3

Apply a small difference

The example uses ±2 mV at IN+ A3 while IN− A4 is grounded. The input-linearizing diodes are open.

Step 3 / 3

Turn current into voltage

OUT A5 drives a 10 kΩ load to GND. The nominal output signal is about ±34.8 mV, before offset and device tolerances.

LM13700 in a circuit

A millivolt input and a resistive load reveal the OTA principle.

LM13700 physical IC on split fifteen-volt rails, 150 kilohm bias resistor, two-millivolt input and ten-kilohm output load.
Matching node labels connect. Calculated signal amplitudes exclude DC offset and tolerances.

Connect it, step by step

Follow the component values and pin connections

Connect both rails

Connect +15 V to pin 11 and −15 V to pin 6, with local bypass to the supply midpoint.

Set and limit bias

Feed IABC A1 through 150 kΩ from GND; never short this pin directly to GND.

Compare signal amplitudes

Observe the AC output across 10 kΩ. Changing the bias resistor changes the nominal gain.

Inside LM13700

Two current-output amplifiers and two separate buffers.

Compact dual OTA cutaway showing differential inputs, linearizing diodes, bias control and independent Darlington buffers.
Functional architecture, not a transistor-level die schematic. The OTA outputs are not internally joined to the buffer inputs.

Explore the circuit

Select a stage to see its role and connections

Set gm independently

IABC A1 and IABC B16 control the two channels separately.

Linearize when needed

DIODE A2 and DIODE B15 bias input-linearizing diodes for appropriately conditioned signals.

Choose the output stage

Use the OTA current output directly, or externally connect and bias its separate buffer.

Selected packagePDIP-16LM13700N
Physical connections16 pinsPackage-specific numbering
Reference collection8 tables48 parameters & pin functions

Pin reference

Signal names, electrical functions and connection guidance

PDIP-16
Physical pin numbers16 pins

Scroll within the table to see all columns and rows.

LM13700 pin functions and connections
PinSignalTypeFunction & connection
IABC AChannel A bias currentSets channel A transconductance through an externally supplied current.
Connection guidance

For the example, connect a 150 kΩ resistor from circuit GND to this pin.

The pin sits approximately two diode drops above V−; do not drive it directly from a voltage source. Absolute maximum is 2 mA.

DIODE AChannel A diode biasFeeds the two input-linearizing diodes.
Connection guidance

Leave open in the small-signal example. Use a properly limited bias current when enabling the diodes.

The diode current and input attenuation must be designed together; 2 mA is an absolute maximum.

IN+ AChannel A noninverting inputA positive differential input produces positive output current.
Connection guidance

Apply a 1 kHz sine wave, ±2 mV peak, centered on circuit GND.

IN− AChannel A inverting inputThe OTA responds to IN+ minus IN−.
Connection guidance

Connect to circuit GND in this example.

Keep the differential signal small when the linearizing diodes are unused.

OUT AChannel A current outputHigh-impedance output supplies a current proportional to differential voltage.
Connection guidance

Connect a 10 kΩ load to GND and a high-impedance scope.

This is a current output, not an ordinary low-impedance voltage-amplifier output.

V−Negative supplyNegative supply for both OTAs and buffers.
Connection guidance

Connect to −15 V and bypass to circuit GND with 100 nF.

BUF IN AChannel A buffer inputIndependent input to the Darlington output buffer.
Connection guidance

Ground in this unbuffered example.

It is not internally connected to OUT A pin 5.

BUF OUT AChannel A buffer outputEmitter-follower output with a two-junction level shift.
Connection guidance

Leave open in this example. When used, provide a bias load toward V−.

Output current and package dissipation must stay within limits; the buffer is not rail-to-rail.

BUF OUT BChannel B buffer outputIndependent Darlington follower output.
Connection guidance

Leave open in this example.

BUF IN BChannel B buffer inputIndependent input to the second buffer.
Connection guidance

Connect to circuit GND in this example.

It is not internally connected to OUT B pin 12.

V+Positive supplyPositive supply shared by both channels.
Connection guidance

Connect to +15 V and bypass to circuit GND with 100 nF.

OUT BChannel B current outputSecond high-impedance OTA output.
Connection guidance

Leave open in this channel-A example.

IN− BChannel B inverting inputNegative differential input of the second OTA.
Connection guidance

Connect to circuit GND when channel B is unused here.

IN+ BChannel B noninverting inputPositive differential input of the second OTA.
Connection guidance

Connect to circuit GND when channel B is unused here.

DIODE BChannel B diode biasBias connection for channel B linearizing diodes.
Connection guidance

Leave open in this example.

IABC BChannel B bias currentSets the second channel transconductance independently.
Connection guidance

Leave open so IABC B is zero in this example.

An unused bias pin does not require a direct connection to GND.

PDIP-16 · Top view · Select a pin number to open its interactive pinout.

Supplies and limits

Recommended conditions and absolute ratings

Manufacturer-referenced values7 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Recommended total supply9.5–32 VSingle-supply configuration
Recommended split supplies±4.75 to ±16 VSymmetric dual-supply configuration
Example supply+15 V / GND / −15 V30 V total rail span
Operating temperature0 to +70°CCommercial grade
Absolute supply limit36 V total / ±18 VStress limit, not the operating target
Absolute IABC / diode current2 mA eachExternal current limiting is required
Absolute buffer output current20 mAAlso constrained by package dissipation

Circuit GND is the midpoint of the split supply; it is not the V− pin.

OTA characteristics

±15 V, 25°C, IABC = 500 µA unless noted

Manufacturer-referenced values8 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Forward transconductance6.7–13 mS; 9.6 mS typical5.4 mS minimum over specified temperature
Channel gm tracking0.3 dB typicalManufacturer reference conditions
Input offset0.4 mV typical; 4 mV maximumManufacturer specified-temperature condition
Input bias current0.4 µA typical; 5 µA maximum1 µA typical / 8 µA maximum over temperature
Input resistance26 kΩ typical; 10 kΩ minimumReference test conditions
Common-mode input range±12 V minimum; ±13.5 V typicalWith ±15 V rails
Peak output current500 µA typical; 350–650 µAIABC = 500 µA, RL = 0
Supply current2.6 mA typicalBoth channels, IABC = 500 µA

Typical transconductance and example gain are not guaranteed exact values.

Signal behavior

OTA and buffer are different stages

Manufacturer-referenced values7 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Small-signal equationIOUT ≈ gm × (VIN+ − VIN−)Without the linearizing diodes, use a few millivolts differential
Typical gm at 25°CApproximately 19.2 × IABCIABC in amperes gives gm in siemens
Current-to-voltage conversionVOUT ≈ IOUT × RLValid while output swing and current remain in range
Open-loop bandwidth2 MHz typicalNot a guaranteed closed-loop bandwidth for every circuit
Slew rate50 V/µs typicalUnity-gain compensated test
Separate buffersDarlington emitter followersInput must be connected externally; output has a level shift
Buffer loadBias toward V− when usedManufacturer buffer test uses 5 kΩ to V−

The LM13700 is not a pin-compatible replacement for a conventional dual voltage op amp.

Small-signal gain experiment

One OTA with an unbuffered resistive output

Manufacturer-referenced values8 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
V+11 / V−6+15 V / −15 V100 nF bypass from each rail to GND
IABC A1150 kΩ to GNDApproximately 90.7 µA at the assumed bias voltage
IN+ A3 / IN− A4±2 mV sine / GND1 kHz, zero DC offset
OUT A510 kΩ to GND plus high-impedance scopeScope input capacitance affects high-frequency response
DIODE A2 and B15OpenLinearizing diodes unused in this experiment
BUF IN A7 and B10GNDBUF OUT A8 and B9 left open
Unused channel BIN−13 and IN+14 to GNDIABC B16 and OUT B12 open
All source returnsCircuit GNDThe split-supply midpoint, not −15 V

This is an explanatory circuit, not a running simulation. Offset and bias currents may add a DC output offset.

Gain calculation

Nominal 25°C example

Manufacturer-referenced values7 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Bias pin estimateV− + 2 VBE ≈ −13.6 VAssume VBE ≈ 0.7 V
Bias current13.6 V / 150 kΩ ≈ 90.7 µAResistor goes from GND to IABC A1
Transconductance19.2 × 90.7 µA ≈ 1.74 mSTypical small-signal approximation
Voltage gain1.74 mS × 10 kΩ ≈ 17.4 V/VAbout 24.8 dB
Signal output2 mV peak × 17.4 ≈ 34.8 mV peakExcludes DC offset and tolerances
Use 300 kΩ insteadApproximately 8.7 V/VLower bias reduces gain
Use 100 kΩ insteadApproximately 26.1 V/VHigher bias increases gain

Changing temperature, resistor tolerance, junction voltage or the actual gm changes these results.

Using the linearizing diodes

Advanced input conditioning

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
PurposeReduce transfer nonlinearityThe diodes must be biased with current
Diode current requirementID greater than twice input signal currentUse the manufacturer circuit and input attenuation
Manufacturer VCA exampleAbout 1 mA diode bias13 kΩ from +15 V, approximate 0.7 V diode node
Input amplitudeAttenuate before the OTAA large differential voltage clips or distorts without suitable conditioning
Control-voltage conversionResistor feeds IABC from a control voltageInclude the V− + 2 VBE bias-pin offset
Buffer wiringOUT5 to BUF IN7 only when intendedThis connection is external, not inside the IC

The simple illustrated circuit deliberately leaves the diodes and buffers unused to isolate the gm principle.

Packages and ordering

LM13700N · PDIP-16

Manufacturer-referenced values5 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
SOIC-16LM13700M/NOPB; LM13700MX/NOPBListed in TI ordering appendix dated 10 November 2025
PDIP-16LM13700NHistorical package documented in the datasheet; not listed in that current appendix
Pin mapSame 16 physical functionsTop view, pin 1 at the notch end
Body / pitchPDIP: 19.304 × 6.35 mm / 2.54 mmSOIC: 9.90 × 3.91 mm / 1.27 mm
Footprint provenanceOriginal TEP editable land patternsVerify the exact mechanical drawing and assembly process

Legacy package visualization is not a claim of current availability.

Read each value with its conditions

Typical values describe the stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Texas Instruments · SNOSBW2F · November 2015
Official PDF datasheet

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Find LM13700 in the Components Library to place its schematic symbol and connect its pins.

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