MAX4855 V half-duplex RS-485 transceiver

Carry a logic signal across a balanced two-wire bus.

Manufacturer-referenced

Analog Devices / Maxim · MAX485EPA+

PDIP-819-0122 · Rev 10 · September 2014

MAX485 connects a controller’s logic-level data to an RS-485 differential bus. One driver and one receiver share terminals A and B, so the link is half duplex: only one node should drive the pair at a time. It does not generate UART framing or implement a protocol by itself. The transceiver runs from a regulated 5 V supply and supports data rates up to 2.5 Mbit/s. DE enables transmission; the active-LOW receiver enable controls RO. Joining those controls provides one direction signal, LOW to receive and HIGH to transmit. The example shows two nodes, termination at both cable ends and one external idle-bias network. A reference conductor keeps the bus common-mode voltage within its operating range. This MAX485 reference does not inherit the shutdown or quarter-unit-load features of other parts in the manufacturer’s family datasheet.

Real View

MAX485EPA+ black package with silver leads and readable markings.

Pinout

MAX485PDIP-8Top view

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8Physical pins MAX485EPA+PDIP-8 Manufacturer-referencedAnalog Devices / Maxim

Pin diagram

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Package map

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MAX485PDIP-8Top view

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PIN 1 · Receive data

RO

Receiver data output

Function

When enabled, HIGH for A − B ≥ 200 mV and LOW for A − B ≤ −200 mV. High impedance when RE̅ is HIGH.

How to connect

Connect to a 5 V-compatible controller RX input.

Electrical note

Open receiver inputs produce HIGH; a terminated idle bus needs separately designed bias.

Key specifications

A differential driver converts DI into opposite bus voltages. A receiver compares A with B and recovers a logic level. Separate enable controls determine who is driving and listening.

Operating supply4.75–5.25 V

Maximum data rate2.5 Mbit/s

Selected E grades−40–85 °C

CommunicationHalf duplex One active driver at a time

Operating profile

Supply, signals and operating conditions

MAX485 operating profile
Parameter	Value	Conditions / notes
Selected package	PDIP-8	MAX485EPA+
Receiver loading	1 unit load	12 kΩ minimum · 32 standard loads
Joined DE / RE̅	LOW = receive	HIGH = transmit

Package details

MAX485EPA+ · PDIP-8

Selected package

Selected MAX485 physical package
Property	Details
Manufacturer	Analog Devices / Maxim
Part number	MAX485EPA+
Package	PDIP-8
Connections	8 pins
Mounting	Through-hole
Lead pitch	2.54 mm
Package code	dip
Thermal reference	Board and package dependent; see manufacturer data

Driver and receiver truth states

Controls are independent

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
DE HIGH; DI HIGH	A HIGH relative to B	Transmitter enabled
DE HIGH; DI LOW	A LOW relative to B	Transmitter enabled
DE LOW	A and B driver outputs high impedance	Receiver may remain enabled
RE̅ LOW; A − B ≥ +200 mV	RO HIGH	Within common-mode range
RE̅ LOW; A − B ≤ −200 mV	RO LOW	Within common-mode range
RE̅ HIGH	RO high impedance	External input may need a defined idle state
RE̅ LOW; both bus inputs open	RO HIGH	Specified open-input fail-safe
DE LOW; RE̅ HIGH	Driver and receiver disabled	MAX485 has no low-current shutdown mode

Do not assume a terminated, unbiased idle bus has the same fail-safe behavior as physically open receiver inputs.

Supply, logic and receiver

Selected industrial grades

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Supply voltage	4.75–5.25 V	Nominal 5 V
Ambient range	−40 to +85°C	EPA / ESA orderables
Logic input HIGH / LOW	≥ 2.0 V / ≤ 0.8 V	DI, DE and RE̅
RO HIGH / LOW	≥ 3.5 V / ≤ 0.4 V	Source / sink 4 mA
Receiver common-mode	−7 to +12 V	Referenced to local GND
Receiver threshold region	−200 to +200 mV	No guaranteed level inside the transition region
Typical input hysteresis	70 mV	Common-mode 0 V
Receiver input resistance	12 kΩ minimum	One standard unit load

A 3.3 V controller may drive the logic inputs, but its RX input must tolerate or translate the 5 V RO level.

Driver and power characteristics

Manufacturer specified test loads

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Loaded differential output	1.5 V minimum	RS-485 test load: two 27 Ω branches
No-load current, DE LOW	300 µA typical; 500 µA maximum	MAX485; defined input levels
No-load current, DE HIGH	500 µA typical; 900 µA maximum	MAX485; driver enabled and unloaded
Receiver bus loading	Up to 32 standard unit loads	Bias, cable and other loads also matter
Driver protection	Current limiting and thermal shutdown	Not permission for continuous bus contention
Slew-rate limiting	Not provided	Use controlled cable topology
Low-power shutdown	Not provided in MAX485	MAX481 / 483 / 487 have different features

The MAX487 and MAX1487 quarter-unit-load and 128-node figures do not apply to MAX485.

Data path and bus timing

5 V ±5% · manufacturer test circuits

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Maximum data rate	2.5 Mbit/s	Do not infer this rate over every cable length
Bit period at 2.5 Mbit/s	400 ns	1 / data rate
Driver propagation	10–60 ns; 30 ns typical	54 Ω differential load; 100 pF each output
Driver rise / fall	3–40 ns; 15 ns typical	Specified test load
Receiver propagation	200 ns maximum; 90 ns typical	15 pF output load
Driver enable / disable	70 ns maximum; 40 ns typical	Specified test circuits
Receiver enable / disable	50 ns maximum; 20 ns typical	Specified test circuits

Protocol turnaround must also include UART completion, firmware latency, cable delay and the receiving node’s timing.

Two-node half-duplex connection

5 V controllers · short teaching link

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
UART TX / RX	TX → DI4; RO1 → RX	5 V-compatible logic
Direction	GPIO → DE3 and RE̅2	10 kΩ pull-down: default receive
Twisted pair	A6 → A6; B7 → B7	Keep stubs short
Cable-end termination	120 Ω across A–B at each end	Two total; not at every node
Single idle-bias location	390 Ω from +5 V to A; 390 Ω from B to GND	Example only; review loading and tolerances
Ideal idle difference	5 × 60 / (390 + 60 + 390) ≈ 0.357 V	Two 120 Ω terminators in parallel; receiver loads omitted
Supply bypass	100 nF at each IC, VCC8 to GND5	Short local paths
Signal reference	Common reference conductor	Maintain each receiver’s common-mode limits

The bias estimate is a design illustration. Recalculate for actual transceiver count, tolerances, cable and ground offsets.

Packages and stress limits

MAX485EPA+ · PDIP-8

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
PDIP-8 EPA	P8-1 · 2.54 mm pitch	7.62 mm nominal lead rows
Narrow SOIC-8 ESA	S8-2 · 1.27 mm pitch	Separate surface-mount footprint
Supply absolute maximum	12 V	Not the normal operating voltage
A / B absolute voltage	−8 to +12.5 V	Receiver operation remains −7 to +12 V common mode
Logic pin stress	−0.5 to VCC + 0.5 V	DI, enables and RO
PDIP dissipation at 70°C	727 mW	Derate 9.09 mW/°C above 70°C
SOIC dissipation at 70°C	471 mW	Derate 5.88 mW/°C above 70°C
Storage temperature	−65 to +160°C	Unpowered

The alternate µMAX package in this family uses a different pin arrangement and is not represented by these DIP/SO maps.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Receive data1 pin

Direction controls2 pins

Transmit data1 pin

Ground1 pin

Differential bus2 pins

Supply1 pin

MAX485 working principle: illustrated functional stages, basic circuit and connections — Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Choose a direction

For the joined control, LOW enables the receiver and disables the driver. HIGH reverses those enable states.

Step 2 / 3

Drive the differential pair

DI HIGH makes A greater than B. DI LOW makes B greater than A. Only one node should actively drive.

Step 3 / 3

Recover the data

The receiving node compares A − B with its thresholds. UART framing and error handling remain the controller’s job.

TwoMAX485ICswithcontrollers,UARTTXRXdirection,100nFbypasseach,two120ohmendterminatorsandone390ohmApullupBpulldownbiasnetwork. — A/B naming follows MAX485. Matching labels connect; each node requires a common signal reference.

Connect it, step by step

Follow the component values and pin connections

Wire the controllers

Connect TX, RX and direction to each transceiver. Use a receive-default pull-down.

Terminate and bias once

Terminate only the two cable ends. The shown idle-bias pair is installed at one location.

Control ownership

Only one node transmits at a time. Wait for its final stop bit before releasing direction.

CompactMAX485cutawaywithDI4driverDE3,A6B7bus,andreceiverRO1enabledbyRE2withsupply8ground5. — Functional blocks; protection and transistor details are simplified.

Explore the circuit

Select a stage to see its role and connections

Transmit on demand

DE enables the driver and DI selects differential polarity.

Listen independently

RE̅ LOW enables the receiver; HIGH makes RO high impedance.

Share the bus

Driver disable releases A/B. Arbitration and protocol timing are supplied by the system.

Selected packagePDIP-8MAX485EPA+

Physical connections8 pinsPackage-specific numbering

Reference collection7 tables46 parameters & pin functions