MCP1700-3302 Reference Tables
Search the MCP1700-3302 pin reference and manufacturer-referenced specification tables.
Pin reference
Signal names, electrical functions and connection guidance
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| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| GND | Ground reference | Reference and low-current bias return.Connection guidanceJoin the input capacitor, output capacitor and load returns locally. Physical pin 1 in both selected packages. | |
| VIN | Supply input | Input to the CMOS low-dropout pass stage.Connection guidanceUse the example 5 V source with local 1 µF X7R bypass. TO-92 pin 2; SOT-23 pin 3. Recommended input is 2.3–6.0 V, subject to headroom. | |
| VOUT | Regulated output | Fixed nominal 3.3 V output.Connection guidanceFit at least 1 µF effective output capacitance close to VOUT and GND. TO-92 pin 3; SOT-23 pin 2. Up to 250 mA, thermally limited. |
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Ordering and physical pins
Standard extended-temperature 3.3 V parts
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Through-hole order | MCP1700-3302E/TO | TO-92, straight 1.27 mm pin pitch |
| SMD order | MCP1700T-3302E/TT | SOT-23; tape-and-reel order |
| TO-92 front-view pins | 1 GND; 2 VIN; 3 VOUT | Flat face toward viewer, leads downward |
| SOT-23 pins | 1 GND; 2 VOUT; 3 VIN | Package map rotated 90° for this page |
| 3302 code | 3.3 V output; standard 2% tolerance | E grade: −40 to 125°C |
| Other manufacturer packages | SOT-89 and DFN-6 also listed | Those land patterns are not included in this page |
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Illustrations identify the full order; actual SOT-23 3.3 V body marking uses CS plus traceability characters.
Operating ranges and limits
Use recommended values for the design
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Operating input | 2.3–6.0 V | Also satisfy VIN ≥ VOUT(max)+VDROPOUT |
| Absolute maximum input | 6.5 V | Stress limit only |
| Nominal output | 3.3 V | Fixed 3302 option |
| Output-current rating | 250 mA | For voltage options ≥2.5 V; thermally limited |
| Operating junction | −40 to 125°C | Maximum stress junction 150°C |
| Storage temperature | −65 to 150°C | Unpowered storage rating |
| Thermal shutdown | 140°C typical | Protection threshold; not an operating target |
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The regulator cannot step up a low input voltage.
Accuracy and regulation
VIN=nominal VOUT+1 V; 100 µA load; 1 µF X7R bypass unless noted
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Output at 25°C | ±2% maximum; ±0.4% typical | 3.234–3.366 V for 3.3 V nominal |
| Output over temperature | ±3% maximum | 3.201–3.399 V over −40 to 125°C |
| Temperature coefficient | 50 ppm/°C typical | Manufacturer characterization |
| Line regulation | ±0.75%/V typical; ±1%/V limits | VIN from nominal VOUT+1 V to 6 V |
| Load regulation | ±1% typical; ±1.5% limits | 0.1–250 mA; constant-junction pulse measurement |
| Dropout at 250 mA | 178 mV typical; 350 mV max. | Electrical-table voltage class >2.5 V; headline typical quoted at 2.8 V |
| Dropout definition | Output 2% below the value at 1 V headroom | Do not equate it to zero regulation error |
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At worst-case 3% output and 350 mV dropout, the simple input floor is 3.749 V before ripple margin.
Bias, current limit and dynamic conditions
Typical figures retain their test conditions
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| Parameter | Value | Conditions / notes |
|---|---|---|
| No-load quiescent current | 1.6 µA typical; 4 µA maximum | VIN=nominal VOUT+1 V |
| Short-circuit current | 408 mA typical | Peak measured 10 ms after short; no guaranteed minimum/maximum |
| Output rise time | 500 µs typical | 10–90%; VIN step 0–6 V; 50 Ω resistive load |
| Output-noise density | 3 µV/√Hz typical | 1 kHz; 100 mA; 1 µF output |
| PSRR reference test | 44 dB typical at 100 Hz | 1.2 V option; 50 mA; COUT1 µF; CIN0 µF; not a 3.3 V guarantee |
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Current limiting and thermal shutdown do not make sustained shorts a normal operating condition.
Input and output capacitors
Simple ceramic bypass, close to the leads
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Output capacitor | 1 µF minimum effective capacitance | X7R/X5R recommended; account for DC bias |
| Input capacitor | 1 µF in the example | Low source impedance needed for stability |
| Capacitor alternatives | Ceramic, tantalum or aluminum electrolytic | Check ESR, leakage and temperature behavior |
| Physical placement | OUT capacitor beside VOUT/GND | Keep load-return voltage drops small |
| Supply transient ceiling | Keep VIN within 6 V operating range | Include wiring-induced overshoot |
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A nominal 1 µF marking does not guarantee 1 µF after applied voltage and temperature.
Thermal design and calculated example
Board-dependent temperature rise
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| Parameter | Value | Conditions / notes |
|---|---|---|
| SOT-23 θJA | 212°C/W | JEDEC four-layer FR-4 board |
| SOT-23 θJC(bottom) | 11.95°C/W | Thermal metric; not a substitute for PCB analysis |
| TO-92 thermal resistance | Determine for the actual assembly | Not given in this selected table |
| Nominal load | 330 Ω →10 mA | 3.3²/330=33 mW; use ≥0.25 W resistor |
| Pass-stage loss at 10 mA | (5−3.3)×0.010=17 mW | Total adds VIN×IQ |
| Pass-stage loss at 250 mA | 425 mW | At 5 V input; ≈90°C rise using 212°C/W before bias term |
| Practical current ceiling | Depends on input voltage and ambient | Do not assume 250 mA is thermally available in every package |
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All example readings are calculated, not measured or time-domain simulated.
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