MCP30088-channel 10-bit SPI ADC

Eight analog channels. One compact serial interface.

Manufacturer-referenced

Microchip Technology · MCP3008-I/P

PDIP-16DS20001295E · 2022

MCP3008 is a 10-bit successive-approximation ADC with eight multiplexed analog inputs. A four-wire SPI connection selects one channel, acquires its voltage and returns a straight-binary code from 0 to 1023. The inputs are sampled one at a time, not simultaneously. Each conversion can use a single-ended channel or one of four adjacent pseudo-differential pairs. VREF defines the measurement span; at 3.3 V, one ideal step is about 3.223 mV. The negative input in pseudo-differential mode must remain close to ground. The views show MCP3008-I/P in PDIP-16 and MCP3008-I/SL in narrow SOIC-16, both industrial −40 to +85°C grades. Extended-temperature SOIC ordering options exist. The 3.3 V example keeps the ADC, reference and controller at compatible logic levels.

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MCP3008-I/P black package with silver leads and readable markings.

Pinout

MCP3008PDIP-16Top view

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16Physical pins MCP3008-I/PPDIP-16 Manufacturer-referencedMicrochip Technology

Pin diagram

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Package map

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MCP3008PDIP-16Top view

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PIN 1 · Channels & reference

CH0

Multiplexed analog input

Function

Channel 0; selected by the three channel bits in the SPI command.

How to connect

Connect a low-impedance signal within the selected reference range.

Electrical note

Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.

Key specifications

An input multiplexer feeds a sample-and-hold capacitor. A ten-bit SAR and DAC resolve the voltage; the SPI port shifts the result to the controller.

Resolution10 bits · 1024 codes

Analog channels8 Multiplexed

Supply range2.7–5.5 V

Selected I-grade−40–85 °C

Operating profile

Supply, signals and operating conditions

MCP3008 operating profile
Parameter	Value	Conditions / notes
Selected package	PDIP-16	MCP3008-I/P · 16 pins
Maximum rate at 5 V	200	ksps · specified conditions
SPI modes	0 / 3	Rising-edge input sampling

Package details

MCP3008-I/P · PDIP-16

Selected package

Selected MCP3008 physical package
Property	Details
Manufacturer	Microchip Technology
Part number	MCP3008-I/P
Package	PDIP-16
Connections	16 pins
Mounting	Through-hole
Lead pitch	2.54 mm
Package code	dip
Thermal reference	θJA 70°C/W, manufacturer package reference

Supply, reference and input limits

MCP3008 · selected industrial grades

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Operating supply	2.7–5.5 V	ADC and controller logic must be compatible
Reference input	0.25 V to VDD	Low-impedance source; reduced reference affects linearity
Single-ended range	0 to VREF	Measured relative to analog ground
Pseudo-differential IN−	−100 to +100 mV	Relative to ground; not a wide common-mode differential input
Pseudo-differential IN+	IN− to IN− + VREF	Observe pin voltage limits as well
Selected I-grade ambient	−40 to +85°C	MCP3008-I/P and MCP3008-I/SL
Extended SOIC option	−40 to +125°C	Use the corresponding E-grade ordering option

The table separates operating conditions from absolute stress limits.

Resolution and accuracy

VDD = VREF = 5 V unless stated

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Resolution	10 bits	Codes 0–1023
Ideal step	VREF / 1024	3.22265625 mV at 3.3 V
Integral nonlinearity	±1 LSB maximum	±0.5 LSB typical
Differential nonlinearity	±1 LSB maximum	No missing codes over specified temperature
Offset error, I grade	±1.5 LSB maximum	−40 to +85°C
Offset error, extended grade	±1.95 LSB maximum	−40 to +125°C
Gain error	±1 LSB maximum	Manufacturer electrical conditions
SINAD	61 dB typical	1 kHz signal, 0.1–4.9 V input

Ideal arithmetic does not include these device errors.

Acquisition and throughput

Supply-dependent SPI timing

Manufacturer specifications 9 parameters

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Parameter	Value	Conditions / notes
Acquisition window	1.5 SCLK periods	Source impedance must allow settling
Conversion	10 SCLK periods	Excludes command and framing overhead
Maximum throughput at 5 V	200 ksps	3.6 MHz SPI clock, 18-clock framing
Maximum throughput at 3.3 V	130 ksps	2.34 MHz, characterized recommendation
Maximum throughput at 2.7 V	75 ksps	1.35 MHz SPI clock
Chip-select HIGH time	270 ns minimum	Between conversions
CS LOW to first rising SCLK	100 ns minimum	Setup time
Input data setup / hold	50 ns / 50 ns minimum	Around rising SCLK edge
Effective conversion clock	At least 10 kHz	Finish after acquisition within 1.2 ms at high temperature

The 24-clock byte-oriented example has extra framing overhead; it does not achieve the 18-clock maximum throughput.

Three-byte single-ended transfer

SPI mode 0 or mode 3

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Byte 1 transmitted	0x01	Seven leading zeros, then START
Byte 2 transmitted	(0x08 \| channel) << 4	SGL = 1 followed by channel D2 D1 D0
Byte 3 transmitted	0x00	Clocks out the remaining result
Receive byte 1	Ignore	DOUT not valid result data
Receive byte 2	Keep bits 1:0	Result bits B9 and B8; discard upper bits
Receive byte 3	Keep all eight bits	B7 through B0
Assemble the result	((RX1 & 0x03) << 8) \| RX2	RX indices are zero-based
After transfer	CS HIGH	DOUT becomes Hi-Z; device enters standby

Pseudo-differential mode clears SGL. D2–D0 choose IN+; the other member of its adjacent pair is IN−.

Logic, loading and power

Manufacturer test conditions

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Digital HIGH / LOW input	≥ 0.7 × VDD / ≤ 0.3 × VDD	Do not assume 3.3 V logic reliably drives a 5 V ADC
Output HIGH	≥ 4.1 V	VDD = 4.5 V; source 1 mA
Output LOW	≤ 0.4 V	VDD = 4.5 V; sink 1 mA
Active current at 5 V	425 µA typical; 550 µA maximum	VREF = 5 V; DOUT unloaded
Standby current	5 nA typical; 2 µA maximum	CS = VDD = 5 V
Reference current	100 µA typical; 150 µA maximum	During conversion
Analog leakage	±1 µA maximum	0.001 µA typical
Sample capacitor	20 pF typical	Internal sampling-switch resistance ≈ 1 kΩ

The detailed electrical table specifies 550 µA maximum active current; use it rather than the older 500 µA feature-summary value.

3.3 V controller circuit

Single-ended channel 0

Manufacturer specifications 6 parameters

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Parameter	Value	Conditions / notes
VDD16 and VREF15	Regulated 3.3 V	Common source; VREF must not float
AGND14 and DGND9	Common ground	Keep analog returns quiet
Supply bypass	1 µF	Close to VDD and ground
Analog signal	0–3.3 V into CH0 pin1	Low-impedance source; unused channels grounded in the illustration
SPI wiring	CS10, DIN11, DOUT12, SCLK13	Controller CS, MOSI, MISO and SCLK respectively
Example SPI clock	1 MHz, mode 0	Three bytes per conversion; CS HIGH between transfers

Use a compatible 3.3 V controller. Input filters and buffering depend on bandwidth and source impedance.

Absolute maximum ratings

Stress limits only

Manufacturer specifications 3 parameters

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Parameter	Value	Conditions / notes
Supply	7.0 V maximum	Normal operation: 2.7–5.5 V
Any input/output	−0.6 to VDD + 0.6 V	Referenced to ground
Storage	−65 to +150°C	Unpowered

Absolute maximum ratings are not valid operating targets.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Channels & reference9 pins

Ground2 pins

Serial controls3 pins

Conversion output1 pin

Supply1 pin

MCP3008 working principle: illustrated functional stages, basic circuit and connections — Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Choose the input

Send a start bit, SGL/DIFF and D2–D0 while chip select is LOW. Single-ended channels use ground; pseudo-differential commands select adjacent pairs.

Step 2 / 3

Acquire and convert

The source charges the internal hold capacitor during the 1.5-clock acquisition window. Ten successive-approximation steps determine the result.

Step 3 / 3

Read the serial word

Sample DOUT on rising clock edges. Discard the null bit, keep the ten result bits and return chip select HIGH before the next conversion.

Choose a channel. Build the SPI message.

Explore 10-bit conversion and single-ended or pseudo-differential inputs.

Ideal code + command

Input mode Positive channel VREF · Pin 15 V CH0 voltage V

Channel selection is part of every conversion command. Differential results remain unsigned; a negative difference clips to zero.

IDEAL DECIMAL CODE512

0x2001000000000

CONTROLLER → DIN · Pin 1101 80 00Three transmit bytes · hexadecimal

DOUT → CONTROLLER · Pin 12XX X2 00X = discard · retain 10 result bits

IDEAL STEP3.2227 mVVREF / 1024

CS pin 10 stays LOW for the transaction. Use SCLK pin 13, mode 0 or 3. Read ((RX[1] & 3) << 8) | RX[2], then raise CS. Ideal code calculator and SPI command builder. It rounds to the nearest nominal code, clamps to 0–1023 and excludes timing, acquisition error and noise. Pseudo-differential IN− is limited to ±100 mV. Read the physical device using its specified SPI timing.

MCP3008 CH0 pin1 receives a0to3.3V signal. VDD16 and reference15 use3.3V; grounds9and14 are common. Four color-coded SPI wires connect CS10 DIN11 DOUT12 SCLK13 to a3.3Vcontroller. A1µF capacitor bypasses supply. — One channel is measured per conversion. The same serial interface selects any of the eight inputs.

Connect it, step by step

Follow the component values and pin connections

Power and reference

Connect both VDD and VREF to 3.3 V, join the grounds and place the 1 µF bypass nearby.

Connect the serial bus

Use MOSI→DIN, DOUT→MISO, SCLK→SCLK and a separate chip-select line.

Select and decode

Send 01 80 00 to select single-ended CH0. Combine the ten returned data bits; raise CS between measurements.

Inside MCP3008

Eight inputs share a sample-and-hold and ten-bit SAR core.

Simplified functional architecture, not a transistor-level die layout.

Explore the circuit

Select a stage to see its role and connections

Multiplex the channels

The command selects a single input or adjacent pseudo-differential pair.

Hold the analog sample

A sample capacitor stores the voltage while the SAR tests successive DAC levels.

Transfer the word

The result is shifted out MSB first; CS HIGH releases DOUT and ends the conversion.

Selected packagePDIP-16MCP3008-I/P

Physical connections16 pinsPackage-specific numbering

Reference collection8 tables49 parameters & pin functions