MP1584 Reference Tables, Pins & Specifications

Pin reference

Signal names, electrical functions and connection guidance

SOIC-8E

Physical pin numbers8 pins

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MP1584 pin functions and connections
Signal	Type	Function & connection
SW	Switching power node	The internal high-side MOSFET drives this node. The inductor and external catch diode complete the buck power stage. Connection guidance Connect the inductor to the output and the Schottky cathode to SW; its anode returns to ground. SW is a noisy switching node, not the regulated DC output.
EN	Enable input	A high level enables operation; a low level disables it. An open pin also enables the device. Connection guidance Leave open for the fixed 12 V example, or drive within the specified pin limits. Typical rising threshold 1.5 V. Do not tie EN directly to a 12 V input; its absolute maximum is 6 V.
COMP	Loop compensation	Error-amplifier output used to shape the converter feedback loop. Connection guidance Fit the reviewed series RC network from COMP to ground. Compensation depends on the inductor, output capacitance, ESR and operating conditions.
FB	Output-voltage feedback	The control loop compares the divided output to a nominal 0.8 V reference. Connection guidance Connect the midpoint of the output-to-ground divider. Route away from SW and the high-current loop.
GND	Ground and exposed pad	Return for control and power circuitry. The exposed underside pad also connects to ground. Connection guidance Join pin 5 and the exposed pad to a suitable ground plane. The footprint repeats electrical pad number 5 on the exposed pad; it does not invent a separate signal pin.
FREQ	Frequency programming	A resistor from FREQ to ground sets the switching frequency. Connection guidance Use 200 kΩ in the approximately 500 kHz example. The frequency setting is nominal; light-load pulse skipping changes the observed switching activity.
VIN	Input supply	Supplies the internal control and high-side switching stage. Connection guidance Place a low-ESR input bypass close to VIN and the power return. Operating input is 4.5–28 V; 30 V is an absolute stress limit, not a working target.
BST	Floating bootstrap supply	Provides gate-drive supply above the SW node. Connection guidance Connect 100 nF between BST and SW, with short traces. Observe the 6 V absolute BST-to-SW limit; this capacitor does not connect to ground.

Operating envelope

MP1584EN · limits and test conditions

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Input supply	4.5–28 V	Recommended operating range
Output adjustment	0.8–25 V	Must remain below input with adequate headroom
Output-current class	3 A	Limited by power components, temperature and layout
Operating junction	−20 to +125°C	Do not use shutdown temperature as an operating target
Ambient ordering range	−20 to +85°C	MP1584EN package reference
Package	SOIC-8E	Eight leads plus a grounded exposed pad
Lifecycle note	Not recommended for new designs	MPS identifies MP2338 as an alternative; it is not pin-compatible by assumption

Electrical table baseline is VIN = 12 V, VEN = 2.5 V, VCOMP = 1.4 V and TA = 25°C unless stated.

Electrical reference

Separate nominal behavior from guaranteed limits

Manufacturer-referenced values9 parameters

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Parameter	Value	Conditions / notes
Feedback voltage	0.776 / 0.800 / 0.824 V	Minimum / typical / maximum; 4.5 V < VIN < 28 V
High-side on resistance	150 mΩ typical	BST − SW = 5 V
Current-limit threshold	4.0 A minimum; 4.7 A typical	No maximum is stated here; not a 3 A output guarantee
UVLO rising threshold	2.7 / 3.0 / 3.3 V	Internal threshold; operation still requires the specified input range
UVLO hysteresis	0.35 V typical	Input undervoltage control
EN rising threshold	1.35 / 1.50 / 1.65 V	EN hysteresis 0.30 V typical
No-load quiescent current	100 µA typical; 125 µA maximum	FB = 0.9 V
Shutdown current	12 µA typical; 20 µA maximum	EN = 0 V
Soft start	1.5 ms	Design-guaranteed source value; FB from 0 to 0.8 V

Typical values do not establish worst-case performance.

Frequency and compensation

The example follows the 5 V compensation row

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Programmable frequency	100 kHz–1.5 MHz	External resistor at FREQ
RFREQ relationship	RFREQ[kΩ] = 180000 / f[kHz]^1.1	Approximate design equation
Example RFREQ	200 kΩ	Approximately 485 kHz by the equation; nominal 500 kHz class
Example output inductor	15 µH	Source table lists 15–22 µH for 5 V / 22 µF output
Example output capacitor	22 µF low-ESR ceramic	Account for capacitance loss under DC bias
COMP series network	100 kΩ and 150 pF to ground	Source 5 V compensation row
Extra COMP capacitor	Not fitted in this example	Evaluate separately for high-ESR output capacitors

Changing power-stage components can require a new loop-stability review.

12 V to nominal 5 V

Illustrative 1 A load · regulated bench input

Manufacturer-referenced values10 parameters

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Parameter	Value	Conditions / notes
Input / output	12 V / 4.984 V nominal	Before reference, resistor and regulation errors
Feedback divider	52.3 kΩ upper; 10 kΩ lower	Use 1% resistors; nominal divider current 80 µA
Bootstrap capacitor	100 nF	Between BST8 and SW1
Input bypass	10 µF, 50 V ceramic	Place close to VIN7 and the power return
Catch diode	40 V Schottky, at least 3 A class	Cathode at SW; anode at GND; check losses and surge ratings
Output inductor	15 µH, ≥4 A saturation rating for normal operation	Check RMS current and fault behavior separately
Output capacitor	22 µF, 10 V ceramic	Effective capacitance and ESR matter
Example load	5 Ω, at least 10 W	About 1 A and 5 W; resistor will dissipate heat
EN connection	Open	Fixed 12 V input example; do not tie EN to VIN
Ideal inductor ripple	About 0.39 A peak-to-peak at 500 kHz	12 V input, 5 V output, 15 µH; continuous-conduction approximation

This is an engineering starting circuit, not a claim of tested converter hardware.

Layout and startup

Short power paths; quiet feedback

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Hot loop	Input bypass → VIN / switch → catch diode → return	Keep the switching-current loop compact
SW copper	Short connection to inductor and diode	Keep clear of FB and compensation traces
Exposed pad	Connect to ground copper	Thermal vias and solder stencil need assembly-specific review
Bootstrap loop	BST capacitor close to BST and SW	Do not connect this capacitor to ground
Light-load headroom	VIN − VOUT greater than 3 V	Source guidance for refreshing the floating bootstrap supply
High duty ratio / low input	Review external bootstrap diode guidance	Source recommends it when VOUT/VIN >65% or VIN <5 V
Feedback pickup	Sense the regulated output after the inductor	Keep the divider and COMP components close to the IC

The fixed 12 V-to-5 V example provides generous bootstrap headroom.

Heat and stress limits

Stress ratings are not normal operating conditions

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Junction-to-ambient reference	50°C/W	JESD51-7 four-layer test board
Junction-to-case reference	10°C/W	Source package metric
Thermal shutdown	150°C typical	15°C typical hysteresis
Input absolute maximum	30 V	Normal operation limited to 28 V
BST relative to SW	−0.3 to +6 V	Absolute stress limits
Other control pins	−0.3 to +6 V	Includes EN; do not connect directly to a high input rail
Absolute junction / storage	150°C / −65 to +150°C	Stress / storage ratings

Actual temperature depends on switching losses, diode and inductor losses, copper and airflow.

Package and footprint

MP1584EN-LF-Z · top-view numbering

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Nominal molded body	3.9 × 4.9 mm	SOIC-8E; 1.27 mm lead pitch
Body height	1.30–1.70 mm	Manufacturer mechanical drawing
Lead span	5.80–6.20 mm	Across the two banks
Exposed pad	2.26–2.56 × 3.15–3.45 mm	Underside metal; electrically GND
Outer lands	1.60 × 0.61 mm	5.40 mm row centers; 1.27 mm pitch
Exposed land	2.62 × 3.51 mm	Same electrical pad number 5 as the GND lead
Surface mounting only	SOIC-8E	No through-hole version is presented

The original footprint is a starting land pattern; review mask, stencil, vias and assembly clearances.