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OPA2134Dual FET-input audio operational amplifier

Two quiet analog channels for audio and precision signals.

Manufacturer-referenced

Texas Instruments · OPA2134PA

PDIP-8SBOS058B · November 2024

OPA2134 contains two FET-input operational amplifiers optimized for low-noise, low-distortion analog signal conditioning. Each channel has independent inputs, output and external feedback while sharing its positive and negative supply rails. Its input bias current is only a few picoamperes typically at room temperature. The specified audio distortion is measured under particular gain, frequency, amplitude and load conditions; it does not describe every possible circuit. This reference follows TI revision B and the dual-channel PDIP-8 and SOIC-8 packages. The example uses ±15 V rails, one gain-of-three channel and one voltage follower. The device is not rail-to-rail, so both input and output headroom matter.

Real View

OPA2134PA black PDIP-8 package with silver contacts and readable marking.
OPA2134PA · PDIP-8Package illustration

Pinout

OPA2134PAPDIP-8Top view
Select a pin to see its functionPDIP-8 · 8 pins

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8Physical pins OPA2134PAPDIP-8 Manufacturer-referencedTexas Instruments

Pin diagram

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Package map
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OPA2134PAPDIP-8Top view

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1
PIN 1 · Analog outputs

OUT1

Analog output

Function

Channel A output.

How to connect

Return to IN1− through 20 kΩ; connect a high-impedance meter.

Key specifications

Independent feedback paths let one channel amplify while the other buffers. Keep the signal within the input common-mode range and output swing.

Total supply span5–36 V · recommended
Gain bandwidth8 MHz typical
Input voltage noise8 nV/√Hz at 1 kHz · typical
Ambient range−40 to +85 °C

Operating profile

Supply, signals and operating conditions

OPA2134 operating profile
ParameterValueConditions / notes
Selected packagePDIP-8OPA2134PA
Independent channels2Separate feedback; shared rails
Example outputs1.50 / 0.50V · ideal A / B
Use these values with the stated grade and test conditions.

Package details

OPA2134PA · PDIP-8

Selected package
Selected OPA2134 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberOPA2134PA
PackagePDIP-8
Connections8 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codePDIP-8
Thermal referenceSee operating and package limits

Operating conditions

TI OPA2134 · Rev B

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ParameterValueConditions / notes
Recommended split supplies±2.5 to ±18 V±15 V nominal test condition
Recommended single supply5–36 VSignal reference must provide appropriate headroom
Recommended temperature−40 to +85°CDo not substitute the absolute-rating range
Input common-mode intervalV− + 2.5 V to V+ − 3.5 VAt ±15 V: −12.5 V to +11.5 V
Example supply+15 V / 0 V / −15 V0 V is the shared signal midpoint
Absolute supply ceiling36 V totalAllow for supply tolerance and transients

The signal inputs cannot be assumed to work at either rail.

DC and input characteristics

±15 V, 25°C, unless stated

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ParameterValueConditions / notes
Input offset voltage±1 mV typical; ±3.5 mV maximumRevision B electrical table
Offset drift±2 µV/°C typical−40 to +85°C
Input bias current±5 pA typical; ±100 pA maximumHigh-speed test at junction temperature 25°C
Input bias over temperature±5 nA maximum−40 to +85°C
Input offset current±2 pA typical; ±50 pA maximum25°C
CMRR86 dB minimum; 100 dB typical−12.5 V to +11.5 V common mode
Quiescent current per channel4 mA typical; 5 mA maximumNo output load
Open-loop gain104 dB minimum; 120 dB typical2 kΩ load, −13.8 V to +13.5 V output

Use the stated revision and conditions; product-page summaries may differ from the detailed table.

Audio and noise

Typical values at the manufacturer test conditions

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ParameterValueConditions / notes
THD + noise0.00008%1 kHz, gain 1, 3 Vrms output, 2 kΩ load
THD + noise with heavier load0.00015%Same conditions, 600 Ω load
Input voltage-noise density8 nV/√Hz1 kHz
Integrated input voltage noise1.2 µVrms20 Hz–20 kHz
Input current-noise density3 fA/√Hz1 kHz
Channel separation126 dB typical20 kHz, 2 kΩ load

These values describe the IC test setup, not the total noise or distortion of a finished audio system.

Bandwidth, settling and output

±15 V reference conditions

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ParameterValueConditions / notes
Gain-bandwidth product8 MHz typicalClosed-loop bandwidth also depends on noise gain
Slew rate±20 V/µs typicalSpecified by design
Settling to 0.1% / 0.01%0.7 µs / 1 µs typical10 V step, gain 1, 100 pF load
Output swing with 2 kΩ loadV− + 1.2 V to V+ − 1.5 VSpecified output-voltage interval
Output swing with 10 kΩ loadV− + 0.5 V to V+ − 1.2 VLighter load permits greater swing
Short-circuit current36 mA source / −30 mA sink typicalFault characterization, not a normal load target

Check stability and output current when adding cables or capacitive loads.

Practical design notes

Stable feedback and low-noise layout

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ParameterValueConditions / notes
Supply bypass100 nF from each rail to signal GNDPlace close to pins 8 and 4; add suitable local bulk storage
Feedback loopsKeep short and separated from noisy outputsChannel A: pins 1–2; channel B: pins 7–6
High source impedanceBias-current and leakage errors still applyClean the board and avoid unnecessarily high feedback resistance
Single-supply audioProvide a suitable midpoint referenceGround is not automatically a valid signal bias
Input outside the railsRequires current limitingManufacturer absolute input-current limit is ±10 mA
Package distinctionOPA2134 is the dual versionOPA134 and OPA4134 use different physical maps

The reference circuit is a light-load gain demonstration, not a headphone or loudspeaker power amplifier.

Two-channel amplifier example

±15 V rails · 0 V signal reference

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ParameterValueConditions / notes
Input VIN0.50 VPins 3 and 5; common signal ground
Channel A feedback20 kΩOUT1 pin 1 to IN1− pin 2
Channel A ground resistor10 kΩIN1− pin 2 to 0 V
Channel A ideal output1.50 V0.50 × (1 + 20 / 10)
Channel B feedbackDirect connectionOUT2 pin 7 to IN2− pin 6
Channel B ideal output0.50 VUnity-gain follower
Bypass capacitors100 nF per railEach supply rail to the 0 V midpoint

The 0 V reference is not the negative supply pin. Keep both rail-bypass loops short.

Physical pin reference

OPA2134PA · PDIP-8

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ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
Channel AOUT1 1; IN1− 2; IN1+ 3Independent feedback loop
Channel BIN2+ 5; IN2− 6; OUT2 7Independent feedback loop
SupplyV− 4; V+ 8Shared by both channels
Package orientationTop view; pin 1 at the markerCounterclockwise numbering

This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Analog outputs2 pins

Analog inputs4 pins

Supply2 pins

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

OPA2134 at a glance

Follow the labeled connections and functional stages

OPA2134 working principle: illustrated functional stages, basic circuit and connections
Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Compare each input pair

The true FET input stage provides high input impedance and low room-temperature bias current. Source impedance, board contamination and rising temperature can still create measurable errors.

Step 2 / 3

Set two different gains

Channel A uses 20 kΩ feedback and 10 kΩ to the 0 V midpoint, giving a gain of three. Channel B directly feeds its output back to its negative input, giving unity gain.

Step 3 / 3

Check headroom and speed

With a 0.50 V input, the ideal outputs are 1.50 V and 0.50 V. Real output also depends on input offset, resistor accuracy, loading, noise and signal frequency.

OPA2134 in a circuit

A gain-of-three channel beside a unity-gain follower.

OPA2134PA on ±15 V rails. VIN 0.50 V connects to pins 3 and 5. Pin 1 feeds pin 2 through 20 kΩ; 10 kΩ joins pin 2 to 0 V. Pin 7 joins pin 6 directly. Both supply rails have 100 nF bypass to 0 V.
All VIN labels share one signal. All ground symbols are the 0 V supply midpoint.

Connect it, step by step

Follow the component values and pin connections

Connect power

Use +15 V at pin 8 and −15 V at pin 4, with a 100 nF bypass from each rail to signal ground.

Wire the feedback

Add the 20 kΩ / 10 kΩ network to channel A and join pins 7 and 6 for channel B.

Read both outputs

At a nominal input of 0.50 V, expect about 1.50 V from A and 0.50 V from B under light DC loading.

Inside OPA2134

Two FET differential inputs, compensated gain paths and output drivers.

Two FET-input amplifier channels inside a compact OPA2134 IC. A: positive 3, negative 2, output 1. B: positive 5, negative 6, output 7. Shared supplies 8 and 4.
Functional cutaway; internal compensation is included. External feedback sets the gain.

Explore the circuit

Select a stage to see its role and connections

Input stages

The true FET input stage provides high input impedance and low room-temperature bias current. Source impedance, board contamination and rising temperature can still create measurable errors.

Gain and compensation

Each channel has an internal voltage-gain path and frequency compensation.

Output drivers

Each output can drive an appropriate load inside its specified swing. Leave supply headroom and check capacitive-load stability; the short-circuit current is not a normal continuous-load rating.

Selected packagePDIP-8OPA2134PA
Physical connections8 pinsPackage-specific numbering
Reference collection8 tables44 parameters & pin functions

Pin reference

Signal names, electrical functions and connection guidance

PDIP-8
Physical pin numbers8 pins

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OPA2134 pin functions and connections
PinSignalTypeFunction & connection
OUT1Analog outputChannel A output.
Connection guidance

Return to IN1− through 20 kΩ; connect a high-impedance meter.

IN1−Inverting inputChannel A negative-feedback node.
Connection guidance

Join 20 kΩ from OUT1 and 10 kΩ to signal ground.

IN1+Non-inverting inputChannel A signal input.
Connection guidance

Apply VIN = 0.50 V relative to the 0 V midpoint.

V−Negative supplyNegative rail shared by both amplifiers.
Connection guidance

Connect −15 V; bypass locally to 0 V with 100 nF.

IN2+Non-inverting inputChannel B signal input.
Connection guidance

Connect to the same VIN in the illustrated follower.

IN2−Inverting inputChannel B feedback input.
Connection guidance

Connect directly to OUT2 pin 7.

OUT2Analog outputChannel B output.
Connection guidance

Connect to IN2−; leave unloaded or use a high-impedance instrument.

V+Positive supplyPositive rail shared by both amplifiers.
Connection guidance

Connect +15 V; bypass locally to 0 V with 100 nF.

PDIP-8 · Top view · Select a pin number to open its interactive pinout.

Operating conditions

TI OPA2134 · Rev B

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Recommended split supplies±2.5 to ±18 V±15 V nominal test condition
Recommended single supply5–36 VSignal reference must provide appropriate headroom
Recommended temperature−40 to +85°CDo not substitute the absolute-rating range
Input common-mode intervalV− + 2.5 V to V+ − 3.5 VAt ±15 V: −12.5 V to +11.5 V
Example supply+15 V / 0 V / −15 V0 V is the shared signal midpoint
Absolute supply ceiling36 V totalAllow for supply tolerance and transients

The signal inputs cannot be assumed to work at either rail.

DC and input characteristics

±15 V, 25°C, unless stated

Manufacturer-referenced values8 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Input offset voltage±1 mV typical; ±3.5 mV maximumRevision B electrical table
Offset drift±2 µV/°C typical−40 to +85°C
Input bias current±5 pA typical; ±100 pA maximumHigh-speed test at junction temperature 25°C
Input bias over temperature±5 nA maximum−40 to +85°C
Input offset current±2 pA typical; ±50 pA maximum25°C
CMRR86 dB minimum; 100 dB typical−12.5 V to +11.5 V common mode
Quiescent current per channel4 mA typical; 5 mA maximumNo output load
Open-loop gain104 dB minimum; 120 dB typical2 kΩ load, −13.8 V to +13.5 V output

Use the stated revision and conditions; product-page summaries may differ from the detailed table.

Audio and noise

Typical values at the manufacturer test conditions

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
THD + noise0.00008%1 kHz, gain 1, 3 Vrms output, 2 kΩ load
THD + noise with heavier load0.00015%Same conditions, 600 Ω load
Input voltage-noise density8 nV/√Hz1 kHz
Integrated input voltage noise1.2 µVrms20 Hz–20 kHz
Input current-noise density3 fA/√Hz1 kHz
Channel separation126 dB typical20 kHz, 2 kΩ load

These values describe the IC test setup, not the total noise or distortion of a finished audio system.

Bandwidth, settling and output

±15 V reference conditions

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Gain-bandwidth product8 MHz typicalClosed-loop bandwidth also depends on noise gain
Slew rate±20 V/µs typicalSpecified by design
Settling to 0.1% / 0.01%0.7 µs / 1 µs typical10 V step, gain 1, 100 pF load
Output swing with 2 kΩ loadV− + 1.2 V to V+ − 1.5 VSpecified output-voltage interval
Output swing with 10 kΩ loadV− + 0.5 V to V+ − 1.2 VLighter load permits greater swing
Short-circuit current36 mA source / −30 mA sink typicalFault characterization, not a normal load target

Check stability and output current when adding cables or capacitive loads.

Practical design notes

Stable feedback and low-noise layout

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Supply bypass100 nF from each rail to signal GNDPlace close to pins 8 and 4; add suitable local bulk storage
Feedback loopsKeep short and separated from noisy outputsChannel A: pins 1–2; channel B: pins 7–6
High source impedanceBias-current and leakage errors still applyClean the board and avoid unnecessarily high feedback resistance
Single-supply audioProvide a suitable midpoint referenceGround is not automatically a valid signal bias
Input outside the railsRequires current limitingManufacturer absolute input-current limit is ±10 mA
Package distinctionOPA2134 is the dual versionOPA134 and OPA4134 use different physical maps

The reference circuit is a light-load gain demonstration, not a headphone or loudspeaker power amplifier.

Two-channel amplifier example

±15 V rails · 0 V signal reference

Manufacturer-referenced values7 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Input VIN0.50 VPins 3 and 5; common signal ground
Channel A feedback20 kΩOUT1 pin 1 to IN1− pin 2
Channel A ground resistor10 kΩIN1− pin 2 to 0 V
Channel A ideal output1.50 V0.50 × (1 + 20 / 10)
Channel B feedbackDirect connectionOUT2 pin 7 to IN2− pin 6
Channel B ideal output0.50 VUnity-gain follower
Bypass capacitors100 nF per railEach supply rail to the 0 V midpoint

The 0 V reference is not the negative supply pin. Keep both rail-bypass loops short.

Physical pin reference

OPA2134PA · PDIP-8

Manufacturer-referenced values5 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
Channel AOUT1 1; IN1− 2; IN1+ 3Independent feedback loop
Channel BIN2+ 5; IN2− 6; OUT2 7Independent feedback loop
SupplyV− 4; V+ 8Shared by both channels
Package orientationTop view; pin 1 at the markerCounterclockwise numbering

This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.

Read each value with its conditions

Typical values describe the stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Texas Instruments · SBOS058B · November 2024
Official PDF datasheet

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