PCF8574 Specifications
Review PCF8574 electrical specifications, operating conditions and package details.
Key specifications
Each port bit combines an output latch, a sink driver and a weak HIGH current source. Writing 1 prepares an input; writing 0 actively pulls the terminal LOW.
Package details
PCF8574N · PDIP-16
| Property | Details |
|---|---|
| Manufacturer | Texas Instruments |
| Part number | PCF8574N |
| Package | PDIP-16 |
| Connections | 16 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | dip |
| Thermal reference | Board and package dependent; see manufacturer data |
Port behavior
Quasi-bidirectional operation
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Latch bit 0 | Active LOW sink | Suitable for sinking a current-limited LED |
| Latch bit 1 | Weak current-source HIGH | Can be pulled LOW externally and used as input |
| Power-on state | All latch bits HIGH | Pins behave as inputs with weak HIGH sources |
| Direction registers | None | Direction follows the output-latch state |
| Read value | Actual terminal levels | May differ from the software output shadow |
| Output update | Whole 8-bit byte | Keep all input bits HIGH in every write |
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HIGH is not a sustained strong push-pull output. The temporary strong pull-up assists a rising edge only.
Address selection
7-bit addresses; do not include the R/W bit
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| Parameter | Value | Conditions / notes |
|---|---|---|
| A2 A1 A0 = 000 | 0x20 | Write byte 0x40 · read byte 0x41 |
| A2 A1 A0 = 001 | 0x21 | Write byte 0x42 · read byte 0x43 |
| A2 A1 A0 = 010 | 0x22 | Write byte 0x44 · read byte 0x45 |
| A2 A1 A0 = 011 | 0x23 | Write byte 0x46 · read byte 0x47 |
| A2 A1 A0 = 100 | 0x24 | Write byte 0x48 · read byte 0x49 |
| A2 A1 A0 = 101 | 0x25 | Write byte 0x4a · read byte 0x4b |
| A2 A1 A0 = 110 | 0x26 | Write byte 0x4c · read byte 0x4d |
| A2 A1 A0 = 111 | 0x27 | Write byte 0x4e · read byte 0x4f |
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PCF8574A has a different address block. This page uses PCF8574.
Example byte transfers
Address pins grounded · 7-bit address 0x20
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| Parameter | Value | Conditions / notes |
|---|---|---|
| LED off; inputs released | Write 0xFF | All port latches HIGH |
| LED on at P0 | Write 0xFE | P0 LOW; P1–P7 remain HIGH |
| Read the button | Read one byte; inspect bit 1 | P1 LOW when the grounded button is pressed |
| Typical pressed read with LED on | 0xFC | Assumes other released inputs read HIGH |
| Transfer structure | START → address → data → STOP | No register-address byte |
| INT servicing | Read port, process changes, debounce | Read/write or return to original state can reset INT |
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The example values describe the stated wiring. Do not use a read byte as an unfiltered output-latch shadow.
Electrical limits
Recommended operation unless marked otherwise
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VCC | 2.5–6 V | Example uses 5 V |
| Input HIGH / LOW | ≥ 0.7 VCC / ≤ 0.3 VCC | Supply-dependent logic thresholds |
| P-port weak HIGH source | 30–310 µA magnitude | At VO = GND, VCC 2.5–6 V |
| P-port sink | 10 mA minimum; 25 mA typical | At VCC 5 V, VO 1 V |
| Recommended LOW current | 25 mA maximum per port | Observe total device and thermal limits |
| SDA sink | 3 mA minimum | At VOL 0.4 V |
| INT sink | 1.6 mA minimum | At VOL 0.4 V |
| Standby supply current | 2.5 µA typical; 10 µA maximum | VCC 6 V; inputs at rails; unloaded |
| Operating supply current | 40 µA typical; 100 µA maximum | VCC 6 V; 100 kHz clock; unloaded |
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Do not interpret the absolute 50 mA port rating as a design target.
Bus timing and pull-ups
Standard-mode I²C
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| Parameter | Value | Conditions / notes |
|---|---|---|
| SCL frequency | 100 kHz maximum | Not a 400 kHz fast-mode expander |
| SCL LOW / HIGH | 4.7 µs / 4.0 µs minimum | Timing requirements |
| SDA setup | 250 ns minimum | Before SCL rises |
| Bus rise time | 1 µs maximum | Choose pull-ups for capacitance and sink current |
| Maximum bus capacitance | 400 pF | Requires a compatible pull-up value |
| Example pull-ups | 4.7 kΩ on SDA and SCL | About 0.40 µs rise at an assumed 100 pF |
| Port / interrupt delay | 4 µs maximum | Specified switching-test conditions |
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The example 4.7 kΩ is a starting value for a short bus, not a guarantee at the full 400 pF limit.
Button and LED connections
5 V controller and expander
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply | VCC16 +5 V; GND8 common | 100 nF local bypass |
| Address | A0 pin1, A1 pin2, A2 pin3 to GND | Selects 0x20 |
| SDA15 / SCL14 | Controller I²C bus | Each has a 4.7 kΩ pull-up to +5 V |
| INT13 | Controller interrupt input | 10 kΩ pull-up to +5 V |
| P0 pin4 | LED cathode | Anode via 1 kΩ to +5 V; LOW turns it on |
| P1 pin5 | Pushbutton to GND | Write latch bit 1 before reading; debounce |
| P2–P7 | Unused in this example | Leave open and maintain latch bits HIGH |
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At assumed VF 2 V and VOL 0.2 V, LED current is (5 − 2 − 0.2)/1k = 2.8 mA. Actual values depend on the LED and port.
Package selection and stress limits
PCF8574N · PDIP-16
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| Parameter | Value | Conditions / notes |
|---|---|---|
| N package | PDIP-16; 2.54 mm pitch | Through-hole view shown |
| DW package | Wide SOIC-16; 1.27 mm pitch | 7.5 mm nominal body width |
| PW / DGV alternatives | 20 physical leads | Different mapping with unused pins; not shown |
| VCC absolute maximum | 6.5 V | Normal recommended maximum is 6 V |
| Continuous supply/ground current | ±100 mA absolute maximum | Stress rating; sum all loads |
| Storage temperature | −65 to +150°C | Unpowered |
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The two selected 16-pin packages share logical pin numbering but require different PCB footprints.
Connections by function
Select a pin for its function, connection guidance and electrical notes.