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SG3525AAlternating-output PWM controller

Start gently. Switch alternately. Shut down cleanly.

Manufacturer-referenced

STMicroelectronics · SG3525AN

PDIP-16SG2525A / SG3525A · June 2000

SG3525A is a dual-output PWM controller with an oscillator, error amplifier, pulse-steering flip-flop and source/sink output drivers. Its two outputs alternate, with a LOW off state and an interval in which both are off. External RT, CT and RD set the oscillator period and dead time. A soft-start capacitor limits the initial pulse width, while the shutdown input can terminate a pulse immediately and restart the soft-start sequence after a longer command. This page uses ST SG3525AN and SG3525AP variants. The 12 V scope circuit demonstrates timing, startup and shutdown without a transformer or power MOSFET stage. A complete regulated supply additionally needs feedback, compensation and power-stage protection.

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Real View

SG3525AN black PDIP-16 package with silver contacts and readable marking.
SG3525AN · PDIP-16Package illustration

Pinout

SG3525ANPDIP-16Top view
Select a pin to see its functionPDIP-16 · 16 pins

PCB Footprint

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Finding PDIP-16 packageTop view · mm
Error amplifierTiming and protection controlsClock and driver outputsRC oscillatorSupplies and returnBias reference
SG3525ANPDIP-16Top view

Click a lead or use the arrow keys. Top view

1
PIN 1 · Error amplifier

INV

Inverting error input

Function

A higher voltage than NI2 reduces the demand for output conduction.

How to connect

Connect to the midpoint of two 10 kΩ resistors from REF16 to GND in this pulse demonstration.

At a glance

Alternating-output PWM controller

The oscillator clocks the steering flip-flop. PWM, soft start, shutdown and undervoltage lockout determine whether a pulse reaches an output.

8–35 V recommendedControl supply
5.1 VNominal reference
100 Hz–400 kHz See RT / CT / RD limitsRecommended oscillator
0–70 °CSG3525A ambient

Operating profile

SG3525AN

Selected package
PDIP-16SG3525AN
Each output
fOSC / 2Alternating channels
Soft-start current
50 µATypical · 25–80 µA specified

Recommended operating region

Key parameters and their test conditions

Control supply VI
8–35 VConditions / notes: Pin 15
Driver supply VC
4.5–35 VConditions / notes: Pin 13; separate driver supply
Ambient temperature
0 to +70°CConditions / notes: SG3525A; do not substitute SG2525A limits
Oscillator frequency
100 Hz–400 kHzConditions / notes: Recommended conditions table
Steady output load
0–100 mA source or sinkConditions / notes: Per output; thermal design still applies
Peak output load
0–400 mAConditions / notes: Peak operation only

Package details

Follows the selected physical package

Manufacturer
STMicroelectronics
Part number
SG3525AN
Package
PDIP-16
Connections
16 pins
Mounting
Through-hole
Lead pitch
2.54 mm
Package code
PDIP-16
Thermal reference
See operating and package limits

Connections by function

Select a pin to open its function, electrical notes and wiring guidance.

Error amplifier2 pins

Timing and protection controls4 pins

Clock and driver outputs3 pins

RC oscillator3 pins

Supplies and return3 pins

Bias reference1 pins

Set the clock and dead time

RT6 and CT5 set the charging interval. RD between pins 5 and 7 lengthens capacitor discharge and the blanking interval.

Release pulses gradually

Soft start limits PWM demand as its capacitor charges. The error amplifier determines the requested conduction after startup.

Steer and protect

Outputs A and B take alternate cycles. Shutdown or undervoltage lockout makes both outputs LOW.

RT, CT and RD establish the oscillator rate. Each output repeats at half that rate, and neither output is allowed a continuous 100% duty cycle.

Compact SG3525A cutaway with reference and UVLO, RC oscillator, error amplifier, soft start, shutdown, PWM latch and alternating drivers.
Functional architecture; the timing network and regulated power stage are external.
Physical SG3525AN with RT CT RD network, soft-start capacitor, defined inputs, reference divider, shutdown switch and two scope channels.
Matching node labels connect; all grounds are common. Readings and waveforms are illustrative.

Pin reference

Select a pin to explore its function and connection.

16 pins
PinSignalTypeFunction
INVInverting error inputA higher voltage than NI2 reduces the demand for output conduction.
NINoninverting error inputA higher voltage than INV1 requests a longer pulse.
SYNCOscillator synchronization inputExternal positive clock pulses can synchronize the oscillator.
OSC OUTOscillator clock outputClock at the oscillator rate, before alternating output steering.
CTTiming capacitor nodeThe oscillator charges and discharges this external capacitor.
RTTiming resistor nodeSets the oscillator charging current.
DISCHARGETiming discharge contactThe external resistance between this pin and CT sets extra discharge dead time.
SOFT STARTSoft-start capacitor nodeAn internal current charges the capacitor and gradually releases the pulse-width limit.
COMPError-amplifier compensationError-amplifier output and PWM control node. External compensation shapes a real regulator loop.
SHUTDOWNActive-HIGH shutdownA positive input turns both outputs off; a sustained command discharges soft start.
OUT AFirst alternating outputTotem-pole output driven from VC13. LOW is the OFF state.
GNDCommon returnReturn for the control supply, reference, oscillator and output drivers.
VCOutput-driver supplySeparate supply for the two output stages.
OUT BSecond alternating outputReceives alternate oscillator cycles relative to OUT A. LOW is the OFF state.
VIControl supplyPowers the reference and internal control circuitry.
VREF5.1 V referenceBias reference for low-current control networks.
PDIP-16 · Top view · Select a pin number to inspect its connection.

Recommended operating region

ST SG3525A

ParameterValueConditions / notes
Control supply VI8–35 VPin 15
Driver supply VC4.5–35 VPin 13; separate driver supply
Ambient temperature0 to +70°CSG3525A; do not substitute SG2525A limits
Oscillator frequency100 Hz–400 kHzRecommended conditions table
Steady output load0–100 mA source or sinkPer output; thermal design still applies
Peak output load0–400 mAPeak operation only
Reference load0–20 mAExternal control bias

The operating table is used here; the front-page frequency headline is broader.

Oscillator and PWM

External components set the rate

ParameterValueConditions / notes
RT2–150 kΩPin 6 to GND
CT1–100 nFPin 5 to GND
RD0–500 ΩBetween pins 5 and 7
Frequency equationfOSC ≈ 1 / [CT × (0.7 RT + 3 RD)]First-order approximation
Output repetitionfA = fB = fOSC / 2Alternating cycles
Maximum duty per output45% minimum capability; 49% typicalManufacturer test setup
PWM zero-duty threshold0.7 V minimum; 0.9 V typicalControl threshold, not shutdown-pin threshold
PWM maximum-duty threshold3.3 V typical; 3.6 V maximumSpecified test conditions

Timing tolerances and propagation effects matter; calculated values are not measured guarantees.

Reference and amplifier

Keep bias within the valid region

ParameterValueConditions / notes
Initial reference5.0–5.2 V; 5.1 V typicalSG3525A at TJ = 25°C
Total reference variation4.95–5.25 VSpecified line, load and temperature
Amplifier offset2 mV typical; 10 mV maximumSpecified test conditions
Open-loop gain75 dB typical; 60 dB minimumRL ≥ 10 MΩ
Common-mode test region1.5–5.2 VManufacturer rejection-ratio test
Example input biasINV ≈ 2.55 V; NI ≈ 5.1 VRequests maximum pulse width after soft start

Pin 9 is an amplifier output; external forcing must account for its internal drive.

Soft start and shutdown

Two ways to inhibit pulses

ParameterValueConditions / notes
Soft-start charging current25–80 µA; 50 µA typicalVSD = 0 V, VSS = 0 V
Shutdown threshold0.6–1.0 V; 0.8 V typicalOutput shutdown test at TJ = 25°C
Shutdown input current0.4 mA typical; 1 mA maximumVSD = 2.5 V
Short shutdown pulseTerminates the current PWM pulseMay not substantially discharge CSS
Long shutdown commandDischarges CSSSoft start repeats after release
UVLO threshold6–8 V; 7 V typicalSpecified test with COMP and SS HIGH
Off stateOUT A = LOW; OUT B = LOWSG3525A logic

Keep shutdown defined. It is not a general-purpose power-stage fault detector without external sensing.

12 V scope circuit

No high-power switching stage

ParameterValueConditions / notes
VI15 and VC13+12 V100 nF at each rail plus local bulk bypass
GND12Common groundShort control and bypass returns
REF16100 nF bypassFeeds NI2, shutdown switch and divider
INV1REF / 2Two 10 kΩ divider resistors
NI2 / COMP9REF / no external connectionRequests full available PWM; soft start still limits startup
SYNC3 / OSC OUT4GND / openFree-running oscillator; optional clock probe
RT6 / CT510 kΩ / 10 nF to GNDRD = 100 Ω from CT5 to DISCHARGE7
SOFT START81 µF to GNDPositive at pin 8 if polarized
SHUTDOWN1010 kΩ to GNDNormally open pushbutton connects it to REF16
OUT A11 / OUT B14Separate high-impedance scope channelsOptional 10 kΩ load from each output to ground

Do not connect outputs together; their active intervals alternate.

Example readings

Nominal calculated values

ParameterValueConditions / notes
Oscillator period10 nF × (0.7 × 10 kΩ + 3 × 100 Ω) = 73 µsFirst-order estimate
Oscillator frequencyApproximately 13.70 kHzInverse of 73 µs
Each output frequencyApproximately 6.85 kHzHalf the oscillator rate
Each output periodApproximately 146 µsAlternating cycle allocation
Divider load5.1 V / 20 kΩ = 0.255 mANominal reference
Soft-start slope50 µA / 1 µF = 50 V/sTypical initial slope
Soft-start voltage change1 V in about 20 msNot a guaranteed complete startup time

Real startup also depends on amplifier demand, capacitor tolerance, charging current and PWM thresholds.

Packages and stress limits

SG3525AN · PDIP-16

ParameterValueConditions / notes
Through-holeSG3525AN · DIP162.54 mm lead pitch
Surface mountSG3525AP · narrow SO161.27 mm lead pitch
VI / VC absolute maximum40 VStress rating, not normal operating voltage
Output absolute maximum500 mADo not treat as a continuous drive rating
Reference absolute maximum50 mARecommended external load is lower
Storage temperature−65 to +150°CUnpowered
Logic-input absolute range−0.3 to +5.5 VDo not apply the 12 V rail to shutdown or sync

Footprints are editable starting land patterns; validate clearances and the purchased package before fabrication.

Take it into ProTech

Find SG3525A in the Components Library to place its schematic symbol and connect its pins.

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