TL072Dual FET-input operational amplifier
Two high-impedance analog channels in one compact IC.
TL072 integrates two FET-input operational amplifiers. Each channel compares a pair of input voltages and uses external negative feedback to control its gain. The physical example uses channel A as a gain-of-three amplifier and channel B as a voltage follower. A shared 0.50 V input gives ideal outputs of 1.50 V and 0.50 V from a ±15 V supply. This page follows TI’s July 2025 reference for the C-grade P and D packages. Its revised P/D specifications differ from the legacy PS package; the manufacturer’s package-specific columns are kept separate.
8Physical pins
TL072CPPDIP-8
Manufacturer-referencedTexas Instruments
Pin diagram
Select a pin to explore its connection
Highlight
TL072CPPDIP-8Top view
TL072CDRSOIC-8Top view
Click a lead or use the arrow keys. Top view
PIN 1 · Analog outputs
Analog outputOUT1
Function
Channel A output.
How to connect
Return to IN1− through 20 kΩ; connect a high-impedance meter.
PIN 2 · Analog inputs
Inverting inputIN1−
Function
Channel A negative-feedback node.
How to connect
Join 20 kΩ from OUT1 and 10 kΩ to signal ground.
PIN 3 · Analog inputs
Non-inverting inputIN1+
Function
Channel A signal input.
How to connect
Apply VIN = 0.50 V relative to the 0 V midpoint.
PIN 4 · Supply
Negative supplyV−
Function
Negative rail shared by both amplifiers.
How to connect
Connect −15 V; bypass locally to 0 V with 100 nF.
PIN 5 · Analog inputs
Non-inverting inputIN2+
Function
Channel B signal input.
How to connect
Connect to the same VIN in the illustrated follower.
PIN 6 · Analog inputs
Inverting inputIN2−
Function
Channel B feedback input.
How to connect
Connect directly to OUT2 pin 7.
PIN 7 · Analog outputs
Analog outputOUT2
Function
Channel B output.
How to connect
Connect to IN2−; leave unloaded or use a high-impedance instrument.
PIN 8 · Supply
Positive supplyV+
Function
Positive rail shared by both amplifiers.
How to connect
Connect +15 V; bypass locally to 0 V with 100 nF.
Key specifications
High input impedance suits voltage buffering and active filters. Each channel needs its own negative-feedback path.
Supply span4.5–40 V · TI P/D packages, Rev W
Typical bandwidth5.25 MHz · P/D packages
C-grade ambient0–70 °C
Typical slew rate20 V/µs · specified test
Package details
TL072CP · PDIP-8
| Property | Details |
|---|---|
| Manufacturer | Texas Instruments |
| Part number | TL072CP |
| Package | PDIP-8 |
| Connections | 8 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | dip |
| Thermal reference | Board and package dependent; see manufacturer data |
Operating conditions
TI TL072C · P/D package columns
Manufacturer specifications 5 parameters
Scroll sideways to see all columns.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Total supply span | 4.5–40 V | V+ minus V−; Rev W, all except NS/PS/M |
| Ambient temperature | 0 to +70°C | TL072C grade |
| Recommended input range | V− + 4 V to V+ + 0.1 V | Observe supply and signal restrictions |
| Example supply | +15 V / −15 V | 0 V is the midpoint |
| Legacy PS package | 10–30 V total supply | Different column; not the package illustrated here |
No specifications match. Try a parameter name or a unit.
Values follow the stated revision and package. Do not apply current P/D limits to an unidentified older die.
DC characteristics
±15 V · 25°C unless stated
Manufacturer specifications 7 parameters
Scroll sideways to see all columns.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Input offset voltage | 3 mV typical; 10 mV maximum | TL072C; RS = 50 Ω |
| Input offset, full temperature | 13 mV maximum | 0–70°C |
| Input bias current | 65 pA typical; 200 pA maximum | 7 nA maximum over temperature |
| Input offset current | 5 pA typical; 100 pA maximum | 10 nA maximum over temperature |
| Supply current per amplifier | 1.4 mA typical; 2.5 mA maximum | No load; output at 0 V |
| Common-mode range | ±11 V minimum; −12 to +15 V typical | ±15 V test supply |
| Output swing | ±12 V minimum; ±13.5 V typical | RL = 10 kΩ |
No specifications match. Try a parameter name or a unit.
Typical values describe representative devices; use specified limits for error budgets.
Dynamic characteristics
TI Rev W · P/D packages
Manufacturer specifications 5 parameters
Scroll sideways to see all columns.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Gain-bandwidth product | 5.25 MHz typical | P/D package column |
| Slew rate | 8 V/µs minimum; 20 V/µs typical | 10 V input; CL = 100 pF; RL = 2 kΩ |
| Input voltage noise at 1 kHz | 37 nV/√Hz typical | All except PS/NS/M |
| Input voltage noise at 10 kHz | 21 nV/√Hz typical | P/D package column |
| Phase margin | 56° typical | Gain +1; RL = 10 kΩ; CL = 20 pF |
No specifications match. Try a parameter name or a unit.
Bandwidth, slew rate and settling behavior are different limits; check all three for a changing signal.
Two-channel amplifier example
±15 V rails · 0 V signal reference
Manufacturer specifications 7 parameters
Scroll sideways to see all columns.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Input VIN | 0.50 V | Pins 3 and 5; common signal ground |
| Channel A feedback | 20 kΩ | OUT1 pin 1 to IN1− pin 2 |
| Channel A ground resistor | 10 kΩ | IN1− pin 2 to 0 V |
| Channel A ideal output | 1.50 V | 0.50 × (1 + 20 / 10) |
| Channel B feedback | Direct connection | OUT2 pin 7 to IN2− pin 6 |
| Channel B ideal output | 0.50 V | Unity-gain follower |
| Bypass capacitors | 100 nF per rail | Each supply rail to the 0 V midpoint |
No specifications match. Try a parameter name or a unit.
The 0 V reference is not the negative supply pin. Keep both rail-bypass loops short.
Physical pin reference
TL072CP · PDIP-8
Manufacturer specifications 5 parameters
Scroll sideways to see all columns.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 2.54 mm | Through-hole |
| Channel A | OUT1 1; IN1− 2; IN1+ 3 | Independent feedback loop |
| Channel B | IN2+ 5; IN2− 6; OUT2 7 | Independent feedback loop |
| Supply | V− 4; V+ 8 | Shared by both channels |
| Package orientation | Top view; pin 1 at the marker | Counterclockwise numbering |
No specifications match. Try a parameter name or a unit.
This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.
Connections by function
Select a pin for its function, connection guidance and electrical notes.
Analog outputs2 pins
Analog inputs4 pins
Supply2 pins
Analog outputs2 pins
Analog inputs4 pins
Supply2 pins
TL072 at a glance
Follow the labeled connections and functional stages
How it works
3 stages · Explore one step at a time
Compare each input pair
The FET input stage draws very little bias current at room temperature. Source resistance, board leakage and temperature still affect the input error.
Set two different gains
Channel A uses 20 kΩ feedback and 10 kΩ to the 0 V midpoint, giving a gain of three. Channel B directly feeds its output back to its negative input, giving unity gain.
Check headroom and speed
With a 0.50 V input, the ideal outputs are 1.50 V and 0.50 V. Real output also depends on input offset, resistor accuracy, loading, noise and signal frequency.
Step 1 of 3
TL072 in a circuit
A gain-of-three channel beside a unity-gain follower.
Connect it, step by step
Follow the component values and pin connections
Connect power
Use +15 V at pin 8 and −15 V at pin 4, with a 100 nF bypass from each rail to signal ground.
Wire the feedback
Add the 20 kΩ / 10 kΩ network to channel A and join pins 7 and 6 for channel B.
Read both outputs
At a nominal input of 0.50 V, expect about 1.50 V from A and 0.50 V from B under light DC loading.
Inside TL072
Two FET input stages, compensated gain paths and independent outputs.
Explore the circuit
Select a stage to see its role and connections
Input stages
The FET input stage draws very little bias current at room temperature. Source resistance, board leakage and temperature still affect the input error.
Gain and compensation
Each channel has an internal voltage-gain path and frequency compensation.
Output drivers
Each amplifier drives its own output. Neither output is assumed rail-to-rail; maintain the documented load and voltage headroom.
Selected packagePDIP-8TL072CP
Physical connections8 pinsPackage-specific numbering
Reference collection6 tables29 parameters & pin functions
Pin reference
Signal names, electrical functions and connection guidance
Physical pin numbers8 pins
Scroll within the table to see all columns and rows.
| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| OUT1 | Analog output | Channel A output.Connection guidanceReturn to IN1− through 20 kΩ; connect a high-impedance meter. | |
| IN1− | Inverting input | Channel A negative-feedback node.Connection guidanceJoin 20 kΩ from OUT1 and 10 kΩ to signal ground. | |
| IN1+ | Non-inverting input | Channel A signal input.Connection guidanceApply VIN = 0.50 V relative to the 0 V midpoint. | |
| V− | Negative supply | Negative rail shared by both amplifiers.Connection guidanceConnect −15 V; bypass locally to 0 V with 100 nF. | |
| IN2+ | Non-inverting input | Channel B signal input.Connection guidanceConnect to the same VIN in the illustrated follower. | |
| IN2− | Inverting input | Channel B feedback input.Connection guidanceConnect directly to OUT2 pin 7. | |
| OUT2 | Analog output | Channel B output.Connection guidanceConnect to IN2−; leave unloaded or use a high-impedance instrument. | |
| V+ | Positive supply | Positive rail shared by both amplifiers.Connection guidanceConnect +15 V; bypass locally to 0 V with 100 nF. |
No pins match these filters. Try another signal name or reset the filters.
Operating conditions
TI TL072C · P/D package columns
Manufacturer-referenced values5 parameters
Scroll within the table to see all columns and rows.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Total supply span | 4.5–40 V | V+ minus V−; Rev W, all except NS/PS/M |
| Ambient temperature | 0 to +70°C | TL072C grade |
| Recommended input range | V− + 4 V to V+ + 0.1 V | Observe supply and signal restrictions |
| Example supply | +15 V / −15 V | 0 V is the midpoint |
| Legacy PS package | 10–30 V total supply | Different column; not the package illustrated here |
No specifications match. Try a parameter name or a unit.
Values follow the stated revision and package. Do not apply current P/D limits to an unidentified older die.
DC characteristics
±15 V · 25°C unless stated
Manufacturer-referenced values7 parameters
Scroll within the table to see all columns and rows.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Input offset voltage | 3 mV typical; 10 mV maximum | TL072C; RS = 50 Ω |
| Input offset, full temperature | 13 mV maximum | 0–70°C |
| Input bias current | 65 pA typical; 200 pA maximum | 7 nA maximum over temperature |
| Input offset current | 5 pA typical; 100 pA maximum | 10 nA maximum over temperature |
| Supply current per amplifier | 1.4 mA typical; 2.5 mA maximum | No load; output at 0 V |
| Common-mode range | ±11 V minimum; −12 to +15 V typical | ±15 V test supply |
| Output swing | ±12 V minimum; ±13.5 V typical | RL = 10 kΩ |
No specifications match. Try a parameter name or a unit.
Typical values describe representative devices; use specified limits for error budgets.
Dynamic characteristics
TI Rev W · P/D packages
Manufacturer-referenced values5 parameters
Scroll within the table to see all columns and rows.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Gain-bandwidth product | 5.25 MHz typical | P/D package column |
| Slew rate | 8 V/µs minimum; 20 V/µs typical | 10 V input; CL = 100 pF; RL = 2 kΩ |
| Input voltage noise at 1 kHz | 37 nV/√Hz typical | All except PS/NS/M |
| Input voltage noise at 10 kHz | 21 nV/√Hz typical | P/D package column |
| Phase margin | 56° typical | Gain +1; RL = 10 kΩ; CL = 20 pF |
No specifications match. Try a parameter name or a unit.
Bandwidth, slew rate and settling behavior are different limits; check all three for a changing signal.
Two-channel amplifier example
±15 V rails · 0 V signal reference
Manufacturer-referenced values7 parameters
Scroll within the table to see all columns and rows.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Input VIN | 0.50 V | Pins 3 and 5; common signal ground |
| Channel A feedback | 20 kΩ | OUT1 pin 1 to IN1− pin 2 |
| Channel A ground resistor | 10 kΩ | IN1− pin 2 to 0 V |
| Channel A ideal output | 1.50 V | 0.50 × (1 + 20 / 10) |
| Channel B feedback | Direct connection | OUT2 pin 7 to IN2− pin 6 |
| Channel B ideal output | 0.50 V | Unity-gain follower |
| Bypass capacitors | 100 nF per rail | Each supply rail to the 0 V midpoint |
No specifications match. Try a parameter name or a unit.
The 0 V reference is not the negative supply pin. Keep both rail-bypass loops short.
Physical pin reference
TL072CP · PDIP-8
Manufacturer-referenced values5 parameters
Scroll within the table to see all columns and rows.
| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 2.54 mm | Through-hole |
| Channel A | OUT1 1; IN1− 2; IN1+ 3 | Independent feedback loop |
| Channel B | IN2+ 5; IN2− 6; OUT2 7 | Independent feedback loop |
| Supply | V− 4; V+ 8 | Shared by both channels |
| Package orientation | Top view; pin 1 at the marker | Counterclockwise numbering |
No specifications match. Try a parameter name or a unit.
This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.
No matching rowsTry a pin name, parameter, unit or test condition, or reset the filters.
High-impedance buffers
Buffer suitable high-resistance signal sources with attention to input leakage and common-mode range.
Manufacturer application guideActive filters
Use separate feedback networks to build two filter stages, or a filter and an output buffer.
Manufacturer application guideAudio conditioning
Build gain or mixing stages with appropriate coupling, supply decoupling and load headroom.
Manufacturer application guideTake it into ProTech
Find TL072 in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech