TL081Single JFET-input operational amplifier

High input impedance for sensitive analog signals.

Manufacturer-referenced

STMicroelectronics · TL081CN

PDIP-8TL081 · Rev 3 · June 2008

TL081 is a single operational amplifier with a JFET input stage and internal frequency compensation. It is useful when the signal source should supply very little input current. The example uses ±15 V rails and a gain of ten. A physical IC, two feedback resistors and local bypass capacitors show how a small input produces a larger output without changing polarity. This reference follows ST’s TL081C grade: TL081CN in DIP-8 and TL081CDT in SO-8. The pins retain the same numbers in both packages; limits from other manufacturers or newer revisions are not mixed into these tables.

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TL081CN black package with silver leads and readable markings.

Pinout

TL081CNPDIP-8Top view

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8Physical pins TL081CNPDIP-8 Manufacturer-referencedSTMicroelectronics

Pin diagram

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Package map

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TL081CNPDIP-8Top view

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PIN 1 · Offset trim

NULL1

Offset null

Function

Optional input-offset trim connection.

How to connect

Leave open for the illustrated circuit.

Electrical note

Use the ST offset-adjustment network if trimming is required.

Key specifications

A JFET input reduces source loading, while external negative feedback determines useful gain.

Supply span6–36 V · total rail-to-rail span

Typical gain-bandwidth4 MHz · specified ±15 V test

C-grade ambient0–70 °C

Typical slew rate16 V/µs · specified test

Operating profile

Supply, signals and operating conditions

TL081 operating profile
Parameter	Value	Conditions / notes
Selected package	PDIP-8	TL081CN
Input technology	JFET	Low bias at room temperature
Example gain	10×	0.20 V → 2.00 V, ideal

Package details

TL081CN · PDIP-8

Selected package

Selected TL081 physical package
Property	Details
Manufacturer	STMicroelectronics
Part number	TL081CN
Package	PDIP-8
Connections	8 pins
Mounting	Through-hole
Lead pitch	2.54 mm
Package code	dip
Thermal reference	Board and package dependent; see manufacturer data

Operating conditions

ST TL081C grade

Manufacturer specifications 5 parameters

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Parameter	Value	Conditions / notes
Total supply span	6–36 V	V+ minus V−
Ambient temperature	0 to +70°C	C-grade devices
Reference test supply	±15 V	Used for electrical values unless stated
Common-mode range	±11 V minimum; −12 to +15 V typical	±15 V supply; see manufacturer conditions
Example input	0.20 V	Relative to the 0 V midpoint

A typical range is not a guaranteed operating boundary. Use the specified minimum range for design margin.

DC characteristics

±15 V · 25°C · TL081C

Manufacturer specifications 5 parameters

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Parameter	Value	Conditions / notes
Input offset voltage	3 mV typical; 10 mV maximum	RS = 50 Ω
Input resistance	1 TΩ typical	Manufacturer Ri characteristic
Input offset current	5 pA typical; 100 pA maximum	Difference between input currents at 25°C
No-load supply current	1.4 mA typical; 2.5 mA maximum	Per amplifier
Open-loop gain	200 V/mV typical; 25 minimum	RL = 2 kΩ; VO = ±10 V

Bias leakage rises rapidly with temperature; room-temperature leakage values do not apply over the full range.

Output and dynamic characteristics

±15 V · specified tests

Manufacturer specifications 5 parameters

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Parameter	Value	Conditions / notes
Output swing at RL = 10 kΩ	±13.5 V typical; ±12 V minimum	25°C
Output swing at RL = 2 kΩ	±12 V typical; ±10 V minimum	25°C
Gain-bandwidth product	4 MHz typical; 2.5 MHz minimum	RL = 2 kΩ; CL = 100 pF; f = 100 kHz
Slew rate	16 V/µs typical; 8 V/µs minimum	Unity gain; 10 V input step; RL = 2 kΩ; CL = 100 pF
Input noise density	15 nV/√Hz typical	RS = 100 Ω; 1 kHz

Do not infer output current or stability from bandwidth alone.

Gain-of-ten example

Split-supply non-inverting stage

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Power rails	+15 V / −15 V	Pins 7 and 4
Input	0.20 V	IN+ pin 3
Feedback	90 kΩ	OUT pin 6 to IN− pin 2
Ground resistor	10 kΩ	IN− pin 2 to 0 V
Ideal gain / output	10 V/V / 2.00 V	1 + 90 / 10
Bypass	100 nF per rail	Each rail to the 0 V midpoint
Trim and NC	Pins 1, 5, 8 open	No offset-trim network in this circuit

The meter is high impedance. Real output includes offset, noise and resistor errors.

Package and pin reference

TL081CN · PDIP-8

Manufacturer specifications 6 parameters

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Parameter	Value	Conditions / notes
Pitch	2.54 mm	Through-hole
Inputs	IN− 2; IN+ 3	JFET differential pair
Output	6	Single analog channel
Power	V− 4; V+ 7	0 V is the external supply midpoint
Offset trim	1 and 5	Optional; consult the exact manufacturer circuit
No connection	8	Leave open

Do not confuse TL081’s single-amplifier pinout with the dual TL072 pinout.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Offset trim2 pins

JFET signal inputs2 pins

Supply2 pins

Analog output1 pin

Not connected1 pin

TL081 working principle: illustrated functional stages, basic circuit and connections — Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Sense with JFET inputs

The differential input stage has a high input impedance. Leakage still rises with temperature, so a high-impedance source needs careful board cleanliness and bias analysis.

Step 2 / 3

Close the feedback loop

A 90 kΩ resistor returns the output to IN− and a 10 kΩ resistor connects that node to 0 V. Their ratio sets a nominal non-inverting gain of ten.

Step 3 / 3

Allow headroom and bandwidth

The amplifier needs input and output headroom. At higher frequencies, gain-bandwidth and slew rate limit the signal independently of the resistor ratio.

TL081CN poweredfrom±15Vwith100nFrailbypasses.0.2VtoIN+3.OUT6through90ktoIN−2and10kto0V.Trimpins1and5andNC8open. — All ground symbols are the 0 V midpoint, not the negative supply rail.

Connect it, step by step

Follow the component values and pin connections

Power both rails

Connect +15 V to pin 7 and −15 V to pin 4, with a 100 nF local bypass from each rail to ground.

Set the gain

Use 90 kΩ feedback and 10 kΩ to ground; apply VIN to IN+.

Observe the output

0.20 V becomes 2.00 V ideally. Keep the input and requested output within the specified ranges.

TL081 functional stages inside a compact IC outline: JFET differential input, compensated voltage gain and output driver, with offset contacts and split supply. — Functional cutaway; not a transistor-level die schematic.

Explore the circuit

Select a stage to see its role and connections

JFET input pair

The input pair compares IN+ and IN− with low room-temperature leakage.

Internal compensation

The gain stage includes frequency compensation for practical feedback circuits.

Output stage

The driver delivers the signal with finite rail headroom and load capability.

Selected packagePDIP-8TL081CN

Physical connections8 pinsPackage-specific numbering

Reference collection6 tables28 parameters & pin functions