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TLV1117-33800 mA fixed-output linear regulator

A compact 3.3 V supply, with silicon revision made explicit.

Manufacturer-referenced

Texas Instruments · TLV1117-33IKVURG3

TO-252SLVS561O · June 2025

TLV1117-33 is a fixed 3.3 V linear regulator with an 800 mA output-current class. It converts a higher DC supply into a regulated rail through a series-pass stage. Its available current depends on dropout headroom, board cooling and the 125°C operating junction limit. The selected TLV1117-33IKVURG3 uses a TO-252 surface-mount package: GND1, OUT2 and IN3, with the exposed tab connected to OUT. The Real View, interactive pinout, 3D model and downloadable footprint all describe this exact package. TI specifies both legacy and newer silicon under this family. Their dropout, bias current and capacitor requirements differ. Check the shipment’s CSO identifier before applying the new-chip ceramic-capacitor example: SFB identifies legacy silicon; RFB or FFAB identifies new silicon.

3D View

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Real View

TLV1117-33 black TO-252 with bright formed silver leads, center stub and exposed output tab.
TLV1117-33IKVURG3 · TO-252Package illustration

Pinout

TLV1117-33TO-252Front face · leads down · 1 GND, 2 OUT, 3 IN; tab OUT
Select a pin to see its functionTO-252 · 3 pins

PCB Footprint

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3Physical pins TLV1117-33IKVURG3TO-252 Manufacturer-referencedTexas Instruments

Pin diagram

Select a pin to explore its connection

Package map
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TLV1117-33TO-252Front face · leads down · 1 GND, 2 OUT, 3 IN; tab OUT

Click a lead or use the arrow keys. Front face · leads down · 1 GND, 2 OUT, 3 IN; tab OUT

1
PIN 1 · Ground

GND

Ground reference

Function

Reference and bias return for the fixed 3.3 V regulator.

How to connect

Join input return, capacitor returns and load ground locally.

Electrical note

Lead 1. The tab is OUTPUT, not ground.

Key specifications

The voltage name is shared, but legacy and new fixed-output silicon have different dropout, ground current and stability requirements.

Fixed output3.3 V nominal
Current class800 mA · thermally limited
New-chip no-load bias65 µA typical at 15 V
I-grade junction range−40–125 °C recommended

Operating profile

Supply, signals and operating conditions

TLV1117-33 operating profile
ParameterValueConditions / notes
Selected packageTO-252TLV1117-33IKVURG3
Recommended input4.7–15 V16 V absolute maximum is not an operating target
New-chip example1 µF COUTEffective capacitance; ESR 2–500 mΩ
Use these values with the stated grade and test conditions.

Package details

TLV1117-33IKVURG3 · TO-252

Selected package
Selected TLV1117-33 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberTLV1117-33IKVURG3
PackageTO-252
Connections3 pins
MountingSMD
Lead pitch2.29 mm
Package codeKVU
Thermal referenceNew-chip θJA 67.2°C/W under TI board conditions; actual mounting changes temperature rise

Exact order and silicon revision

One verified fixed-3.3 V package

Scroll sideways to see all columns.

ParameterValueConditions / notes
Selected orderTLV1117-33IKVURG3TO-252 KVU; industrial junction range
Package markingZF33Manufacturer marking plus traceability data
Physical electrical nodes1 GND; 2 OUT/tab; 3 INMetal tab must not be grounded
Legacy chip identifierCSO SFBUse legacy limits and stability guidance
New chip identifiersCSO RFB or FFABUse new fixed-output specifications
Through-hole optionNot offered on this pageNo matching fixed-3.3 V through-hole order verified in the selected order table

Package illustrations show identity; use the shipment label to distinguish silicon.

Operating range and accuracy

Selected I-grade device

Scroll sideways to see all columns.

ParameterValueConditions / notes
Recommended input4.7–15 VAdd ripple margin above worst-case dropout
Absolute maximum input16 VStress rating only
Output current0–800 mALimited by heat and source headroom
Recommended junction−40 to 125°CNot the ambient-temperature rating
Output at 25°C3.267–3.333 VVIN5 V, 10 mA load
I-grade output over specified range3.168–3.432 VVIN4.75–10 V; 0–800 mA; full temperature
I-grade line regulation1 mV typical; 10 mV maximumVIN4.75–15 V, no load
I-grade load regulation1 mV typical; 15 mV maximumVIN4.75 V; 0–800 mA

C-grade temperature and accuracy limits are not substituted.

Dropout: legacy versus new

I-grade limits; load matters

Scroll sideways to see all columns.

ParameterValueConditions / notes
Legacy at 100 mA1.1 V typical; 1.3 V maximumOutput dropout test
Legacy at 500 mA1.15 V typical; 1.35 V maximumOutput dropout test
Legacy at 800 mA1.2 V typical; 1.4 V maximumOutput dropout test
New fixed chip at 100 mA0.2 V typical; 0.4 V maximumNew-chip specification
New fixed chip at 500 mA0.5 V typical; 0.8 V maximumNew-chip specification
New fixed chip at 800 mA0.8 V typical; 1.2 V maximumNew-chip specification

The family operating input range still applies; dropout alone does not define the minimum permitted input.

Ground current and protection

Do not mix the silicon columns

Scroll sideways to see all columns.

ParameterValueConditions / notes
Legacy fixed-output ground current5 mA typical; 15 mA maximumVIN≤15 V
New fixed no-load ground current65 µA typical; 110 µA maximumVIN15 V; not a full-load bias specification
Legacy current limit0.8 A min.; 1.2 A typ.; 1.6 A max.5 V input/output differential, 25°C
New fixed current limit1.1 A typical; 1.6 A maximumVOUT=90% nominal; specified input headroom
New fixed short-circuit current150–350 mA; 250 mA typicalFoldback protection; not useful output power
New fixed thermal shutdown180°C typical; reset 160°C typicalProtection values, far above normal operating limits

Keep the junction below 125°C in normal service.

Capacitors and revision selection

The diagram targets new fixed-output silicon

Scroll sideways to see all columns.

ParameterValueConditions / notes
Illustrated input bypass10 µF ceramicClose to IN and GND; choose voltage rating and effective capacitance
Illustrated output capacitor1 µF effective ceramicTI new-chip example uses 1 µF
New fixed-output ESR2–500 mΩRecommended operating condition
Ceramic dielectricX7R or X5RAccount for tolerance, temperature and DC bias
Legacy output capacitorAt least 10 µF tantalumFollow the legacy stability guidance, not the new-chip example
Long input wiringUse local input capacitanceEspecially when source impedance exceeds 0.5 Ω

A nominal capacitor value does not guarantee its effective value under applied voltage.

Board cooling and calculated load

TO-252 soldered directly to a PCB

Scroll sideways to see all columns.

ParameterValueConditions / notes
New-chip KVU θJA67.2°C/WTI reference-board thermal metric
Legacy KVU θJA50.9°C/WDifferent silicon column and board-dependent metric
Example output load33 Ω →100 mA nominalLoad power 330 mW; use ≥1 W resistor
Example pass loss(5−3.3)×0.1=170 mWAdd VIN×actual ground current
Full 800 mA pass loss at 5 V1.36 WBefore bias term; large heat rise in small copper areas
Approximate rise at 1.36 W91°C using 67.2°C/WBoard-dependent estimate, not a guaranteed temperature

The headline 800 mA rating is not a promise at arbitrary input voltage and ambient.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Ground1 pin

Regulated output and tab1 pin

Supply1 pin

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

TLV1117-33 at a glance

Follow the labeled connections and functional stages

TLV1117-33 working principle: illustrated functional stages, basic circuit and connections
Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Identify the shipment

Check the CSO identifier: SFB legacy, RFB/FFAB new. Do not infer silicon solely from the output voltage.

Step 2 / 3

Bypass for that revision

The new-chip example uses 1 µF effective ceramic COUT, within the specified ESR range. Legacy guidance is different.

Step 3 / 3

Cool the output tab

The tab is OUT. Its PCB copper removes heat but must not short to ground.

TLV1117-33 in a circuit

TO-252 physical connections and ceramic bypass.

Real-looking TLV1117 TO252,5Vinput3,ground1,outputtab2,10uFinput,1uFoutput,33ohmload.
For new fixed-output silicon only; verify CSO RFB/FFAB and effective capacitor values.

Connect it, step by step

Follow the component values and pin connections

Supply

Apply 5 V to IN3; connect GND1 to the common return.

Bypass

Use local 10 µF input and 1 µF effective output ceramic capacitors.

Load

The 33 Ω load draws nominally 100 mA. The exposed tab is OUT2.

Inside TLV1117-33

A compact reference, pass stage and feedback loop inside the package.

TLV1117 fixed feedback,reference,error amplifier,pass stage,current and thermal protection inside a package outline.
Functional explanation, not a transistor-level netlist or exact die layout.

Explore the circuit

Select a stage to see its role and connections

Compare

Compare divided output voltage against the internal reference.

Regulate

Change pass-device drive to correct the error.

Protect

Limit overload and excessive junction temperature.

Selected packageTO-252TLV1117-33IKVURG3
Physical connections3 pinsPackage-specific numbering
Reference collection7 tables38 parameters & pin functions

Pin reference

Signal names, electrical functions and connection guidance

TO-252
Physical pin numbers3 pins

Scroll within the table to see all columns and rows.

TLV1117-33 pin functions and connections
PinSignalTypeFunction & connection
GNDGround referenceReference and bias return for the fixed 3.3 V regulator.
Connection guidance

Join input return, capacitor returns and load ground locally.

Lead 1. The tab is OUTPUT, not ground.

OUTRegulated output and tabFixed 3.3 V output; also connected to the large exposed tab.
Connection guidance

Connect the load and output stability capacitor here.

Lead 2 and exposed thermal tab are one electrical node.

INSupply inputInput to the protected series-pass stage.
Connection guidance

Use +5 V with local ceramic bypass in the illustrated circuit.

Recommended 4.7–15 V for this output; allow dropout and ripple margin.

TO-252 · Front face · leads down · 1 GND, 2 OUT, 3 IN; tab OUT · Select a pin number to open its interactive pinout.

Exact order and silicon revision

One verified fixed-3.3 V package

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Selected orderTLV1117-33IKVURG3TO-252 KVU; industrial junction range
Package markingZF33Manufacturer marking plus traceability data
Physical electrical nodes1 GND; 2 OUT/tab; 3 INMetal tab must not be grounded
Legacy chip identifierCSO SFBUse legacy limits and stability guidance
New chip identifiersCSO RFB or FFABUse new fixed-output specifications
Through-hole optionNot offered on this pageNo matching fixed-3.3 V through-hole order verified in the selected order table

Package illustrations show identity; use the shipment label to distinguish silicon.

Operating range and accuracy

Selected I-grade device

Manufacturer-referenced values8 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Recommended input4.7–15 VAdd ripple margin above worst-case dropout
Absolute maximum input16 VStress rating only
Output current0–800 mALimited by heat and source headroom
Recommended junction−40 to 125°CNot the ambient-temperature rating
Output at 25°C3.267–3.333 VVIN5 V, 10 mA load
I-grade output over specified range3.168–3.432 VVIN4.75–10 V; 0–800 mA; full temperature
I-grade line regulation1 mV typical; 10 mV maximumVIN4.75–15 V, no load
I-grade load regulation1 mV typical; 15 mV maximumVIN4.75 V; 0–800 mA

C-grade temperature and accuracy limits are not substituted.

Dropout: legacy versus new

I-grade limits; load matters

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Legacy at 100 mA1.1 V typical; 1.3 V maximumOutput dropout test
Legacy at 500 mA1.15 V typical; 1.35 V maximumOutput dropout test
Legacy at 800 mA1.2 V typical; 1.4 V maximumOutput dropout test
New fixed chip at 100 mA0.2 V typical; 0.4 V maximumNew-chip specification
New fixed chip at 500 mA0.5 V typical; 0.8 V maximumNew-chip specification
New fixed chip at 800 mA0.8 V typical; 1.2 V maximumNew-chip specification

The family operating input range still applies; dropout alone does not define the minimum permitted input.

Ground current and protection

Do not mix the silicon columns

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Legacy fixed-output ground current5 mA typical; 15 mA maximumVIN≤15 V
New fixed no-load ground current65 µA typical; 110 µA maximumVIN15 V; not a full-load bias specification
Legacy current limit0.8 A min.; 1.2 A typ.; 1.6 A max.5 V input/output differential, 25°C
New fixed current limit1.1 A typical; 1.6 A maximumVOUT=90% nominal; specified input headroom
New fixed short-circuit current150–350 mA; 250 mA typicalFoldback protection; not useful output power
New fixed thermal shutdown180°C typical; reset 160°C typicalProtection values, far above normal operating limits

Keep the junction below 125°C in normal service.

Capacitors and revision selection

The diagram targets new fixed-output silicon

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
Illustrated input bypass10 µF ceramicClose to IN and GND; choose voltage rating and effective capacitance
Illustrated output capacitor1 µF effective ceramicTI new-chip example uses 1 µF
New fixed-output ESR2–500 mΩRecommended operating condition
Ceramic dielectricX7R or X5RAccount for tolerance, temperature and DC bias
Legacy output capacitorAt least 10 µF tantalumFollow the legacy stability guidance, not the new-chip example
Long input wiringUse local input capacitanceEspecially when source impedance exceeds 0.5 Ω

A nominal capacitor value does not guarantee its effective value under applied voltage.

Board cooling and calculated load

TO-252 soldered directly to a PCB

Manufacturer-referenced values6 parameters

Scroll within the table to see all columns and rows.

ParameterValueConditions / notes
New-chip KVU θJA67.2°C/WTI reference-board thermal metric
Legacy KVU θJA50.9°C/WDifferent silicon column and board-dependent metric
Example output load33 Ω →100 mA nominalLoad power 330 mW; use ≥1 W resistor
Example pass loss(5−3.3)×0.1=170 mWAdd VIN×actual ground current
Full 800 mA pass loss at 5 V1.36 WBefore bias term; large heat rise in small copper areas
Approximate rise at 1.36 W91°C using 67.2°C/WBoard-dependent estimate, not a guaranteed temperature

The headline 800 mA rating is not a promise at arbitrary input voltage and ambient.

Read each value with its conditions

Typical values describe the stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Texas Instruments · SLVS561O · June 2025
Official PDF datasheet

Take it into ProTech

Find TLV1117-33 in the Components Library to place its schematic symbol and connect its pins.

Reference page · circuit simulation model not yet availableOpen ProTech

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