W25Q32JV32-Mbit Dual/Quad SPI NOR flash

Four mebibytes of nonvolatile storage on a compact SPI bus.

Manufacturer-referenced

Winbond Electronics · W25Q32JVDAIQ

PDIP-8Revision C · 30 August 2016

W25Q32JV is a 32-Mbit serial NOR flash memory, equivalent to 4 MiB of addressable storage. It retains data without power and supports standard, Dual and Quad SPI instructions. A controller supplies the clock and commands; the memory does not execute application code by itself. The array contains 16,384 pages of 256 bytes and 1,024 erasable 4 KiB sectors. Programming changes selected bits from one to zero, while an erase restores an entire sector or block to ones. Firmware must split page writes and preserve data that shares an erase unit. The views show the industrial Q-option PDIP-8 and 208-mil SOIC-8 packages from the referenced Winbond revision. Both operate at 2.7–3.6 V, with IO2 and IO3 reserved for quad transfers. The basic circuit uses 3.3 V standard SPI to read the JEDEC identification bytes EF 40 16 without altering memory.

Real View

W25Q32JVDAIQ black PDIP-8 package with silver contacts and readable marking.

Pinout

W25Q32JVPDIP-8Top view

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8Physical pins W25Q32JVDAIQPDIP-8 Manufacturer-referencedWinbond Electronics

Pin diagram

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Package map

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W25Q32JVPDIP-8Top view

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PIN 1 · Serial control

/CS

Active-LOW select

Function

Frames each serial command. HIGH deselects the chip and releases the data outputs.

How to connect

Connect to controller chip-select with a pull-up to 3.3 V; keep HIGH during power-up.

Electrical note

Program and erase commands must end on a complete byte boundary.

Key specifications

A serial command engine feeds address decoders, a page-program buffer and the NOR cell array. Status bits report whether an internal program or erase cycle is still busy.

Storage32 Mbit · 4 MiB

Supply range2.7–3.6 V

Program page256 bytes

Industrial ambient−40–85 °C

Operating profile

Supply, signals and operating conditions

W25Q32JV operating profile
Parameter	Value	Conditions / notes
Selected package	PDIP-8	W25Q32JVDAIQ
Smallest erase unit	4	KiB sector
Fast-command ceiling	133	MHz at 3.0–3.6 V · command-dependent

Package details

W25Q32JVDAIQ · PDIP-8

Selected package

Selected W25Q32JV physical package
Property	Details
Manufacturer	Winbond Electronics
Part number	W25Q32JVDAIQ
Package	PDIP-8
Connections	8 pins
Mounting	Through-hole
Lead pitch	2.54 mm
Package code	PDIP-8
Thermal reference	See operating and package limits

Memory organization

Binary sizes, addresses and boundaries

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Capacity	32 Mbit / 4,194,304 bytes	4 MiB, not 32 megabytes
Address range	0x000000–0x3FFFFF	24-bit address field for normal array commands
Program page	256 bytes	16,384 pages
Sector erase	4 KiB	1,024 sectors
Block erase	32 KiB or 64 KiB	128 or 64 blocks respectively
Erased state	0xFF per byte	All bits are ones
Programming direction	1 → 0	Erase required for 0 → 1
Page boundary	Split writes before it	Excess program data wraps within the selected page

Plan data structures around erase units and power-loss recovery.

Common standard-SPI commands

MSB first; separate CS transaction for each command

Manufacturer specifications 11 parameters

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Parameter	Value	Conditions / notes
Read JEDEC identification	9F	Returns EF 40 16 for the reviewed device
Read data	03 + 24-bit address	No dummy byte; clock ceiling 50 MHz
Fast read	0B + address + dummy byte	Observe supply-dependent fast-command limit
Write enable / disable	06 / 04	Sets / clears Write Enable Latch
Read status register 1	05	BUSY bit0, WEL bit1
Page program	02 + address + data	1…256 bytes, without crossing a page
Erase 4 KiB sector	20 + address	Requires Write Enable
Erase 32 / 64 KiB block	52 / D8 + address	Requires Write Enable
Chip erase	C7 or 60	Erases the entire array
Power-down / release	B9 / AB	Observe entry and recovery timing
Software reset sequence	66 then 99	Two command frames; allow reset recovery

Identification and read commands do not modify user memory. Programming, erasing and protection writes do.

Supply, logic and startup

Revision C selected industrial variants

Manufacturer specifications 9 parameters

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Parameter	Value	Conditions / notes
Supply	2.7–3.6 V	Example: regulated 3.3 V
Industrial ambient	−40 to +85°C	I temperature grade
Input HIGH / LOW	≥0.7×VCC / ≤0.3×VCC	Not 5 V tolerant
Normal 03 read clock	Up to 50 MHz	At specified supply range
Other supported command clocks	Up to 133 MHz	VCC=3.0–3.6 V; not every framing mode has identical throughput
Fast-command clock at 2.7–3.0 V	Up to 104 MHz	Meet AC timing and loading requirements
VCC valid to CS LOW	20 µs minimum	Keep CS HIGH during startup
Delay before write instruction	5 ms minimum	After power becomes valid
Local bypass	100 nF in the example	Short loop between VCC8 and GND4

The 1 MHz identification example is intentionally well below the speed ceiling.

Program, erase and recovery times

Typical values and maximum completion limits

Manufacturer specifications 9 parameters

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Parameter	Value	Conditions / notes
Page program	0.7 ms typical / 3 ms maximum	Poll BUSY rather than delaying only the typical time
4 KiB sector erase	45 ms typical / 400 ms maximum	Target erase unit only
32 KiB block erase	120 ms typical / 1.6 s maximum	Larger erase scope
64 KiB block erase	150 ms typical / 2 s maximum	Larger erase scope
Chip erase	10 s typical / 50 s maximum	Entire memory
Write status register	10 ms typical / 15 ms maximum	Protection/configuration operation
Power-down entry	3 µs maximum	After CS rises for B9
Release without ID read	3 µs maximum	Wait before next instruction
Software-reset recovery	30 µs minimum	Wait before next command

Retain supply throughout a modifying cycle; power interruption can leave the affected data incomplete.

Variant and package distinctions

Read the exact part suffix and revision

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Q ordering option	QE=1 factory default	QE is writable; Standard and Dual commands still available
Pin3 / pin7	IO2 / IO3	Quad data lanes; not /WP and /HOLD on this reference
Separate hardware RESET	Absent on these eight-lead packages	Available on specified larger packages
SOIC option shown	SS, 208-mil body	5.28 × 5.28 mm nominal body
PDIP option shown	DA, 300-mil row format	2.54 mm pitch
Other offered package families	VSOP, WSON, XSON, SOIC16, TFBGA	Not interchangeable footprints; not all displayed here
Orderability	Check current manufacturer/distributor listing	This page identifies the source revision and selected package definitions

Do not blindly substitute another W25Q32 family or suffix.

Read the device identity

3.3 V host, mode 0, 1 MHz

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Supply and ground	VCC8 / GND4	3.3 V / common ground
SPI signals	CS1, DO2, DI5, CLK6	Host CS, MISO, MOSI, SCLK
Defined idle nets	10 kΩ pull-ups on CS, IO2 and IO3	IO2/IO3 unused by this standard-SPI example
Transmit bytes	9F 00 00 00	CS LOW for the complete transfer
Receive bytes	XX EF 40 16	Discard response during opcode
After transfer	CS HIGH	Data output releases
Interpretation	EF: Winbond; 40: type; 16: capacity code	Expected identification, not a measured live result

All logic is 3.3 V. Add level translation if the controller uses incompatible voltages.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Serial control2 pins

Data lanes4 pins

Ground1 pin

Supply1 pin

W25Q32JV working principle: illustrated functional stages, basic circuit and connections — Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Identify and address

The example sends 9F and reads manufacturer, memory-type and capacity identification bytes.

Step 2 / 3

Read the stored data

03 followed by a 24-bit address reads bytes sequentially. Faster instructions use different framing and dummy cycles.

Step 3 / 3

Update safely

Erase if needed, issue Write Enable for each modifying operation, program within a page and poll the status register.

W25Q32JV eight-pin circuit with four colored SPI signals,3.3V supply,100nF bypass and10k pullups. Ahost transmits9F000000 andexpects EF4016 identification. — Standard SPI identification example. The illustrated bytes are expected values, not a live measurement.

Connect it, step by step

Follow the component values and pin connections

Power and define idle state

Bypass VCC locally and keep CS HIGH through power-up.

Send the identification opcode

At 1 MHz mode0, transfer 9F and three dummy bytes under one CS LOW interval.

Read and deselect

Receive EF4016 after the opcode response, then raise CS.

Compact W25Q32JV functional cutaway with SPI command logic, status registers, page buffer, address decoder and NOR cell array. — Original functional illustration, not an exact transistor-level die layout.

Explore the circuit

Select a stage to see its role and connections

Decode the command

CS and CLK frame opcodes, addresses and data.

Locate the memory

Address decoders select the array location or erase unit.

Manage internal cycles

Program and erase logic sets BUSY until the internal cycle finishes.

Selected packagePDIP-8W25Q32JVDAIQ

Physical connections8 pinsPackage-specific numbering

Reference collection7 tables51 parameters & pin functions