Vlog [-R<simargs>]
Did any1 tried the vlog oprtion to simulate after the compilation
Vlog [-R<simargs>]
I tried to give the vsim options for the simargs but I could not get it done, It would be helpful if any1 could point out how to use this option for vlog efficently.
FPGA LVDS-receiver input capacitance
Hello,
I am currently designing a LVDS standard interface to drive a Virtex-6 FPGA with 1.25Gbps (DDR) and I would like to know if the corresponding values for the input capacitance of the LVDS-pins in the data-sheet or IBIS-file are valid? With a normal LVDS interface (I=3.5 mA and Rd=100 Ohm) it is to my mind not possible to drive 6-8pF single-ended input capacitance at 1.25Gbps. What do I misunderstand, because the data-sheet says that it is possible to drive the Virtex-6 at 1.25Gbps with a standard LVDS driver? Are the values right?
I´m grateful for any help regarding this topic.....
OFDM using system generator..
hi guys! i am currently working on implementation of channel equalizer for OFDM using xilinx system generator. But i have stuck at one point please help me out of this>
Problem is is that i want to implement 16 bit qam using xilinx blocksets.And i unable to define 16 bit qam using xilinx block .if anybody had done before this then please show me how you have done it...
LCD program.help in vhdl
Hi all !!
Currently i am working on LCD program in FPGA spartan 3. I am manage to display 16 bit data.
How can i able to display 32 bit data.
My question is "after completing 16 bit data whether i have to give next line address?But i am incrementing address by 1 at every time?My cursor or itself is not moving to the next line.how can be i able to do that?
please help regarding this.I am using VHDL language for coding.
4DSP development kit + Stellar IP tool
Dear all,
Can any body here help me in some things regarding 4DSP product. and Stellar IP software.
I am using in one of my project and need some assistance in some area.
If any one has experience of using this please let me know. I want to inquire something about STAR communication issue.
Xilinx Old school software "XACT" or "ViewLogic4"
Hey Folks,
I've run into a snag here....
I dug out the old school Xilinx "Xact" software boxes from storage, and I even found the hardware Dongle which was what I was most concerned about finding in order to revive this old software that came out in the early 90's.
Just looking to mess around with the Vintage stuff for fun! Do a few of the old tutorials i have on file.
:)
I then go to take out the XACT software Discs to set it all up... and I find a Windows Drivers Disc and a Printer driver disk in their place!!
NNNooooooooooo!!!
I guess whoever used it last here in my lab, didn't put the discs back and so I'm supper upset as I wanted to get this all setup and do a few Old school tutorials from back in the good old days of the Vintage Xilinx 2K devices.
I know this is probably a long shot......
but I'm wondering if there might be someone here that might still have a copy of this "XACT" or "Viewlogic" software lying around somewhere that I could get?
It seems we've lost all of our old School Xilinx stuff too.
A real bummer.
So if anyone can help......if you could send me a message.
That would be amazing!
Thanks folks,
FPGA based Modulation and Demodulation
hello friends...
please guide me how to go about this project "fpga based mod/demod".
i'll be using a spartan 3 fpga kit. and my modulation technique will be 'binary amplitude shift keying'.
what i intend in doing is ... i have two kits ...in one i'll be giving my message signal as input(now that message will be voice or text or something)
that message will be modulated after it passes from one kit and that modulated signal will be input to another kit which will demodulate it and give me the output.
i m new to vhdl and i m trying to learn it.
Loading .rbf file into EPCS16 for remote configuration of FPGA.
Hi all,
I am dealing with .rbf file, generated by Quartus II. I want to write the contents of rbf file into the EPCS flash using SPI interface. But the problem is that the .rbf file is encrypted and so I can't access the data though it. (Having rbf file loaded in flash, the FPGA can configure remotely). How can I see the contents of this encrypted .rbf file in binary or hex format?
In FIFO how Read / Write Pointer Functionality Happens ?
Hi every 1
here i have some doubts on FIFO read and write. please any1 knows tel me.
In FIFO how Read / Write Pointer Functionality Happens ? in the following cases ?
1. when fifo is in almost full and almost empty condition ?
2. when fifo is in full and empty ?
3. when fifo , program threshold value set to some value i.e 100 ?
4. fifo read EN / write En is HIGH , then what is the status of read/write pointers ?