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Vlog [-R<simargs>]
Did any1 tried the vlog oprtion to simulate after the compilation
Vlog [-R<simargs>]
I tried to give the vsim options for the simargs but I c ...
0
753
Outlook question help and information.
11:33 PM
FPGA LVDS-receiver input capacitance
Hello,
I am currently designing a LVDS standard interface to drive a Virtex-6 FPGA with 1.25Gbps (DDR) and I would like to know if the corresponding ...
0
753
OFDM using system generator..
hi guys! i am currently working on implementation of channel equalizer for OFDM using xilinx system generator. But i have stuck at one point please he ...
0
753
LCD program.help in vhdl
Hi all !!
Currently i am working on LCD program in FPGA spartan 3. I am manage to display 16 bit data.
How can i able to display 32 bit data.
My ques ...
0
753
4DSP development kit + Stellar IP tool
Dear all,
Can any body here help me in some things regarding 4DSP product. and Stellar IP software.
I am using in one of my project and need some ass ...
0
753
Xilinx Old school software "XACT" or "ViewLogic4"
Hey Folks,
I've run into a snag here....
I dug out the old school Xilinx "Xact" software boxes from storage, and I even found the hardware Dongle whi ...
1
753
VME controller configuration in FPGA
Friends,
I would like to configure VME controller in Vertex-6 FPGA. please share ur ideas to implement it.
0
753
FPGA based Modulation and Demodulation
hello friends...
please guide me how to go about this project "fpga based mod/demod".
i'll be using a spartan 3 fpga kit. and my modulation technique ...
0
753
Loading .rbf file into EPCS16 for remote configuration of FPGA.
Hi all,
I am dealing with .rbf file, generated by Quartus II. I want to write the contents of rbf file into the EPCS flash using SPI interface. But th ...
0
753
In FIFO how Read / Write Pointer Functionality Happens ?
Hi every 1
here i have some doubts on FIFO read and write. please any1 knows tel me.
In FIFO how Read / Write Pointer Functionality Happens ? in the ...
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753
Associate Engineer
Arduino Code Serial Communication
