Real View
A4988Microstepping DMOS driver
Control a bipolar stepper with STEP and DIR.
A4988 combines two DMOS H-bridges with a microstep translator for bipolar stepper motors. STEP pulses advance the phase-current sequence, DIR selects direction and three mode inputs choose full step through 1/16 microstepping. This page documents the bare 28-contact QFN IC, rather than assuming the wiring or sense resistors of a particular carrier board. A 12 V motor rail and 3.3 V logic supply feed the example; two 0.10 Ω sense resistors and a measured 0.8 V reference set a nominal 1 A full-scale limit. The physical pinout, original footprint and black 3D package match the Allegro ET drawing. Silver contacts surround the body; the exposed ground pad is included as contact 29. The internal diagram separates the translator, phase DACs, current chopping and bridge outputs.
Motor outputsEnable/reset/sleepGround and exposed padCharge pumpNo connectionSuppliesResolution selectionCurrent timingSTEP/DIRCurrent referenceCurrent sensing
A4988SETTR-TQFN-28 + EPTop view · EP shown through body
Click a lead or use the arrow keys. Top view · EP shown through body
PIN 1 · Motor outputs
Bridge 2 output BOUT2B
Function
Switched output for one end of the second winding.
How to connect
Connect the other end of this winding to OUT2A (pin 26).
PIN 2 · Enable/reset/sleep
Active-LOW output enablenENABLE
Function
LOW permits the output bridges to drive; HIGH disables their MOSFETs.
How to connect
Tie LOW for the simple example or drive from a defined controller output.
Electrical note
The translator remains active and still accepts STEP while outputs are disabled.
PIN 3 · Ground and exposed pad
Device groundGND
Function
First ground contact.
How to connect
Join GND (pin 18) and the exposed-pad ground plane.
PIN 4 · Charge pump
Charge-pump flying capacitorCP1
Function
First connection of the high-side gate-drive pump capacitor.
How to connect
Connect 100 nF ceramic directly to CP2 pin 5.
Electrical note
Use suitable voltage rating and Class 2 dielectric stability; neither end is GND.
PIN 5 · Charge pump
Charge-pump flying capacitorCP2
Function
Second flying-capacitor terminal.
How to connect
Connect to the other end of the CP1 capacitor.
PIN 6 · Charge pump
Charge-pump reservoirVCP
Function
Boosted voltage for high-side gate drive.
How to connect
Connect 100 nF ceramic between VCP and VBB.
Electrical note
The reservoir returns to the motor rail, not to ground.
PIN 7 · No connection
No connectionNC
Function
Unassigned package contact.
How to connect
Leave open.
PIN 8 · Supplies
Internal regulator bypassVREG
Function
Internal approximately 7 V supply used by the low-side gate drivers.
How to connect
Connect 220 nF ceramic to GND.
Electrical note
This is a bypass node; do not use it as a general-purpose external supply.
PIN 9 · Resolution selection
Microstep select 1MS1
Function
First step-resolution input.
How to connect
Ground for full step.
Electrical note
Internal 100 kΩ pulldown; use the exact MS1/MS2/MS3 table.
PIN 10 · Resolution selection
Microstep select 2MS2
Function
Second step-resolution input.
How to connect
Ground for full step.
Electrical note
Internal 50 kΩ pulldown.
PIN 11 · Resolution selection
Microstep select 3MS3
Function
Third step-resolution input.
How to connect
Ground for full step.
Electrical note
Internal 100 kΩ pulldown. This device supports up to 1/16, not 1/32.
PIN 12 · Enable/reset/sleep
Active-LOW translator resetnRESET
Function
LOW selects the electrical home state and turns off all outputs.
How to connect
Drive HIGH for normal operation.
Electrical note
STEP is ignored until reset is released.
PIN 13 · Current timing
Current-regulator off-time settingROSC
Function
Sets fixed off-time and influences decay selection.
How to connect
Use 24.9 kΩ to GND for approximately 30.2 µs off-time.
Electrical note
tOFF[µs]≈ROSC[Ω]/825; this is not the external STEP period.
PIN 14 · Enable/reset/sleep
Active-LOW sleepnSLEEP
Function
LOW powers down the bridges, current regulator and charge pump.
How to connect
Drive HIGH and allow 1 ms before STEP.
Electrical note
Define the level; do not assume a carrier-board pull-up exists on the bare IC.
PIN 15 · Supplies
Logic supplyVDD
Function
Powers translator and logic interface.
How to connect
Use 3.3 V with 220 nF local bypass in the example.
Electrical note
Operating range 3–5.5 V; logic thresholds track VDD.
PIN 16 · STEP/DIR
Step commandSTEP
Function
A rising edge advances the translator one selected increment.
How to connect
Use controller pulses with at least 1 µs HIGH and 1 µs LOW.
Electrical note
Meet 200 ns setup/hold for the other sampled controls.
PIN 17 · Current reference
Winding-current referenceREF
Function
Analog input setting the full-scale current comparator level.
How to connect
Set and measure 0.8 V for a nominal 1 A limit with 0.10 Ω sense resistors.
Electrical note
ITRIPMAX=VREF/(8×RSENSE); use the actual sense resistance, not a carrier-board rule of thumb.
PIN 18 · Ground and exposed pad
Device groundGND
Function
Second ground contact.
How to connect
Connect to GND (pin 3) and the exposed-pad ground plane.
PIN 19 · STEP/DIR
Sequence directionDIR
Function
Sets translator sequence direction at the next STEP edge.
How to connect
Connect to a defined controller output.
Electrical note
Direction does not establish an absolute shaft position.
PIN 20 · No connection
No connectionNC
Function
Unassigned contact.
How to connect
Leave open.
PIN 21 · Motor outputs
Bridge 1 output BOUT1B
Function
One end of the first motor winding.
How to connect
Connect winding 1 between OUT1B (pin 21) and OUT1A (pin 24).
PIN 22 · Supplies
Bridge 1 motor supplyVBB1
Function
Motor supply input for bridge 1.
How to connect
Join VBB2 to the 12 V example motor rail, with local and bulk bypass.
Electrical note
Operating 8–35 V; keep transients below device limits.
PIN 23 · Current sensing
Bridge 1 current returnSENSE1
Function
Current-sense return for the first winding.
How to connect
Connect a separate 0.10 Ω resistor to the common ground.
Electrical note
Sense voltage must not exceed the 0.5 V absolute limit.
PIN 24 · Motor outputs
Bridge 1 output AOUT1A
Function
Other end of winding 1.
How to connect
Connect to the motor lead paired with OUT1B (pin 21).
PIN 25 · No connection
No connectionNC
Function
Unassigned contact.
How to connect
Leave open.
PIN 26 · Motor outputs
Bridge 2 output AOUT2A
Function
Other end of winding 2.
How to connect
Connect winding 2 between OUT2A (pin 26) and OUT2B (pin 1).
PIN 27 · Current sensing
Bridge 2 current returnSENSE2
Function
Current-sense return for the second winding.
How to connect
Use a separate 0.10 Ω resistor to ground with Kelvin sense routing.
PIN 28 · Supplies
Bridge 2 motor supplyVBB2
Function
Motor supply input for bridge 2.
How to connect
Join VBB1 and the 12 V motor rail.
PIN 29 · Ground and exposed pad
Exposed ground/thermal padEP
Function
Underside pad carries heat into the PCB ground plane.
How to connect
Solder to ground and join both GND pins externally.
Electrical note
Contact 29 is the page/export number; the manufacturer identifies this contact as PAD.
At a glance
Microstepping DMOS driver
The translator selects a phase-current pair. Two DACs and sense comparators regulate the bridges with fixed off-time chopping and automatic decay selection.
8–35 VMotor supply
3–5.5 VLogic supply
1/16 of a full stepFinest microstep
−20–85 °COperating ambient
Operating profile
A4988SETTR-T
Power and input levels
Key parameters and their test conditions
- VBB motor rail
- 8–35 VConditions / notes: Use 12 V in the example and allow for transients
- VDD logic rail
- 3–5.5 VConditions / notes: Use 3.3 V with matching controller logic
- Logic HIGH / LOW
- ≥0.7×VDD / ≤0.3×VDDConditions / notes: At 3.3 V:≥2.31 V / ≤0.99 V
- Reference input
- 0–4 V operatingConditions / notes: The 5.5 V absolute rating is not the operating range
- Ambient range
- −20–85°CConditions / notes: Selected S-grade part
- Junction maximum
- 150°CConditions / notes: Do not use thermal shutdown as an operating target
Package details
Follows the selected physical package
- Manufacturer
- Allegro MicroSystems
- Part number
- A4988SETTR-T
- Package
- QFN-28 + EP
- Connections
- 29 pins
- Mounting
- SMD
- Lead pitch
- 0.50 mm
- Package code
- ET
- Thermal reference
- −20 to 85 °C ambient; board-dependent current
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Motor outputs4 pins
Enable/reset/sleep3 pins
Ground and exposed pad3 pins
Charge pump3 pins
No connection3 pins
Supplies4 pins
Resolution selection3 pins
Current timing1 pins
STEP/DIR2 pins
Current reference1 pins
Current sensing2 pins
Select a step
STEP rising edges advance the translator. The MS inputs choose resolution and DIR sets the sequence direction.
Set both current targets
Each DAC scales the common REF input for its phase position.
Chop and recirculate
A sense comparator terminates drive at the target, followed by slow or mixed decay for the fixed off-time.
ITRIPMAX=VREF/(8×RSENSE). At 0.8 V and 0.10 Ω, the nominal limit is 1 A. Full-step phase targets are approximately 70.71% of that value.
Pin reference
Select a pin to explore its function and connection.
29 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| OUT2B | Bridge 2 output B | Switched output for one end of the second winding. | |
| nENABLE | Active-LOW output enable | LOW permits the output bridges to drive; HIGH disables their MOSFETs. | |
| GND | Device ground | First ground contact. | |
| CP1 | Charge-pump flying capacitor | First connection of the high-side gate-drive pump capacitor. | |
| CP2 | Charge-pump flying capacitor | Second flying-capacitor terminal. | |
| VCP | Charge-pump reservoir | Boosted voltage for high-side gate drive. | |
| NC | No connection | Unassigned package contact. | |
| VREG | Internal regulator bypass | Internal approximately 7 V supply used by the low-side gate drivers. | |
| MS1 | Microstep select 1 | First step-resolution input. | |
| MS2 | Microstep select 2 | Second step-resolution input. | |
| MS3 | Microstep select 3 | Third step-resolution input. | |
| nRESET | Active-LOW translator reset | LOW selects the electrical home state and turns off all outputs. | |
| ROSC | Current-regulator off-time setting | Sets fixed off-time and influences decay selection. | |
| nSLEEP | Active-LOW sleep | LOW powers down the bridges, current regulator and charge pump. | |
| VDD | Logic supply | Powers translator and logic interface. | |
| STEP | Step command | A rising edge advances the translator one selected increment. | |
| REF | Winding-current reference | Analog input setting the full-scale current comparator level. | |
| GND | Device ground | Second ground contact. | |
| DIR | Sequence direction | Sets translator sequence direction at the next STEP edge. | |
| NC | No connection | Unassigned contact. | |
| OUT1B | Bridge 1 output B | One end of the first motor winding. | |
| VBB1 | Bridge 1 motor supply | Motor supply input for bridge 1. | |
| SENSE1 | Bridge 1 current return | Current-sense return for the first winding. | |
| OUT1A | Bridge 1 output A | Other end of winding 1. | |
| NC | No connection | Unassigned contact. | |
| OUT2A | Bridge 2 output A | Other end of winding 2. | |
| SENSE2 | Bridge 2 current return | Current-sense return for the second winding. | |
| VBB2 | Bridge 2 motor supply | Motor supply input for bridge 2. | |
| EP | Exposed ground/thermal pad | Underside pad carries heat into the PCB ground plane. |
No pins match. Try a signal name or choose All pins.
Power and input levels
Operating limits are distinct from package headline current
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| VBB motor rail | 8–35 V | Use 12 V in the example and allow for transients |
| VDD logic rail | 3–5.5 V | Use 3.3 V with matching controller logic |
| Logic HIGH / LOW | ≥0.7×VDD / ≤0.3×VDD | At 3.3 V:≥2.31 V / ≤0.99 V |
| Reference input | 0–4 V operating | The 5.5 V absolute rating is not the operating range |
| Ambient range | −20–85°C | Selected S-grade part |
| Junction maximum | 150°C | Do not use thermal shutdown as an operating target |
| Output-current absolute rating | ±2 A | Check PCB cooling, conduction and switching loss |
| Motor/logic sleep currents | 10 µA maximum each | Stated sleep conditions |
No specifications match. Try a parameter name or a unit.
Electrical-table values use 25 °C and 35 V unless otherwise specified.
STEP and startup timing
Control edges and current chopping are different clocks
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| STEP HIGH / LOW pulse | At least 1 µs / 1 µs | Logic-interface timing diagram |
| Command setup / hold | 200 ns / 200 ns | MS inputs, reset and direction around STEP rising |
| Sleep release delay | 1 ms | Let the charge pump stabilize before STEP |
| ROSC resistor example | 24.9 kΩ | About 30.2 µs nominal off-time |
| Off-time estimate | tOFF[µs]≈ROSC[Ω]/825 | An off-time, not a fixed PWM or motor-step frequency |
| Blanking time | 0.7 / 1.0 / 1.3 µs | Minimum / typical / maximum |
| At 1 kHz full step | 300 rpm ideal | 200-full-step/revolution motor, without missed steps |
No specifications match. Try a parameter name or a unit.
Use practical pulse margins, acceleration and a motor torque budget.
Microstep selection
MS1 · MS2 · MS3
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| LOW LOW LOW | Full step | Two-phase excitation, 70.71% phase-current targets |
| HIGH LOW LOW | 1/2 step | 400 pulses/rev for a 200-step motor |
| LOW HIGH LOW | 1/4 step | 800 pulses/rev |
| HIGH HIGH LOW | 1/8 step | 1600 pulses/rev |
| HIGH HIGH HIGH | 1/16 step | 3200 pulses/rev |
| Other combinations | Not specified here | Use a documented combination rather than guessing |
| At 1 kHz, full / 1/16 | 300 / 18.75 rpm ideal | Same assumed 200-step motor |
| MS1/MS2/MS3 pulldowns | 100/50/100 kΩ typical | Only these documented pulls are assumed |
No specifications match. Try a parameter name or a unit.
Microstep resolution does not guarantee equivalent mechanical accuracy.
Current setting and heat
Use the actual resistor fitted to the board
Manufacturer specifications 9 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Full-scale current | ITRIPMAX=VREF/(8×RSENSE) | Reference in volts, resistance in ohms |
| Example | 0.8 V /(8×0.10 Ω)=1.0 A | Set REF before enabling the motor |
| Full-step phase targets | Approximately 0.707 A each | Not 1 A simultaneously in both phases |
| Sense-resistor heat at 1 A | I²R=0.10 W | Use ≥0.25 W parts here with appropriate pulse/thermal margin |
| Sense voltage absolute limit | 0.5 V | Includes transients |
| Current-trip error at 70.71/100% | ±5% | At VREF=2 V; do not promise this tolerance for every setting |
| Source/sink on-resistance | 320 mΩ typical each | At ±1.5 A, stated test conditions |
| One 1 A current path estimate | 0.64 W conduction | Two typical MOSFETs; temperature and switching increase loss |
| θJA reference | 32°C/W | Four-layer JEDEC board, not any carrier board |
No specifications match. Try a parameter name or a unit.
Reference accuracy, resistor tolerance, blanking, winding dynamics and heat affect actual current.
Output control and decay
ENABLE does not freeze the translator
Manufacturer specifications 10 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| nENABLE HIGH | Outputs off; translator active | STEP still advances the internal sequence |
| nENABLE LOW | Outputs enabled | Normal defined output drive |
| nRESET LOW | Home state; outputs off | STEP ignored until reset is HIGH |
| nSLEEP LOW | Low-power sleep | Current regulator and pump also disabled |
| ROSC resistor or tied VDD | Automatic decay selection | Full step uses slow decay; fractional stepping follows DAC transitions |
| ROSC tied GND | Mixed decay on rising/falling currents | Fixed 30 µs nominal off-time |
| Mixed-decay division | 31.25% fast, then slow | Percentage of the off-time |
| Thermal shutdown/hysteresis | 165 °C / 15 °C typical | Protection thresholds exceed the normal junction limit |
| VDD UVLO rising | 2.7 / 2.8 / 2.9 V | Minimum/typical/maximum |
| Fault indication | No dedicated fault output | Do not invent a DRV8825-style nFAULT pin |
No specifications match. Try a parameter name or a unit.
After a short-to-ground fault, follow the manufacturer sleep/power-reset recovery sequence after correcting the cause.
12 V motor / 3.3 V logic wiring
Bare-QFN support components are included
Manufacturer specifications 11 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| VBB1=22,VBB2=28 | Common 12 V rail | Local 100 nF ceramics plus appropriate bulk capacitance |
| VDD15 | 3.3 V with 220 nF local bypass | Controller uses the same logic-voltage domain |
| CP1=4 to CP2=5 | 100 nF ceramic | Flying capacitor; neither end grounded |
| VCP (pin 6) to VBB | 100 nF ceramic | Pump reservoir returns to motor rail |
| VREG8 | 220 nF to GND | Internal approximately 7 V bypass node |
| REF17 | Measure 0.8 V | Set with a lightly loaded divider/potentiometer; limit before enabling |
| SENSE1=23,SENSE2=27 | Separate 0.10 Ω resistors | Common ground with Kelvin sensing |
| Winding 1 / 2 | OUT1A (pin 24)–OUT1B (pin 21) / OUT2A (pin 26)–OUT2B (pin 1) | Check the actual motor winding pairs |
| Control | STEP (pin 16), DIR (pin 19), RESET (pin 12), SLEEP (pin 14) | Keep reset/sleep HIGH; enable pin 2 LOW |
| Full step and off-time | MS1=9, MS2=10, MS3=11 LOW; ROSC (pin 13) via 24.9 kΩ to GND | No undocumented pull-ups assumed |
| Ground/unused | GND (pin 3), GND (pin 18), EP grounded; NC7,20,25 open | EP29 is a grounded thermal pad |
No specifications match. Try a parameter name or a unit.
This is an educational board-level circuit, not a claim that all carrier modules have these resistor values.
QFN package and PCB
Original ET drawing with exposed ground contact
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Molded body | 5×5×0.90 mm nominal | QFN28, ET package |
| Signal contacts | 28 at 0.50 mm pitch | Seven on each edge |
| Underside exposed pad | 3.15×3.15 mm | Ground; contact 29 in this page/export |
| Perimeter copper lands | 0.30×1.15 mm | 4.80 mm row-center spacing |
| Contact finish | Matte tin-plated leadframe | Silver contacts, not long gull-wing leads |
| Footprint download | KiCad .kicad_mod | Add thermals, vias and assembly-specific paste/mask |
| Top-view orientation | Pin 1 upper left; counterclockwise numbering | The center EP is shown through the body for selection |
| Orderable reference | A4988SETTR-T | Bare IC; carrier-board connectors are not the IC pinout |
No specifications match. Try a parameter name or a unit.
Review the actual package and assembly process before manufacturing.
Small positioning axes
Coordinate STEP pulses with acceleration, limits and homing.
Manufacturer application guidePrinter/extruder mechanisms
Set current for the winding and cooling available on the board.
Manufacturer application guideStepper experiments
Compare full-step and microstep commands while observing current and motor motion.
Manufacturer application guideTake it into ProTech
Find A4988 in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech