ATSAML10D15A peripherals

Each block of the ATSAML10D15A: what it is, the registers that control it and the pins it uses.

PORT

PORT

Port Module

Registers

EIC

EIC

External Interrupt Controller

Registers

Pins

TC0

TC

Basic Timer Counter

Registers

Pins

TC1

TC

Basic Timer Counter

Registers

Pins

TC2

TC

Basic Timer Counter

Registers

Pins

SERCOM0

SERCOM

Serial Communication Interface

Registers

I2CM.CTRLA0x42000400I2CS.CTRLA0x42000400SPIM.CTRLA0x42000400SPIS.CTRLA0x42000400USART_EXT.CTRLA0x42000400USART_INT.CTRLA0x42000400I2CM.CTRLB0x42000404I2CS.CTRLB0x42000404SPIM.CTRLB0x42000404SPIS.CTRLB0x42000404USART_EXT.CTRLB0x42000404USART_INT.CTRLB0x42000404USART_EXT.CTRLC0x42000408USART_INT.CTRLC0x42000408I2CM.BAUD0x4200040CSPIM.BAUD0x4200040CSPIS.BAUD0x4200040CUSART_EXT.BAUD0x4200040CUSART_INT.BAUD0x4200040CUSART_EXT.RXPL0x4200040EUSART_INT.RXPL0x4200040EI2CM.INTENCLR0x42000414I2CS.INTENCLR0x42000414SPIM.INTENCLR0x42000414SPIS.INTENCLR0x42000414USART_EXT.INTENCLR0x42000414USART_INT.INTENCLR0x42000414I2CM.INTENSET0x42000416I2CS.INTENSET0x42000416SPIM.INTENSET0x42000416SPIS.INTENSET0x42000416USART_EXT.INTENSET0x42000416USART_INT.INTENSET0x42000416I2CM.INTFLAG0x42000418I2CS.INTFLAG0x42000418SPIM.INTFLAG0x42000418SPIS.INTFLAG0x42000418USART_EXT.INTFLAG0x42000418USART_INT.INTFLAG0x42000418I2CM.STATUS0x4200041AI2CS.STATUS0x4200041ASPIM.STATUS0x4200041ASPIS.STATUS0x4200041AUSART_EXT.STATUS0x4200041AUSART_INT.STATUS0x4200041AI2CM.SYNCBUSY0x4200041CI2CS.SYNCBUSY0x4200041CSPIM.SYNCBUSY0x4200041CSPIS.SYNCBUSY0x4200041CUSART_EXT.SYNCBUSY0x4200041CUSART_INT.SYNCBUSY0x4200041CUSART_EXT.RXERRCNT0x42000420USART_INT.RXERRCNT0x42000420I2CM.ADDR0x42000424I2CS.ADDR0x42000424SPIM.ADDR0x42000424SPIS.ADDR0x42000424I2CM.DATA0x42000428I2CS.DATA0x42000428SPIM.DATA0x42000428SPIS.DATA0x42000428USART_EXT.DATA0x42000428USART_INT.DATA0x42000428I2CM.DBGCTRL0x42000430SPIM.DBGCTRL0x42000430SPIS.DBGCTRL0x42000430USART_EXT.DBGCTRL0x42000430USART_INT.DBGCTRL0x42000430

Pins

SERCOM1

SERCOM

Serial Communication Interface

Registers

I2CM.CTRLA0x42000800I2CS.CTRLA0x42000800SPIM.CTRLA0x42000800SPIS.CTRLA0x42000800USART_EXT.CTRLA0x42000800USART_INT.CTRLA0x42000800I2CM.CTRLB0x42000804I2CS.CTRLB0x42000804SPIM.CTRLB0x42000804SPIS.CTRLB0x42000804USART_EXT.CTRLB0x42000804USART_INT.CTRLB0x42000804USART_EXT.CTRLC0x42000808USART_INT.CTRLC0x42000808I2CM.BAUD0x4200080CSPIM.BAUD0x4200080CSPIS.BAUD0x4200080CUSART_EXT.BAUD0x4200080CUSART_INT.BAUD0x4200080CUSART_EXT.RXPL0x4200080EUSART_INT.RXPL0x4200080EI2CM.INTENCLR0x42000814I2CS.INTENCLR0x42000814SPIM.INTENCLR0x42000814SPIS.INTENCLR0x42000814USART_EXT.INTENCLR0x42000814USART_INT.INTENCLR0x42000814I2CM.INTENSET0x42000816I2CS.INTENSET0x42000816SPIM.INTENSET0x42000816SPIS.INTENSET0x42000816USART_EXT.INTENSET0x42000816USART_INT.INTENSET0x42000816I2CM.INTFLAG0x42000818I2CS.INTFLAG0x42000818SPIM.INTFLAG0x42000818SPIS.INTFLAG0x42000818USART_EXT.INTFLAG0x42000818USART_INT.INTFLAG0x42000818I2CM.STATUS0x4200081AI2CS.STATUS0x4200081ASPIM.STATUS0x4200081ASPIS.STATUS0x4200081AUSART_EXT.STATUS0x4200081AUSART_INT.STATUS0x4200081AI2CM.SYNCBUSY0x4200081CI2CS.SYNCBUSY0x4200081CSPIM.SYNCBUSY0x4200081CSPIS.SYNCBUSY0x4200081CUSART_EXT.SYNCBUSY0x4200081CUSART_INT.SYNCBUSY0x4200081CUSART_EXT.RXERRCNT0x42000820USART_INT.RXERRCNT0x42000820I2CM.ADDR0x42000824I2CS.ADDR0x42000824SPIM.ADDR0x42000824SPIS.ADDR0x42000824I2CM.DATA0x42000828I2CS.DATA0x42000828SPIM.DATA0x42000828SPIS.DATA0x42000828USART_EXT.DATA0x42000828USART_INT.DATA0x42000828I2CM.DBGCTRL0x42000830SPIM.DBGCTRL0x42000830SPIS.DBGCTRL0x42000830USART_EXT.DBGCTRL0x42000830USART_INT.DBGCTRL0x42000830

Pins

DSU

DSU

Device Service Unit

Registers

DWT

DWT

Data Watchpoint and Trace

Registers

EVSYS

EVSYS

Event System Interface

Registers

CTRLA0x42000000SWEVT0x42000004PRICTRL0x42000008INTPEND0x42000010INTSTATUS0x42000014BUSYCH0x42000018READYUSR0x4200001CCHANNEL0.CHANNEL0x42000020CHANNEL0.CHINTENCLR0x42000024CHANNEL0.CHINTENSET0x42000025CHANNEL0.CHINTFLAG0x42000026CHANNEL0.CHSTATUS0x42000027CHANNEL1.CHANNEL0x42000028CHANNEL1.CHINTENCLR0x4200002CCHANNEL1.CHINTENSET0x4200002DCHANNEL1.CHINTFLAG0x4200002ECHANNEL1.CHSTATUS0x4200002FCHANNEL2.CHANNEL0x42000030CHANNEL2.CHINTENCLR0x42000034CHANNEL2.CHINTENSET0x42000035CHANNEL2.CHINTFLAG0x42000036CHANNEL2.CHSTATUS0x42000037CHANNEL3.CHANNEL0x42000038CHANNEL3.CHINTENCLR0x4200003CCHANNEL3.CHINTENSET0x4200003DCHANNEL3.CHINTFLAG0x4200003ECHANNEL3.CHSTATUS0x4200003FCHANNEL4.CHANNEL0x42000040CHANNEL4.CHINTENCLR0x42000044CHANNEL4.CHINTENSET0x42000045CHANNEL4.CHINTFLAG0x42000046CHANNEL4.CHSTATUS0x42000047CHANNEL5.CHANNEL0x42000048CHANNEL5.CHINTENCLR0x4200004CCHANNEL5.CHINTENSET0x4200004DCHANNEL5.CHINTFLAG0x4200004ECHANNEL5.CHSTATUS0x4200004FCHANNEL6.CHANNEL0x42000050CHANNEL6.CHINTENCLR0x42000054CHANNEL6.CHINTENSET0x42000055CHANNEL6.CHINTFLAG0x42000056CHANNEL6.CHSTATUS0x42000057CHANNEL7.CHANNEL0x42000058CHANNEL7.CHINTENCLR0x4200005CCHANNEL7.CHINTENSET0x4200005DCHANNEL7.CHINTFLAG0x4200005ECHANNEL7.CHSTATUS0x4200005FUSER00x42000120USER10x42000121USER20x42000122USER30x42000123USER40x42000124USER50x42000125USER60x42000126USER70x42000127USER80x42000128USER90x42000129USER100x4200012AUSER110x4200012BUSER120x4200012CUSER130x4200012DUSER140x4200012EUSER150x4200012FUSER160x42000130USER170x42000131USER180x42000132USER190x42000133USER200x42000134USER210x42000135USER220x42000136INTENCLR0x420001D4INTENSET0x420001D5INTFLAG0x420001D6NONSECCHAN0x420001D8NSCHKCHAN0x420001DCNONSECUSER0x420001E0NSCHKUSER0x420001F0

GCLK

GCLK

Generic Clock Generator

Registers

Pins

IDAU

IDAU

Implementation Defined Attribution Unit

NVIC

NVIC

Nested Vectored Interrupt Controller

Registers

PTC

PTC

Peripheral Touch Controller

Pins

RTC

RTC

Real-Time Counter

Registers

Pins

TRAM

TRAM

TrustRAM

Registers