ATtiny13 fuses & lock bits
The fuse bytes set the clock, start-up, brown-out and boot options; the lock bits protect flash and EEPROM. A fuse bit is programmed at 0 . Change a setting and the byte below updates; the starting values are the factory defaults.
SPIEN Serial program downloading (SPI) enabled 1 · unprogrammed 0 · programmed EESAVE Preserve EEPROM through the Chip Erase cycle 1 · unprogrammed 0 · programmed WDTON Watch-dog Timer always on 1 · unprogrammed 0 · programmed CKDIV8 Divide clock by 8 internally 1 · unprogrammed 0 · programmed SUT_CKSEL Select Clock Source Ext. Clock; Start-up time: 14 CK + 0 ms Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 0 ms Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 0 ms Int. RC Osc. 128 kHz; Start-up time: 14 CK + 0 ms Ext. Clock; Start-up time: 14 CK + 4 ms Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 4 ms Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 4 ms Int. RC Osc. 128 kHz; Start-up time: 14 CK + 4 ms Ext. Clock; Start-up time: 14 CK + 64 ms Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 64 ms Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 64 ms Int. RC Osc. 128 kHz; Start-up time: 14 CK + 64 ms HIGH fuse 0xFF default 0xFF SELFPRGEN Self Programming enable 1 · unprogrammed 0 · programmed DWEN Debug Wire enable 1 · unprogrammed 0 · programmed BODLEVEL Enable BOD and select level Brown-out detection at VCC=4.3 V Brown-out detection at VCC=2.7 V Brown-out detection at VCC=1.8 V Brown-out detection disabled RSTDISBL Reset Disabled (Enable PB5 as i/o pin) 1 · unprogrammed 0 · programmed Lock bits 0xFF default 0xFF LB Memory Lock Further programming and verification disabled Further programming disabled No memory lock features enabled