ATtiny13 registers
All 35 registers by peripheral, at their data-space address (the I/O address IN and OUT use is shown beside it), with their reset value and every bit.
AC Analog Comparator
ADCSRBADC Control and Status Register B
- Address
0x23 I/O 0x03
- Reset
0x00
- Access
- read/write
- 7–
- 6ACME
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
1 field
| Field | Bits | What it does |
|---|
| ACME | 6 | Analog Comparator Multiplexer Enable |
ACSRAnalog Comparator Control And Status Register
- Address
0x28 I/O 0x08
- Reset
0x00
- Access
- read/write
- 7ACD
- 6ACBG
- 5ACO
- 4ACI
- 3ACIE
- 2–
- 1ACIS1
- 0ACIS0
6 fields
| Field | Bits | What it does |
|---|
| ACD | 7 | Analog Comparator Disable |
| ACBG | 6 | Analog Comparator Bandgap Select |
| ACO | 5 | Analog Compare Output |
| ACI | 4 | Analog Comparator Interrupt Flag |
| ACIE | 3 | Analog Comparator Interrupt Enable |
| ACIS | 1:0 | Analog Comparator Interrupt Mode Select bits0 Interrupt on Toggle1 Reserved2 Interrupt on Falling Edge3 Interrupt on Rising Edge
|
DIDR0
- Address
0x34 I/O 0x14
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1AIN1D
- 0AIN0D
2 fields
| Field | Bits | What it does |
|---|
| AIN1D | 1 | AIN1 Digital Input Disable |
| AIN0D | 0 | AIN0 Digital Input Disable |
ADC Analog-to-Digital Converter
ADCSRBADC Control and Status Register B
- Address
0x23 I/O 0x03
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2ADTS2
- 1ADTS1
- 0ADTS0
1 field
| Field | Bits | What it does |
|---|
| ADTS | 2:0 | ADC Auto Trigger Sources0 Free Running mode1 Analog Comparator2 External Interrupt Request 03 Timer/Counter0 Compare Match A4 Timer/Counter0 Overflow5 Timer/Counter1 Compare Match B6 Timer/Counter1 Overflow7 Timer/Counter1 Capture Event
|
ADCADC Data Register Bytes
- Address
0x24 I/O 0x04
- Reset
0x0000
- Access
- read/write
- Size
- 16-bit
ADCSRAThe ADC Control and Status register
- Address
0x26 I/O 0x06
- Reset
0x00
- Access
- read/write
- 7ADEN
- 6ADSC
- 5ADATE
- 4ADIF
- 3ADIE
- 2ADPS2
- 1ADPS1
- 0ADPS0
6 fields
| Field | Bits | What it does |
|---|
| ADEN | 7 | ADC Enable |
| ADSC | 6 | ADC Start Conversion |
| ADATE | 5 | ADC Auto Trigger Enable |
| ADIF | 4 | ADC Interrupt Flag |
| ADIE | 3 | ADC Interrupt Enable |
| ADPS | 2:0 | ADC Prescaler Select Bits0 21 22 43 84 165 326 647 128
|
ADMUXThe ADC multiplexer Selection Register
- Address
0x27 I/O 0x07
- Reset
0x00
- Access
- read/write
- 7–
- 6REFS0
- 5ADLAR
- 4–
- 3–
- 2–
- 1MUX1
- 0MUX0
3 fields
| Field | Bits | What it does |
|---|
| REFS0 | 6 | Reference Selection Bit 0 |
| ADLAR | 5 | Left Adjust Result |
| MUX | 1:0 | Analog Channel and Gain Selection Bits |
DIDR0Digital Input Disable Register 0
- Address
0x34 I/O 0x14
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5ADC0D
- 4ADC2D
- 3ADC3D
- 2ADC1D
- 1–
- 0–
4 fields
| Field | Bits | What it does |
|---|
| ADC0D | 5 | ADC0 Digital input Disable |
| ADC2D | 4 | ADC2 Digital input Disable |
| ADC3D | 3 | ADC3 Digital input Disable |
| ADC1D | 2 | ADC2 Digital input Disable |
EXINT External Interrupts
PCMSKPin Change Enable Mask
- Address
0x35 I/O 0x15
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
MCUCRMCU Control Register
- Address
0x55 I/O 0x35
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1ISC01
- 0ISC00
2 fields
| Field | Bits | What it does |
|---|
| ISC01 | 1 | Interrupt Sense Control 0 Bit 1 |
| ISC00 | 0 | Interrupt Sense Control 0 Bit 00 Low Level of INTX1 Any Logical Change of INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
GIFRGeneral Interrupt Flag register
- Address
0x5A I/O 0x3A
- Reset
0x00
- Access
- read/write
- 7–
- 6INTF0
- 5PCIF
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| INTF0 | 6 | External Interrupt Flag 0 |
| PCIF | 5 | Pin Change Interrupt Flag |
GIMSKGeneral Interrupt Mask Register
- Address
0x5B I/O 0x3B
- Reset
0x00
- Access
- read/write
- 7–
- 6INT0
- 5PCIE
- 4–
- 3–
- 2–
- 1–
- 0–
2 fields
| Field | Bits | What it does |
|---|
| INT0 | 6 | External Interrupt Request 0 Enable |
| PCIE | 5 | Pin Change Interrupt Enable |
PORTB I/O Port
PINBInput Pins, Port B
- Address
0x36 I/O 0x16
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5PINB5
- 4PINB4
- 3PINB3
- 2PINB2
- 1PINB1
- 0PINB0
DDRBData Direction Register, Port B
- Address
0x37 I/O 0x17
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5DDB5
- 4DDB4
- 3DDB3
- 2DDB2
- 1DDB1
- 0DDB0
PORTBData Register, Port B
- Address
0x38 I/O 0x18
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5PORTB5
- 4PORTB4
- 3PORTB3
- 2PORTB2
- 1PORTB1
- 0PORTB0
EEPROM EEPROM
EECREEPROM Control Register
- Address
0x3C I/O 0x1C
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5EEPM1
- 4EEPM0
- 3EERIE
- 2EEMWE
- 1EEWE
- 0EERE
5 fields
| Field | Bits | What it does |
|---|
| EEPM | 5:4 | 0 Erase and Write in one operation1 Erase Only2 Write Only
|
| EERIE | 3 | EEProm Ready Interrupt Enable |
| EEMWE | 2 | EEPROM Master Write Enable |
| EEWE | 1 | EEPROM Write Enable |
| EERE | 0 | EEPROM Read Enable |
EEDREEPROM Data Register
- Address
0x3D I/O 0x1D
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
EEAREEPROM Read/Write Access
- Address
0x3E I/O 0x1E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
WDT Watchdog Timer
WDTCRWatchdog Timer Control Register
- Address
0x41 I/O 0x21
- Reset
0x00
- Access
- read/write
- 7WDTIF
- 6WDTIE
- 5WDP5
- 4WDCE
- 3WDE
- 2WDP2
- 1WDP1
- 0WDP0
5 fields
| Field | Bits | What it does |
|---|
| WDTIF | 7 | Watchdog Timeout Interrupt Flag |
| WDTIE | 6 | Watchdog Timeout Interrupt Enable |
| WDP | 5,2,1,0 | Watchdog Timer Prescaler Bits0 Oscillator Cycles 2K1 Oscillator Cycles 4K2 Oscillator Cycles 8K3 Oscillator Cycles 16K4 Oscillator Cycles 32K5 Oscillator Cycles 64K6 Oscillator Cycles 128K7 Oscillator Cycles 256K8 Oscillator Cycles 512K9 Oscillator Cycles 1024K
|
| WDCE | 4 | Watchdog Change Enable |
| WDE | 3 | Watch Dog Enable |
CPU CPU Registers
CLKPRClock Prescale Register
- Address
0x46 I/O 0x26
- Reset
0x00
- Access
- read/write
- 7CLKPCE
- 6–
- 5–
- 4–
- 3CLKPS3
- 2CLKPS2
- 1CLKPS1
- 0CLKPS0
2 fields
| Field | Bits | What it does |
|---|
| CLKPCE | 7 | Clock Prescaler Change Enable |
| CLKPS | 3:0 | Clock Prescaler Select Bits0 11 22 43 84 165 326 647 1288 256
|
DWDRDebug Wire Data Register
- Address
0x4E I/O 0x2E
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
OSCCALOscillator Calibration Register
- Address
0x51 I/O 0x31
- Reset
0x00
- Access
- read/write
- 7OSCCAL7
- 6OSCCAL6
- 5OSCCAL5
- 4OSCCAL4
- 3OSCCAL3
- 2OSCCAL2
- 1OSCCAL1
- 0OSCCAL0
1 field
| Field | Bits | What it does |
|---|
| OSCCAL | 7:0 | Oscillator Calibration |
MCUSRMCU Status register
- Address
0x54 I/O 0x34
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3WDRF
- 2BORF
- 1EXTRF
- 0PORF
4 fields
| Field | Bits | What it does |
|---|
| WDRF | 3 | Watchdog Reset Flag |
| BORF | 2 | Brown-out Reset Flag |
| EXTRF | 1 | External Reset Flag |
| PORF | 0 | Power-On Reset Flag |
MCUCRMCU Control Register
- Address
0x55 I/O 0x35
- Reset
0x00
- Access
- read/write
- 7–
- 6PUD
- 5SE
- 4SM1
- 3SM0
- 2–
- 1ISC01
- 0ISC00
4 fields
| Field | Bits | What it does |
|---|
| PUD | 6 | Pull-up Disable |
| SE | 5 | Sleep Enable |
| SM | 4:3 | Sleep Mode Select Bits0 Idle1 ADC Noise Reduction (If Available)2 Power Down3 Reserved
|
| ISC0 | 1:0 | Interrupt Sense Control 0 bits0 Low Level of INTX1 Any Logical Change in INTX2 Falling Edge of INTX3 Rising Edge of INTX
|
SPMCSRStore Program Memory Control and Status Register
- Address
0x57 I/O 0x37
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4CTPB
- 3RFLB
- 2PGWRT
- 1PGERS
- 0SPMEN
5 fields
| Field | Bits | What it does |
|---|
| CTPB | 4 | Clear Temporary Page Buffer |
| RFLB | 3 | Read Fuse and Lock Bits |
| PGWRT | 2 | Page Write |
| PGERS | 1 | Page Erase |
| SPMEN | 0 | Store program Memory Enable |
SPLStack Pointer Low Byte
- Address
0x5D I/O 0x3D
- Reset
0x9F
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
SREGStatus Register
- Address
0x5F I/O 0x3F
- Reset
0x00
- Access
- read/write
- 7I
- 6T
- 5H
- 4S
- 3V
- 2N
- 1Z
- 0C
8 fields
| Field | Bits | What it does |
|---|
| I | 7 | Global Interrupt Enable |
| T | 6 | Bit Copy Storage |
| H | 5 | Half Carry Flag |
| S | 4 | Sign Bit |
| V | 3 | Two's Complement Overflow Flag |
| N | 2 | Negative Flag |
| Z | 1 | Zero Flag |
| C | 0 | Carry Flag |
TC0 Timer/Counter, 8-bit
GTCCRGeneral Timer Counter Register
- Address
0x48 I/O 0x28
- Reset
0x00
- Access
- read/write
- 7TSM
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0PSR10
2 fields
| Field | Bits | What it does |
|---|
| TSM | 7 | Timer/Counter Synchronization Mode |
| PSR10 | 0 | Prescaler Reset Timer/Counter0 |
OCR0BTimer/Counter0 Output Compare Register
- Address
0x49 I/O 0x29
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TCCR0ATimer/Counter Control Register A
- Address
0x4F I/O 0x2F
- Reset
0x00
- Access
- read/write
- 7COM0A1
- 6COM0A0
- 5COM0B1
- 4COM0B0
- 3–
- 2–
- 1WGM01
- 0WGM00
3 fields
| Field | Bits | What it does |
|---|
| COM0A | 7:6 | Compare Match Output A Mode |
| COM0B | 5:4 | Compare Match Output B Mode |
| WGM0 | 1:0 | Waveform Generation Mode |
TCNT0Timer/Counter0
- Address
0x52 I/O 0x32
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TCCR0BTimer/Counter Control Register B
- Address
0x53 I/O 0x33
- Reset
0x00
- Access
- read/write
- 7FOC0A
- 6FOC0B
- 5–
- 4–
- 3WGM02
- 2CS02
- 1CS01
- 0CS00
4 fields
| Field | Bits | What it does |
|---|
| FOC0A | 7 | Force Output Compare A |
| FOC0B | 6 | Force Output Compare B |
| WGM02 | 3 | Waveform Generation Mode |
| CS0 | 2:0 | Clock Select0 No Clock Source (Stopped)1 Running, No Prescaling2 Running, CLK/83 Running, CLK/644 Running, CLK/2565 Running, CLK/10246 Running, ExtClk Tn Falling Edge7 Running, ExtClk Tn Rising Edge
|
OCR0ATimer/Counter0 Output Compare Register
- Address
0x56 I/O 0x36
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0–
TIFR0Timer/Counter0 Interrupt Flag register
- Address
0x58 I/O 0x38
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3OCF0B
- 2OCF0A
- 1TOV0
- 0–
3 fields
| Field | Bits | What it does |
|---|
| OCF0B | 3 | Timer/Counter0 Output Compare Flag 0B |
| OCF0A | 2 | Timer/Counter0 Output Compare Flag 0A |
| TOV0 | 1 | Timer/Counter0 Overflow Flag |
TIMSK0Timer/Counter0 Interrupt Mask Register
- Address
0x59 I/O 0x39
- Reset
0x00
- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3OCIE0B
- 2OCIE0A
- 1TOIE0
- 0–
3 fields
| Field | Bits | What it does |
|---|
| OCIE0B | 3 | Timer/Counter0 Output Compare Match B Interrupt Enable |
| OCIE0A | 2 | Timer/Counter0 Output Compare Match A Interrupt Enable |
| TOIE0 | 1 | Timer/Counter0 Overflow Interrupt Enable |