PIC16F15313 configuration bits The configuration words set the oscillator, the watchdog, the power-up timer, brown-out reset, low-voltage programming and code protection. Pick a setting and the word below updates; the starting values are the defaults in Microchip's device file. In XC8 each setting is a #pragma config NAME = SETTING line.
CONFIG1 · 0x8007 0x3FFF default 0x3FFF FCMEN Fail-Safe Clock Monitor Enable bit FSCM timer disabled FSCM timer enabled CSWEN Clock Switch Enable bit The NOSC and NDIV bits cannot be changed by user software Writing to NOSC and NDIV is allowed CLKOUTEN Clock Out Enable bit CLKOUT function is enabled; FOSC/4 clock appears at OSC2 CLKOUT function is disabled; i/o or oscillator function on OSC2 RSTOSC Power-up default value for COSC bits HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1 HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1 (FOSC = 32 MHz) EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits LFINTOSC HFINTOSC (1MHz) EXTOSC operating per FEXTOSC bits FEXTOSC External Oscillator mode selection bits LP (crystal oscillator) optimized for 32.768kHz; PFM set to low power XT (crystal oscillator) above 500kHz, below 4MHz; PFM set to medium power HS (crystal oscillator) above 4MHz; PFM set to high power Oscillator not enabled EC below 500kHz; PFM set to low power EC for 500kHz to 8MHz; PFM set to medium power EC above 8MHz; PFM set to high power CONFIG2 · 0x8008 0x3FFF default 0x3FFF DEBUG Background Debugger background debugger enabled Background Debugger disabled STVREN Stack Overflow/Underflow Reset Enable bit Stack Overflow or Underflow will not cause a reset Stack Overflow or Underflow will cause a reset PPS1WAY Peripheral Pin Select one-way control The PPSLOCK bit can be set and cleared repeatedly by software The PPSLOCK bit can be cleared and set only once in software ZCD Zero-cross detect disable Zero-cross detect circuit is always enabled Zero-cross detect circuit is disabled at POR. BORV Brown-out Reset Voltage Selection Brown-out Reset Voltage (VBOR) is set to 2.7V Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices BOREN Brown-out reset enable bits Brown-out reset disabled Brown-out reset enabled according to SBOREN bit Brown-out Reset enabled while running, disabled in sleep; SBOREN is ignored Brown-out Reset Enabled, SBOREN bit is ignored LPBOREN Low-Power BOR enable bit ULPBOR enabled ULPBOR disabled PWRTE Power-up Timer Enable bit PWRT enabled PWRT disabled MCLRE Master Clear Enable bit MCLR pin function is port defined function MCLR pin is Master Clear function CONFIG3 · 0x8009 0x3FFF default 0x3FFF WDTCCS WDT input clock selector WDT reference clock is the 31.0kHz LFINTOSC output WDT reference clock is the 31.25 kHz HFINTOSC Reserved Software Control WDTCWS WDT Window Select bits window delay = 87.5 percent of time; no software control; keyed access required window delay = 75 percent of time; no software control; keyed access required window delay = 62.5 percent of time; no software control; keyed access required window delay = 50 percent of time; no software control; keyed access required window delay = 37.5 percent of time; no software control; keyed access required window delay = 25 percent of time; no software control; keyed access required window always open (100%); no software control; keyed access required window always open (100%); software control; keyed access not required WDTE WDT operating mode WDT Disabled, SWDTEN is ignored WDT enabled/disabled by SWDTEN bit in WDTCON0 WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored WDT enabled regardless of sleep; SWDTEN ignored WDTCPS WDT Period Select bits Divider ratio 1:32 Divider ratio 1:64 Divider ratio 1:128 Divider ratio 1:256 Divider ratio 1:512 Divider ratio 1:1024 Divider ratio 1:2048 Divider ratio 1:4096 Divider ratio 1:8192 Divider ratio 1:16384 Divider ratio 1:32768 Divider ratio 1:65536 Divider ratio 1:131072 Divider ratio 1:262144 Divider ratio 1:524299 Divider ratio 1:1048576 Divider ratio 1:2097152 Divider ratio 1:4194304 Divider ratio 1:8388608 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:32 Divider ratio 1:65536; software control of WDTPS CONFIG4 · 0x800A 0x3FFF default 0x3FFF LVP Low Voltage Programming Enable bit High Voltage on MCLR/Vpp must be used for programming Low Voltage programming enabled. MCLR/Vpp pin function is MCLR. WRTSAF Storage Area Flash Write Protection bit SAF write protected SAF not write protected WRTC Configuration Register Write Protection bit Configuration Register write protected Configuration Register not write protected WRTB Boot Block Write Protection bit Boot Block write protected Boot Block not write protected WRTAPP Application Block Write Protection bit Application Block write protected Application Block not write protected SAFEN SAF Enable bit SAF enabled SAF disabled BBEN Boot Block Enable bit Boot Block enabled Boot Block disabled BBSIZE Boot Block Size Selection bits * half of user program memory * half of user program memory * half of user program memory * half of user program memory * half of user program memory 2048 words boot block size 1024 words boot block size 512 words boot block size CONFIG5 · 0x800B 0x3FFF default 0x3FFF CP UserNVM Program memory code protection bit UserNVM code protection enabled UserNVM code protection disabled 
BETA