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74HC1658-bit parallel-to-serial register
Capture eight switches. Read them through one data wire.
74HC165 is a 16-pin parallel-to-serial shift register that captures eight digital inputs and sends their states to a controller one bit at a time. Pull SH/LD LOW to load the switches, return it HIGH, then read H first and clock the remaining bits toward the serial output. Clock inhibit pauses shifting while a complementary output offers the inverted bit. This page covers TI SN74HC165N in PDIP-16 and SN74HC165D in SOIC-16, using a 5 V switch-input example.
Load & inhibitClock inputParallel & serial inputsSerial outputsSupply & return
SN74HC165NPDIP-16Top view
SN74HC165DSOIC-16Top view
Click a lead or use the arrow keys. Top view
PIN 1 · Load & inhibit
Active-low parallel loadSH/LD
Function
LOW enables direct parallel loading, independently of CLK, inhibit and serial data.
How to connect
Pulse LOW, then HIGH before reading the captured byte.
Electrical note
While held LOW the register follows the parallel inputs; it is not only an edge-triggered latch.
PIN 2 · Clock input
Clock inputCLK
Function
A rising edge shifts data toward H when SH/LD is HIGH and CLK INH is LOW.
How to connect
Connect to a clean controller output; read QH before the first pulse.
PIN 3 · Parallel & serial inputs
Parallel inputE
Function
Input E loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 4 · Parallel & serial inputs
Parallel inputF
Function
Input F loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 5 · Parallel & serial inputs
Parallel inputG
Function
Input G loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 6 · Parallel & serial inputs
Parallel inputH
Function
Input H loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 7 · Serial outputs
Complementary serial outputQH̅
Function
Inverted version of the last shift-register stage.
How to connect
Leave unconnected if only the normal QH output is needed.
Electrical note
This is an output, not a ground connection.
PIN 8 · Supply & return
Supply returnGND
Function
Ground reference for all logic signals.
How to connect
Connect to controller ground and the bypass capacitor return.
PIN 9 · Serial outputs
Serial outputQH
Function
The H-stage value; exposes H first after parallel loading.
How to connect
Connect to a controller input, or SER of the next register.
Electrical note
Read the bit before applying the clock pulse that shifts the next bit into H.
PIN 10 · Parallel & serial inputs
Serial fill inputSER
Function
The bit entering A on a permitted shift edge.
How to connect
Tie LOW in a single-register circuit, or connect the preceding register’s QH when cascading.
PIN 11 · Parallel & serial inputs
Parallel inputA
Function
Input A loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 12 · Parallel & serial inputs
Parallel inputB
Function
Input B loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 13 · Parallel & serial inputs
Parallel inputC
Function
Input C loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 14 · Parallel & serial inputs
Parallel inputD
Function
Input D loads its corresponding stage while SH/LD is LOW.
How to connect
Connect to the switch node with a 10 kΩ pull-up to +5 V; the switch connects the node to GND.
Electrical note
H is read first at QH. A is read last. Do not leave unused CMOS inputs floating.
PIN 15 · Load & inhibit
Clock inhibitCLK INH
Function
HIGH prevents CLK pulses from shifting the register.
How to connect
Tie LOW for the basic circuit. If controlled, change it to HIGH while CLK is already HIGH.
Electrical note
Raising CLK INH while CLK is LOW also creates a shift edge. The two clock inputs are logically interchangeable.
PIN 16 · Supply & return
Positive supplyVCC
Function
Supply for the register and output buffers.
How to connect
Use +5 V for the example; place 100 nF between pins 16 and 8.
Electrical note
Recommended range 2–6 V. A 3.3 V controller HIGH is not guaranteed at a 5 V HC supply.
At a glance
8-bit parallel-to-serial register
Eight parallel signals become a serial byte without a processor inside the IC.
2–6 VRecommended supply
8 A through HParallel inputs
−40–125 °CAmbient range
21 MHz · −40 to 125°CClock limit at 4.5 V
Operating profile
SN74HC165N
Operating conditions
Key parameters and their test conditions
- Supply
- 2–6 VConditions / notes: 5 V nominal
- Ambient temperature
- −40 to +125°CConditions / notes: SN74HC165; limits depend on temperature
- Input HIGH minimum
- 3.15 VConditions / notes: VCC = 4.5 V
- Input LOW maximum
- 1.35 VConditions / notes: VCC = 4.5 V
- Unused inputs
- Defined HIGH or LOWConditions / notes: Never leave CMOS inputs floating
Package details
Follows the selected physical package
- Manufacturer
- Texas Instruments
- Part number
- SN74HC165N
- Package
- PDIP-16
- Connections
- 16 pins
- Mounting
- Through-hole
- Lead pitch
- 2.54 mm
- Package code
- dip
- Thermal reference
- Board and package dependent; see manufacturer data
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Load & inhibit2 pins
Clock input1 pins
Parallel & serial inputs9 pins
Serial outputs2 pins
Supply & return2 pins
Load & inhibit2 pins
Clock input1 pins
Parallel & serial inputs9 pins
Serial outputs2 pins
Supply & return2 pins
Capture the input states
Each switch has a pull-up resistor. An open switch reads HIGH; a closed switch reads LOW. SH/LD LOW loads all eight states into the register.
Read H, then shift
Return SH/LD HIGH. Read QH before the first clock edge, then pulse CLK to expose the next bit. Eight reads recover H through A.
Pause or extend the chain
CLK INH HIGH blocks ordinary CLK pulses. For more inputs, connect one register’s QH to the next SER and share the load and clock signals.
The switches and register below are an ideal logic teaching model. Propagation delay, contact bounce and analog voltage thresholds still matter in a physical circuit.
Capture eight inputs. Read one wire.
Set the switches, load the register, and watch the serial data leave H first.
Serial fill · pin 10
Click a switch. H is read first; A is read last.
SH/LD LOW loads all eight inputs
With SH/LD HIGH, each permitted rising edge moves A → H.
H0G0F0E0D0C0B0A0
QH · pin 90
QH̅ · pin 71
Serial bits read · H → A
Enable JavaScript to try the controls.
Ideal slow-motion logic. Inputs follow while SH/LD is held LOW. Raising inhibit while CLK is LOW also clocks the register, just as on the IC. The demo starts cleared; real power-up data is unspecified. Contact bounce and propagation delays are omitted.
Pin reference
Select a pin to explore its function and connection.
16 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| SH/LD | Active-low parallel load | LOW enables direct parallel loading, independently of CLK, inhibit and serial data. | |
| CLK | Clock input | A rising edge shifts data toward H when SH/LD is HIGH and CLK INH is LOW. | |
| E | Parallel input | Input E loads its corresponding stage while SH/LD is LOW. | |
| F | Parallel input | Input F loads its corresponding stage while SH/LD is LOW. | |
| G | Parallel input | Input G loads its corresponding stage while SH/LD is LOW. | |
| H | Parallel input | Input H loads its corresponding stage while SH/LD is LOW. | |
| QH̅ | Complementary serial output | Inverted version of the last shift-register stage. | |
| GND | Supply return | Ground reference for all logic signals. | |
| QH | Serial output | The H-stage value; exposes H first after parallel loading. | |
| SER | Serial fill input | The bit entering A on a permitted shift edge. | |
| A | Parallel input | Input A loads its corresponding stage while SH/LD is LOW. | |
| B | Parallel input | Input B loads its corresponding stage while SH/LD is LOW. | |
| C | Parallel input | Input C loads its corresponding stage while SH/LD is LOW. | |
| D | Parallel input | Input D loads its corresponding stage while SH/LD is LOW. | |
| CLK INH | Clock inhibit | HIGH prevents CLK pulses from shifting the register. | |
| VCC | Positive supply | Supply for the register and output buffers. |
No pins match. Try a signal name or choose All pins.
Operating conditions
SN74HC165N / SN74HC165D
Manufacturer specifications 5 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply | 2–6 V | 5 V nominal |
| Ambient temperature | −40 to +125°C | SN74HC165; limits depend on temperature |
| Input HIGH minimum | 3.15 V | VCC = 4.5 V |
| Input LOW maximum | 1.35 V | VCC = 4.5 V |
| Unused inputs | Defined HIGH or LOW | Never leave CMOS inputs floating |
No specifications match. Try a parameter name or a unit.
TI SCLS116H recommended conditions.
Electrical characteristics
4.5 V unless stated
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Output HIGH | ≥3.70 V | IOH = −4 mA; −40 to 125°C |
| Output LOW | ≤0.33 V | IOL = 4 mA; −40 to 125°C |
| Supply current | ≤160 µA | 6 V; inputs at rails; unloaded; −40 to 125°C |
| Supply current at lower temperature | ≤80 µA | Same conditions; −40 to 85°C |
| Input leakage | ±1 µA maximum | 6 V; −40 to 125°C |
| Input capacitance | 10 pF maximum | 2–6 V |
No specifications match. Try a parameter name or a unit.
Output drive ratings are not the absolute maximum current.
Timing reference
VCC = 4.5 V · −40 to 125°C
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Maximum clock | 21 MHz | Use all setup and hold requirements |
| CLK HIGH / LOW pulse | ≥24 ns | Each half-cycle |
| SH/LD LOW pulse | ≥24 ns | Parallel loading |
| SH/LD HIGH before CLK ↑ | ≥24 ns | Recovery to shifting |
| SER setup / hold | ≥12 ns / ≥5 ns | Around CLK rising edge |
| Parallel data setup / hold | ≥30 ns / ≥5 ns | Referenced to SH/LD falling edge in TI timing table |
| CLK → serial output | ≤45 ns | CL = 50 pF |
No specifications match. Try a parameter name or a unit.
These are selected limits; consult the PDF for all clock-inhibit and voltage conditions.
Load and clock functions
Asynchronous parallel load has priority
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| SH/LD LOW | Load A–H | Independent of clock and inhibit |
| SH/LD HIGH; CLK ↑; INH LOW | Shift toward H | SER enters A |
| SH/LD HIGH; INH ↑; CLK LOW | Also shifts | Change inhibit while CLK is HIGH to avoid this edge |
| CLK INH HIGH | CLK pulses blocked | Parallel loading still works |
| QH̅ | Complement of QH | Neither output is three-state |
| Power-up | Register contents unspecified | Capture the inputs before using the byte |
No specifications match. Try a parameter name or a unit.
Unlike 74HC595, this IC expands inputs and has no separate output-storage register.
Package and stress limits
SN74HC165N · PDIP-16
Manufacturer specifications 5 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 2.54 mm | Through-hole; top view |
| Supply absolute maximum | −0.5 to +7 V | Stress rating only |
| Continuous output current | ±25 mA | Absolute maximum per output |
| VCC or GND current | ±50 mA | Absolute maximum package current |
| Storage temperature | −65 to +150°C | Unpowered storage |
No specifications match. Try a parameter name or a unit.
Use recommended operating conditions for normal operation. Verify the exact package before PCB manufacture.
Switch banks and buttons
Read eight switch states through a serial connection. Pull-ups prevent floating inputs; debounce in software when contacts chatter.
Manufacturer application guideController input expansion
Capture all inputs together, then read them at a controlled rate. The register does not measure analog sensor levels.
Manufacturer application guideCascaded input chains
Share clock and load, connect QH to the next SER, and read one byte per IC. Document chip order so firmware maps each bit correctly.
Manufacturer application guideTake it into ProTech
Find 74HC165 in the Components Library to place its schematic symbol and connect its pins.
Reference page · circuit simulation model not yet availableOpen ProTech