Real View
74HC5958-bit serial-to-parallel register
Three control wires. Eight outputs. One synchronized update.
74HC595 is a 16-pin serial-to-parallel IC that turns a stream of bits into eight digital outputs. A separate storage register keeps the outputs steady while the next byte is shifted in. Pulse the latch clock to update all eight outputs together. Output enable can disconnect the outputs without erasing their data; the serial output lets you chain more registers. This reference covers TI SN74HC595N in PDIP-16 and SN74HC595D in SOIC-16, with a 5 V LED example.
Parallel outputsSupply & returnCascade outputControl inputsClock inputsSerial data
SN74HC595NPDIP-16Top view
SN74HC595DSOIC-16Top view
Click a lead or use the arrow keys. Top view
PIN 1 · Parallel outputs
Three-state outputQB
Function
Storage-register output B. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 2 · Parallel outputs
Three-state outputQC
Function
Storage-register output C. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 3 · Parallel outputs
Three-state outputQD
Function
Storage-register output D. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 4 · Parallel outputs
Three-state outputQE
Function
Storage-register output E. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 5 · Parallel outputs
Three-state outputQF
Function
Storage-register output F. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 6 · Parallel outputs
Three-state outputQG
Function
Storage-register output G. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 7 · Parallel outputs
Three-state outputQH
Function
Storage-register output H. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 8 · Supply & return
Supply returnGND
Function
Ground reference for logic and output current.
How to connect
Join the controller ground and capacitor return here.
PIN 9 · Cascade output
Serial outputQH′
Function
Last stage of the shift register, before the output latch.
How to connect
Connect to SER of the next register when cascading; otherwise leave unconnected.
Electrical note
OE does not disable this output. It is not the latched QH output at pin 7.
PIN 10 · Control inputs
Active-low clearSRCLR
Function
LOW asynchronously clears all eight shift-register stages. The storage register is unchanged.
How to connect
Hold HIGH for normal shifting. To clear the displayed outputs, pulse LOW, release, then pulse RCLK.
Electrical note
LOW blocks serial loading; clearing the shift register alone does not blank the LEDs.
PIN 11 · Clock inputs
Rising-edge clockSRCLK
Function
Samples SER into stage A and shifts the other bits toward H.
How to connect
Connect to Arduino D13 (SCK) or a clean digital clock.
Electrical note
Keep SER stable for the specified setup and hold times.
PIN 12 · Clock inputs
Rising-edge latch clockRCLK
Function
Copies all eight shift-register bits into the storage register together.
How to connect
Connect to Arduino D10 and pulse after shifting the complete byte.
Electrical note
A simultaneous rise of both clocks transfers the previous shift-register contents.
PIN 13 · Control inputs
Active-low output enableOE
Function
LOW enables QA–QH; HIGH places those eight outputs in high impedance.
How to connect
Tie LOW for the illustrated always-enabled display, or drive from a controller.
Electrical note
Neither register is erased. High impedance is not the same as driving a logic LOW.
PIN 14 · Serial data
Serial data inputSER
Function
Data sampled on each rising SRCLK edge.
How to connect
Connect to Arduino D11 (MOSI) or another digital data source.
Electrical note
For the displayed QH→QA pattern, transmit the most significant bit first.
PIN 15 · Parallel outputs
Three-state outputQA
Function
Storage-register output A. It changes after a rising RCLK edge, not on every shift clock.
How to connect
Connect through its own 560 Ω resistor to an LED anode; connect the cathode to GND.
Electrical note
OE HIGH disconnects the output into a high-impedance state. Check per-output and total package current.
PIN 16 · Supply & return
Positive supplyVCC
Function
Powers the register and its output drivers.
How to connect
Use regulated +5 V in this example; add 100 nF directly between pins 16 and 8.
Electrical note
Recommended range 2–6 V. A 3.3 V HIGH is not guaranteed to meet the HC threshold at a 5 V supply.
At a glance
8-bit serial-to-parallel register
Separate shift and storage registers let you prepare the next pattern while the current one stays visible.
2–6 VRecommended supply
8 three-stateLatched parallel outputs
−40–85 °CAmbient range
25 MHz · full temperature rangeClock limit at 4.5 V
Operating profile
SN74HC595N
Operating conditions
Key parameters and their test conditions
- Supply voltage
- 2–6 VConditions / notes: Recommended; example uses 5 V
- Ambient temperature
- −40 to +85°CConditions / notes: SN74HC595 grade
- Input HIGH, VIH
- ≥3.15 VConditions / notes: VCC = 4.5 V
- Input LOW, VIL
- ≤1.35 VConditions / notes: VCC = 4.5 V
- Input transition time
- ≤500 nsConditions / notes: VCC = 4.5 V; do not use slow floating edges
Package details
Follows the selected physical package
- Manufacturer
- Texas Instruments
- Part number
- SN74HC595N
- Package
- PDIP-16
- Connections
- 16 pins
- Mounting
- Through-hole
- Lead pitch
- 2.54 mm
- Package code
- N
- Thermal reference
- 67°C/W · TI RθJA reference
Connections by function
Select a pin to open its function, electrical notes and wiring guidance.
Parallel outputs8 pins
Supply & return2 pins
Cascade output1 pins
Control inputs2 pins
Clock inputs2 pins
Serial data1 pins
Parallel outputs8 pins
Supply & return2 pins
Cascade output1 pins
Control inputs2 pins
Clock inputs2 pins
Serial data1 pins
Shift the byte
Set SER, then pulse SRCLK. Each rising edge loads A and moves the older bits toward H. Eight pulses load a complete byte; the displayed outputs stay unchanged.
Latch the outputs
Pulse RCLK after the byte is ready. The storage register captures all eight bits together, so the LEDs change as a group.
Enable, clear or expand
OE HIGH disconnects QA–QH without losing data. SRCLR LOW clears only the shift register; latch afterward to display zeros. QH′ feeds another chip for more outputs.
The explorer models ideal logic transitions in slow motion. Use the linked ProTech example to run the connected circuit and examine its timing.
Shift it. Latch it. Light it.
Follow each bit from serial input to eight parallel outputs.
Enter exactly eight binary digits (0 or 1).
Manual serial input · pin 14
SRCLK ↑ moves each bit one stage toward H.
H0G0F0E0D0C0B0A0
RCLK ↑ copies all eight bits together
These bits stay unchanged while new data shifts in.
H0G0F0E0D0C0B0A0
QHpin 70QGpin 60QFpin 50QEpin 40QDpin 30QCpin 20QBpin 10QApin 150
Shift clocks 0Pattern progress 0 / 8QH′ · pin 9 0
Enable JavaScript to try the controls.
Ideal logic demonstration in slow motion, initialized to zeros for clarity. Real power-up contents are unspecified. Propagation delay, electrical loading and analog LED brightness are not modeled here.
Pin reference
Select a pin to explore its function and connection.
16 pins
| Pin | Signal | Type | Function |
|---|---|---|---|
| QB | Three-state output | Storage-register output B. It changes after a rising RCLK edge, not on every shift clock. | |
| QC | Three-state output | Storage-register output C. It changes after a rising RCLK edge, not on every shift clock. | |
| QD | Three-state output | Storage-register output D. It changes after a rising RCLK edge, not on every shift clock. | |
| QE | Three-state output | Storage-register output E. It changes after a rising RCLK edge, not on every shift clock. | |
| QF | Three-state output | Storage-register output F. It changes after a rising RCLK edge, not on every shift clock. | |
| QG | Three-state output | Storage-register output G. It changes after a rising RCLK edge, not on every shift clock. | |
| QH | Three-state output | Storage-register output H. It changes after a rising RCLK edge, not on every shift clock. | |
| GND | Supply return | Ground reference for logic and output current. | |
| QH′ | Serial output | Last stage of the shift register, before the output latch. | |
| SRCLR | Active-low clear | LOW asynchronously clears all eight shift-register stages. The storage register is unchanged. | |
| SRCLK | Rising-edge clock | Samples SER into stage A and shifts the other bits toward H. | |
| RCLK | Rising-edge latch clock | Copies all eight shift-register bits into the storage register together. | |
| OE | Active-low output enable | LOW enables QA–QH; HIGH places those eight outputs in high impedance. | |
| SER | Serial data input | Data sampled on each rising SRCLK edge. | |
| QA | Three-state output | Storage-register output A. It changes after a rising RCLK edge, not on every shift clock. | |
| VCC | Positive supply | Powers the register and its output drivers. |
No pins match. Try a signal name or choose All pins.
Operating conditions
TI SN74HC595N / SN74HC595D
Manufacturer specifications 5 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply voltage | 2–6 V | Recommended; example uses 5 V |
| Ambient temperature | −40 to +85°C | SN74HC595 grade |
| Input HIGH, VIH | ≥3.15 V | VCC = 4.5 V |
| Input LOW, VIL | ≤1.35 V | VCC = 4.5 V |
| Input transition time | ≤500 ns | VCC = 4.5 V; do not use slow floating edges |
No specifications match. Try a parameter name or a unit.
TI SCLS041J recommended operating conditions. Do not substitute HCT logic thresholds.
Electrical characteristics
Supply, temperature and load matter
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Parallel-output HIGH, VOH | ≥3.84 V | VCC = 4.5 V; IOH = −6 mA; −40 to 85°C |
| Parallel-output LOW, VOL | ≤0.33 V | VCC = 4.5 V; IOL = 6 mA; −40 to 85°C |
| QH′ test drive | ±4 mA | VCC = 4.5 V; serial-output test current |
| Supply current, ICC | ≤80 µA | VCC = 6 V; inputs at rails; outputs unloaded |
| Input current, II | ±1 µA maximum | VCC = 6 V |
| Disabled-output leakage | ±5 µA maximum | VCC = 6 V |
| Input capacitance | 3 pF typical; 10 pF maximum | See TI electrical characteristics |
No specifications match. Try a parameter name or a unit.
LED load current is additional to the unloaded supply current. Typical values are not guaranteed limits.
Timing requirements
4.5 V · −40 to 85°C unless noted
Manufacturer specifications 8 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Maximum clock frequency | 25 MHz | SRCLK or RCLK |
| Clock HIGH / LOW width | ≥20 ns | SRCLK and RCLK |
| SRCLR LOW pulse | ≥20 ns | Asynchronous shift clear |
| SER setup before SRCLK ↑ | ≥25 ns | Data stable before rising clock |
| SER hold after SRCLK ↑ | ≥0 ns | Minimum manufacturer requirement |
| SRCLK ↑ before RCLK ↑ | ≥19 ns | Shift-to-storage setup |
| SRCLR HIGH before SRCLK ↑ | ≥12 ns | Clear recovery |
| RCLK → QA–QH delay | 17 ns typical; 37 ns maximum | CL = 50 pF; typical at 25°C; maximum full range |
No specifications match. Try a parameter name or a unit.
Actual system speed also depends on wiring, loading, clock quality and the controller.
Control functions
Two registers with distinct jobs
Manufacturer specifications 7 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| SRCLK rising; SRCLR HIGH | Shift one bit | SER enters A; A→B … G→H |
| RCLK rising | Copy shift → storage | All eight output bits update together |
| SRCLR LOW | Clear shift register | Storage contents remain unchanged |
| OE HIGH | QA–QH become high impedance | Neither register is erased; QH′ remains active |
| OE LOW | Drive stored bits | Outputs return to their latched values |
| Both clocks rise together | Latch previous shift state | Separate the edges for straightforward byte transfers |
| Power-up | Output contents unspecified | Initialize explicitly; do not assume zeros |
No specifications match. Try a parameter name or a unit.
Z denotes high impedance, not a driven LOW. The interactive demo starts from a deliberately cleared state.
Package and stress limits
SN74HC595N · PDIP-16
Manufacturer specifications 6 parameters
| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 2.54 mm | Through-hole; top view |
| Supply absolute maximum | −0.5 to +7 V | Stress rating, not the recommended range |
| Continuous current per output | ±35 mA | Absolute maximum; not a normal drive target |
| Continuous VCC / GND current | ±70 mA | Absolute maximum total package current |
| Junction temperature | 150°C maximum | Absolute maximum |
| Storage temperature | −65 to +150°C | Unpowered storage |
No specifications match. Try a parameter name or a unit.
Design within recommended conditions. Footprint dimensions and the exact package drawing must be checked before fabrication.
LED and status displays
Drive individual LEDs through separate current-limiting resistors. Keep the sum of output currents within the IC ratings; use drivers for larger loads.
Manufacturer application guideMicrocontroller output expansion
Share data and clock across cascaded registers, link QH′ to the next SER, and latch the entire chain after sending all bytes.
Manufacturer application guideSeven-segment displays
Map one output to each segment. Account for common-anode or common-cathode polarity and provide a resistor per segment. Multiplexed displays may need external transistor drivers.
Manufacturer application guideTake it into ProTech
Find 74HC595 in the Components Library to place its schematic symbol and connect its pins.
Simulation model available · Run the shift-register displayOpen ProTech