BETASelected packageSPDIP-28MCP23017-E/SP
16-bit register-controlled I²C port expander
MCP23017 Reference Tables
Search the MCP23017 pin reference and manufacturer-referenced specification tables.
Package view
Physical connections28 pinsPackage-specific numbering
Reference collection8 tables59 parameters & pin functions
Pin reference
Signal names, electrical functions and connection guidance
Physical pin numbers28 pins
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| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| GPB0 | Configurable digital I/O | Port B bit 0; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB1 | Configurable digital I/O | Port B bit 1; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB2 | Configurable digital I/O | Port B bit 2; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB3 | Configurable digital I/O | Port B bit 3; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB4 | Configurable digital I/O | Port B bit 4; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB5 | Configurable digital I/O | Port B bit 5; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB6 | Configurable digital I/O | Port B bit 6; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPB7 | Output only | The current MCP23017 datasheet restricts this terminal to output use. Do not allocate it to a switch or sensor input.Connection guidanceConfigure as output LOW and leave open when unused. GPA7 / GPB7 output-only restriction is specific to MCP23017; do not inherit MCP23S17 input capability. | |
| VDD | Supply | Powers logic and I/O. Supply, temperature and bus-rate conditions must be considered together.Connection guidanceUse +5 V and 100 nF to VSS10. | |
| VSS | Ground | Supply and signal reference.Connection guidanceJoin controller ground. | |
| NC | No connection | Not used on the I²C MCP23017.Connection guidanceLeave unconnected. This is CS on the different SPI MCP23S17. | |
| SCL | I²C clock input | Clock for register transfers.Connection guidanceConnect to host SCL and a suitable pull-up to +5 V. 100 kHz example; faster modes require their own voltage and timing conditions. | |
| SDA | I²C data I/O | Open-drain serial data line.Connection guidanceConnect to host SDA and a suitable pull-up to +5 V. | |
| NC | No connection | Not used on the I²C MCP23017.Connection guidanceLeave unconnected. This is SO on the different SPI MCP23S17. | |
| A0 | Address input | Sets hardware address bit 0; all three LOW select 0x20.Connection guidanceTie directly to GND in the example. Do not leave address inputs floating. | |
| A1 | Address input | Sets hardware address bit 1; all three LOW select 0x20.Connection guidanceTie directly to GND in the example. Do not leave address inputs floating. | |
| A2 | Address input | Sets hardware address bit 2; all three LOW select 0x20.Connection guidanceTie directly to GND in the example. Do not leave address inputs floating. | |
| RESET̅ | Active-LOW reset input | Resets registers and places outputs in the reset state.Connection guidanceUse a 10 kΩ pull-up to +5 V and a controller or reset switch to GND. Minimum LOW reset pulse is 1 µs. | |
| INTB | Port B interrupt | Configurable polarity and push-pull/open-drain output. May be mirrored with INTA through IOCON.Connection guidanceLeave open in this example; port B interrupts are disabled. | |
| INTA | Port A interrupt | Reports enabled input conditions. GPIO or INTCAP reads clear the associated interrupt as specified.Connection guidanceUse open-drain mode with 10 kΩ pull-up to +5 V and connect host IRQ. IOCON.ODR = 1 enables open-drain, active-LOW operation. | |
| GPA0 | Configurable digital I/O | Port A bit 0; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceConnect LED cathode; anode through 1 kΩ to +5 V. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA1 | Configurable digital I/O | Port A bit 1; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceConnect pushbutton to GND; enable input mode and weak pull-up. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA2 | Configurable digital I/O | Port A bit 2; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA3 | Configurable digital I/O | Port A bit 3; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA4 | Configurable digital I/O | Port A bit 4; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA5 | Configurable digital I/O | Port A bit 5; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA6 | Configurable digital I/O | Port A bit 6; IODIR selects input/output, GPPU enables weak pull-up, and interrupt registers control input-change detection.Connection guidanceLeave open with input weak pull-up enabled in this example. Read GPIO for terminal levels and OLAT for the output latch. | |
| GPA7 | Output only | The current MCP23017 datasheet restricts this terminal to output use. Do not allocate it to a switch or sensor input.Connection guidanceConfigure as output LOW and leave open when unused. GPA7 / GPB7 output-only restriction is specific to MCP23017; do not inherit MCP23S17 input capability. |
No pins match these filters. Try another signal name or reset the filters.
Useful register map
IOCON.BANK = 0
Manufacturer-referenced values11 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| IODIRA / IODIRB | 0x00 / 0x01 | 1 = input; 0 = output; obey bit-7 restriction |
| IPOLA / IPOLB | 0x02 / 0x03 | Input polarity inversion |
| GPINTENA / GPINTENB | 0x04 / 0x05 | Interrupt enable per input |
| DEFVALA / DEFVALB | 0x06 / 0x07 | Default comparison values |
| INTCONA / INTCONB | 0x08 / 0x09 | Previous-state versus default comparison |
| IOCON | 0x0A or 0x0B | BANK, MIRROR, SEQOP, ODR and polarity |
| GPPUA / GPPUB | 0x0C / 0x0D | Weak input pull-up enables |
| INTFA / INTFB | 0x0E / 0x0F | Which enabled pins triggered |
| INTCAPA / INTCAPB | 0x10 / 0x11 | Captured port values at interrupt |
| GPIOA / GPIOB | 0x12 / 0x13 | Read terminal levels; writes update latch |
| OLATA / OLATB | 0x14 / 0x15 | Read/write output latches |
No specifications match. Try a parameter name or a unit.
Changing IOCON.BANK changes register addresses. These values intentionally use the reset BANK = 0 arrangement.
Example initialization
5 V · address 0x20 · BANK = 0
Manufacturer-referenced values9 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| IOCON 0x0A | Write 0x04 | Open-drain INTA/B; BANK remains 0 |
| OLATA 0x14 | Write 0x01 | Preload GPA0 HIGH so LED starts off |
| OLATB 0x15 | Write 0x00 | Preload unused GPB7 output LOW |
| IODIRA 0x00 | Write 0x7E | A0 and A7 outputs; A1–A6 inputs |
| IODIRB 0x01 | Write 0x7F | B7 output; B0–B6 inputs |
| GPPUA / GPPUB | Write 0x7E / 0x7F | Define unused inputs and pull button HIGH |
| INTCONA 0x08 | Write 0x00 | Compare enabled inputs with previous value |
| GPIOA 0x12 | Read once | Establish current state before enabling interrupt |
| GPINTENA 0x04 | Write 0x02 | Enable GPA1 change notification |
No specifications match. Try a parameter name or a unit.
This sequence reserves both bit-7 pins for outputs and leaves the other unused lines safely defined.
Example control and interrupt service
Separate the output latch from input samples
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| LED on | OLATA bit0 = 0 | GPA0 sinks current through the LED |
| LED off | OLATA bit0 = 1 | GPA0 is HIGH |
| Button state | GPIOA bit1 | LOW when button shorts to GND |
| Captured event | Read INTCAPA 0x10 | Read before another operation clears the event |
| Interrupt source | Read INTFA 0x0E | Flag bits identify enabled causes |
| Output updates | Use OLAT or a software shadow | Avoid rewriting sampled input levels as outputs |
| Firmware debounce | Required for a mechanical button | Interrupt edges are not automatically debounced |
No specifications match. Try a parameter name or a unit.
GPIO/INTCAP reads have interrupt-clear side effects. Design the service order deliberately.
Supply and I/O limits
Conditions distinguish the operating ranges
Manufacturer-referenced values10 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VDD at −40 to +85°C | 1.8–5.5 V | Bus-rate constraints still apply |
| VDD at +85 to +125°C | 4.5–5.5 V | Selected E-grade high-temperature operation |
| GPIO / bus / reset HIGH | ≥ 0.8 VDD | Schmitt-trigger inputs |
| GPIO / bus / reset LOW | ≤ 0.2 VDD | Schmitt-trigger inputs |
| Address HIGH / LOW | ≥ 0.25 VDD + 0.8 V / ≤ 0.15 VDD | A0, A1 and A2 |
| GPIO LOW | ≤ 0.6 V at 8 mA | VDD 4.5 V |
| GPIO HIGH | ≥ VDD − 0.7 V at −3 mA | VDD 4.5 V |
| Weak pull-up current | 75 µA typical; 40–115 µA | VDD 5 V; pin at GND |
| Supply current | 1 mA maximum | SCL/SCK 1 MHz |
| Standby current | 1 µA max. through +85°C | 3 µA max. at +85–125°C and 4.5–5.5 V |
No specifications match. Try a parameter name or a unit.
The 25 mA per-output figure is an absolute maximum; loaded voltage specifications provide the usable drive conditions.
Bus-rate and reset requirements
Use the correct supply for each mode
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| 100 kHz | VDD 1.8–5.5 V | SCL HIGH ≥4 µs; LOW ≥4.7 µs |
| 400 kHz | VDD 2.7–5.5 V | SCL HIGH ≥0.6 µs; LOW ≥1.3 µs |
| 1.7 MHz | VDD 4.5–5.5 V | SCL HIGH ≥0.12 µs; LOW ≥0.32 µs |
| Bus capacitance | 400 pF at 100/400 kHz | 100 pF at 1.7 MHz |
| Maximum rise time | 1000 / 300 / 160 ns | 100 kHz / 400 kHz / 1.7 MHz |
| Reset LOW pulse | 1 µs minimum | RESET must be externally biased |
| Output update delay | 500 ns maximum | Specified GPIO timing conditions |
No specifications match. Try a parameter name or a unit.
The example uses 100 kHz and 4.7 kΩ pull-ups on a short bus. Recalculate pull-ups for the actual capacitance and speed.
Physical wiring
SPDIP-28 / SOIC-28 selected pin map
Manufacturer-referenced values8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Power | VDD9 +5 V; VSS10 GND | 100 nF at the IC |
| I²C | SCL12 and SDA13 | 4.7 kΩ pull-ups to +5 V |
| Address | A0 pin15, A1 pin16, A2 pin17 to GND | 7-bit address 0x20 |
| Reset | RESET18 with 10 kΩ pull-up | Controller reset or switch may pull LOW |
| LED | GPA0 pin21 to cathode | Anode through 1 kΩ to +5 V |
| Button | GPA1 pin22 to switch to GND | GPPUA bit1 enabled |
| Interrupt | INTA20 to host IRQ | 10 kΩ pull-up; IOCON.ODR = 1 |
| Unused terminals | NC11/14 and INTB19 open | A7/B7 outputs LOW and open; other unused GPIO pulled up |
No specifications match. Try a parameter name or a unit.
The controller and pull-ups use the same 5 V logic domain. Do not assume 3.3 V meets the 5 V input HIGH threshold.
Packages and stress limits
MCP23017-E/SP · SPDIP-28
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| SP package | SPDIP-28; 2.54 mm pitch | 7.62 mm row spacing |
| SO package | Wide SOIC-28; 1.27 mm pitch | 7.50 mm body width |
| NC pins | 11 and 14 on these packages | The imported logical symbol has 26 electrical pins; the physical map has 28 |
| Maximum output current | ±25 mA absolute maximum per pin | Not a recommended continuous target |
| Supply/ground absolute current | 125 mA into VDD; 150 mA out of VSS | Sum loads and observe thermal limits |
| Storage temperature | −65 to +150°C | Unpowered |
| MCP23S17 distinction | SPI interface and different pin use | Do not copy its CS/SO wiring or bit-7 input capability |
No specifications match. Try a parameter name or a unit.
Package selection preserves the physical pin numbers and uses the appropriate footprint.
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