MCP2562 Reference Tables, Pins & Specifications

Pin reference

Signal names, electrical functions and connection guidance

PDIP-8

Physical pin numbers8 pins

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MCP2562 pin functions and connections
Signal	Type	Function & connection
TXD	Transmit data input	LOW requests a dominant bus state; HIGH releases the bus to recessive unless another node is dominant. Connection guidance Connect to the CAN controller TX output. Internal pull-up to VIO; prolonged LOW invokes dominant timeout.
VSS	Ground	Supply and logic reference. Connection guidance Join controller ground and the intended bus reference.
VDD	Bus-side supply	Powers the transmitter and receiver. Connection guidance Use 4.5–5.5 V; bypass locally with 100 nF to VSS.
RXD	Receive data output	LOW reports a dominant bus, HIGH a recessive bus in Normal mode. Standby reception is filtered. Connection guidance Connect to CAN controller RX. Output HIGH level follows VIO, not the 5 V bus supply.
VIO	Digital I/O supply	Sets the voltage domain for TXD, RXD and STBY. Connection guidance Connect to the controller I/O supply, 1.8–5.5 V, and bypass with 100 nF. This pin is VIO on MCP2562; MCP2561 has SPLIT here instead.
CANL	CAN low bus terminal	Low-going side of the differential bus during a dominant bit. Connection guidance Connect to CANL in the twisted pair.
CANH	CAN high bus terminal	High-going side of the differential bus during a dominant bit. Connection guidance Connect to CANH in the twisted pair.
STBY	Operating-mode input	LOW selects Normal mode; HIGH selects Standby with a filtered low-power receiver. Connection guidance Hold LOW for the example, or control from a VIO-compatible GPIO. Internal pull-up favors standby if left open; drive explicitly.

Logic and mode behavior

LOW / HIGH relative to VIO

Manufacturer-referenced values6 parameters

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Parameter	Value	Conditions / notes
Normal, TXD LOW	Driver requests dominant	STBY LOW; RXD LOW if dominant is established
Normal, TXD HIGH	Driver releases to recessive	Another node may still force dominant
Normal, bus dominant	RXD LOW	Receiver reflects differential bus state
Normal, bus recessive	RXD HIGH	Receiver output is referenced to VIO
Standby	Driver disabled; filtered reception	STBY HIGH; LOW on RXD indicates wake-up activity
Unpowered / brownout	Bus driver high impedance	Observe specified supply sequencing and thresholds

The mode input has an internal pull-up. Do not leave it floating when Normal mode is intended.

Operating and logic limits

Selected E grade · −40 to +125°C

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
VDD	4.5–5.5 V	Bus transmitter and receiver supply
VIO	1.8–5.5 V	TXD, RXD and STBY voltage domain
Input HIGH	≥ 0.7 × VIO	TXD and STBY
Input LOW	≤ 0.3 × VIO	TXD and STBY
RXD HIGH	≥ VIO − 0.4 V	−1 mA output current
RXD LOW	≤ 0.4 V	4 mA output current
Normal VDD current	5 mA typ. / 10 mA max. recessive	45 mA typ. / 70 mA max. dominant; 60 Ω load
Standby total	5 µA typical / 15 µA maximum	MCP2562; includes IIO

Typical values describe nominal behavior and are not guaranteed limits.

Differential voltage levels

VDD 4.5–5.5 V; stated load conditions

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
CANH dominant	3.5 V typical	2.75–4.5 V; differential load 50–65 Ω
CANL dominant	1.5 V typical	0.5–2.25 V; differential load 50–65 Ω
Dominant differential output	2.0 V typical; 1.5–3.0 V	CANH − CANL; load 50–65 Ω
Recessive output	VDD / 2 typical on each line	No load; differential voltage near zero
Normal receiver recessive	−1.0 to +0.5 V differential	Specified bus common-mode conditions
Normal receiver dominant	+0.9 V to VDD differential	Transition region between 0.5 and 0.9 V
Receiver common-mode characterization	−12 to +12 V	Production tested from −2 to +7 V; see manufacturer note

Voltage states are bus conditions, not separate logic supply levels.

Timing and protection

Electrical table conditions apply

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Bit rate	14.4 kbit/s to 1 Mbit/s	Dominant timeout constrains very slow traffic
TXD LOW → bus dominant	70 ns maximum	Propagation, specified test load
TXD HIGH → bus recessive	125 ns maximum	Propagation, specified test load
Bus dominant → RXD LOW	70 ns maximum	Normal mode
Standby wake-up filter	1 µs typical; 0.5–4 µs	Not the Normal-mode data path
Dominant timeout	1.25 ms typical	TXD must return HIGH to release transmitter lockout
Thermal shutdown	175°C typical junction	Protection threshold, not a permitted operating temperature

Protection does not replace a network-specific transient, grounding or isolation design.

3.3 V controller connection

A CAN controller is required

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
VDD3	+5 V with 100 nF to GND	Keep bypass close to supply pins
VIO5	+3.3 V with 100 nF to GND	Same rail as controller I/O
VSS2	Common reference	Join controller ground
TXD1 / RXD4	CAN_TX / CAN_RX	Use the controller’s CAN peripheral, not UART
STBY8	GND in the always-on example	Use a GPIO if standby is required
CANH7 / CANL6	Twisted pair to other CAN nodes	Keep topology and stubs appropriate to bit rate
Termination	120 Ω at each physical cable end	Two parallel end loads are nominally 60 Ω

Another active node must share timing and acknowledge valid frames.

Packages and stress ratings

MCP2562-E/P · PDIP-8

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
PDIP-8 P	2.54 mm lead pitch	Through-hole version shown
SOIC-8 SN	1.27 mm lead pitch	Narrow SMD version shown
Selected grade E	−40 to +125°C ambient	H grade reaches +150°C; not selected here
VDD / VIO absolute maximum	7 V	Normal operation ends at 5.5 V
Bus pins absolute DC range	−58 to +58 V	Stress rating, not receiver operating common mode
Storage range	−55 to +150°C	Unpowered
MCP2561 difference	Pin 5 is SPLIT, not VIO	Do not substitute its wiring for MCP2562

Use the exact ordering code and current manufacturer drawing when reviewing PCB lands.