MCP6022Dual rail-to-rail CMOS operational amplifier

Two fast analog channels from a single low-voltage supply.

Manufacturer-referenced

Microchip Technology · MCP6022-I/P

PDIP-8DS20001685F · April 2023

MCP6022 integrates two CMOS operational amplifiers with rail-to-rail inputs and outputs. Both channels share a 2.5–5.5 V supply, but each has independent signal inputs, feedback and output. The typical gain-bandwidth product is 10 MHz. The example uses a 5 V supply and a common 0.50 V DC input. Channel A has a gain of three and channel B is a voltage follower, producing ideal outputs of 1.50 V and 0.50 V. Local 100 nF bypass and nearby 1 µF bulk storage help keep the supply quiet. This page follows the industrial MCP6022-I/P and MCP6022-I/SN parts, specified from −40 to +85°C. It is the dual amplifier: the reference-voltage output and chip-select feature of certain single-amplifier family members do not exist on MCP6022.

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Real View

MCP6022-I/P black PDIP-8 package with silver contacts and readable marking.

Pinout

MCP6022PDIP-8Top view

PCB Footprint

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8Physical pins MCP6022-I/PPDIP-8 Manufacturer-referencedMicrochip Technology

Pin diagram

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Package map

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MCP6022PDIP-8Top view

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PIN 1 · Analog outputs

OUT1

Analog output

Function

Channel A output.

How to connect

Return to IN1− through 20 kΩ; connect a high-impedance meter.

Key specifications

Use independent feedback for each channel, common supply decoupling and clean high-impedance nodes. Allow for source and output loading even in a rail-to-rail circuit.

Supply range2.5–5.5 V

Gain bandwidth10 MHz typical

Voltage noise8.7 nV/√Hz at 10 kHz · typical

Industrial range−40 to +85 °C

Operating profile

Supply, signals and operating conditions

MCP6022 operating profile
Parameter	Value	Conditions / notes
Selected package	PDIP-8	MCP6022-I/P
Independent channels	2	Separate feedback; shared rails
Example outputs	1.50 / 0.50	V · ideal A / B

Package details

MCP6022-I/P · PDIP-8

Selected package

Selected MCP6022 physical package
Property	Details
Manufacturer	Microchip Technology
Part number	MCP6022-I/P
Package	PDIP-8
Connections	8 pins
Mounting	Through-hole
Lead pitch	2.54 mm
Package code	PDIP-8
Thermal reference	See operating and package limits

Operating conditions

MCP6022-I/P and MCP6022-I/SN

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Supply span	2.5–5.5 V	VDD minus VSS
Industrial ambient range	−40 to +85°C	Selected I-grade parts
Input common-mode interval	VSS − 0.3 V to VDD + 0.3 V	Input voltage and current protection limits still apply
Example rails	VDD8 = 5 V; VSS4 = 0 V	Supply return is also signal ground
Typical current per amplifier	1.0 mA	0.5 mA minimum; 1.35 mA maximum, unloaded at 25°C
Nominal two-channel current	2.0 mA	Before external load current
No VREF or chip-select pin	MCP6022 has two amplifiers	Do not apply MCP6021/6023 single-amplifier pin functions

Unless stated otherwise, electrical values follow the manufacturer 25°C, 2.5–5.5 V, midsupply signal and 10 kΩ-to-midsupply test conditions.

Input accuracy and output swing

Industrial grade · 25°C unless stated

Manufacturer specifications 9 parameters

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Parameter	Value	Conditions / notes
Input offset voltage	±500 µV maximum	VCM = 0 V; selected industrial grade
Typical offset drift	±3.5 µV/°C	Characterized over −40 to +125°C
Input bias current	1 pA typical	Room temperature
Bias current at +85°C	30 pA typical; 150 pA maximum	Industrial temperature parts
Input offset current	±1 pA typical	Room temperature
CMRR over full common-mode range	74 dB minimum; 90 dB typical	VDD = 5 V; VCM = −0.3 to 5.3 V
Supply rejection	74 dB minimum; 90 dB typical	VCM = 0 V
Open-loop gain	90 dB minimum; 110 dB typical	VCM = 0; VOUT = VSS + 0.3 to VDD − 0.3 V
Output swing endpoints	VSS + 15 mV to VDD − 20 mV	10 kΩ to midsupply; 0.5 V differential overdrive

The swing test uses input overdrive; do not treat its endpoints as precision closed-loop headroom at arbitrary load.

Speed and noise

Typical values at manufacturer AC conditions

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Gain-bandwidth product	10 MHz	Closed-loop bandwidth depends on noise gain
Slew rate	7.0 V/µs	Large-signal slope limit
Phase margin	65°	Gain +1; CL = 60 pF
Settling to 0.2%	250 ns	Gain +1; 100 mV peak-to-peak output
Voltage-noise density	8.7 nV/√Hz	10 kHz
Integrated low-frequency noise	2.9 µV peak-to-peak	0.1–10 Hz
Current-noise density	3 fA/√Hz	1 kHz
THD + noise	0.00053%	1 kHz; gain +1; VDD 5 V; output 0.25–3.25 V; 22 kHz bandwidth

Small-signal bandwidth, large-signal slew and settling describe different limitations.

Supply and feedback layout

A fast CMOS amplifier needs short loops

Manufacturer specifications 7 parameters

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Parameter	Value	Conditions / notes
Local bypass	100 nF in the example	Manufacturer recommends 10–100 nF within 2 mm of VDD
Nearby bulk storage	1 µF or larger	Within 100 mm; may be shared by nearby analog parts
Feedback network	Short routes around each input/output pair	The 20 kΩ / 10 kΩ example is a low-frequency demonstration
Parasitic capacitance	Check feedback resistance against input and board capacitance	High-frequency noise gain can rise and phase margin can fall
Capacitive loads	Choose an isolation network for the actual load	Do not assume stable direct drive of long cables
Input leakage	Clean high-impedance nodes	Temperature, moisture and contamination increase errors
Unused channel	Stable negative feedback to a valid reference	Do not leave its inputs floating

Use the manufacturer capacitive-load and feedback-capacitance guidance for high-frequency designs.

Stress limits and grade distinction

Absolute ratings are not normal operating targets

Manufacturer specifications 6 parameters

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Parameter	Value	Conditions / notes
Absolute supply	7.0 V	Normal operating upper limit is 5.5 V
Analog-input current	±2 mA absolute maximum	Provide the specified protection if inputs can exceed safe voltage limits
Output / supply-pin current	±30 mA absolute maximum	Not a recommended continuous load current
Junction / storage	150°C maximum / −65 to +150°C	Do not substitute these for ambient operating limits
Extended E-grade offset	±250 µV at 25°C, VDD 5 V, VCM 0 V	A different grade; not used as the I-grade limit here
Extended E-grade ambient	−40 to +125°C	The selected I-grade page uses −40 to +85°C

Power dissipation and board thermal conditions can constrain usable current before an absolute limit is reached.

Two-channel amplifier example

5 V single supply · common ground

Manufacturer specifications 8 parameters

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Parameter	Value	Conditions / notes
Input VIN	0.50 V	Pins 3 and 5; common signal ground
Channel A feedback	20 kΩ	OUT1 pin 1 to IN1− pin 2
Channel A ground resistor	10 kΩ	IN1− pin 2 to 0 V
Channel A ideal output	1.50 V	0.50 × (1 + 20 / 10)
Channel B feedback	Direct connection	OUT2 pin 7 to IN2− pin 6
Channel B ideal output	0.50 V	Unity-gain follower
Bypass capacitors	100 nF	VDD pin 8 to ground pin 4
Bulk bypass	1 µF minimum	Nearby between +5 V and GND; may be shared

The supply return and signal ground are common. Keep the bypass loop short.

Physical pin reference

MCP6022-I/P · PDIP-8

Manufacturer specifications 5 parameters

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Parameter	Value	Conditions / notes
Lead pitch	2.54 mm	Through-hole
Channel A	OUT1 1; IN1− 2; IN1+ 3	Independent feedback loop
Channel B	IN2+ 5; IN2− 6; OUT2 7	Independent feedback loop
Supply	VSS 4; VDD 8	Shared by both channels
Package orientation	Top view; pin 1 at the marker	Counterclockwise numbering

This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Analog outputs2 pins

Analog inputs4 pins

Ground1 pin

Supply1 pin

MCP6022 working principle: illustrated functional stages, basic circuit and connections — Select the diagram to read it at full resolution.

How it works

3 stages · Explore one step at a time

Step 1 / 3

Compare each input pair

Complementary CMOS input paths cover the common-mode range near both supply rails. Their offset and bias behavior still varies with common-mode voltage and temperature; rail-to-rail does not remove input protection limits.

Step 2 / 3

Set two different gains

Channel A uses 20 kΩ feedback and 10 kΩ to the common ground, giving a gain of three. Channel B directly feeds its output back to its negative input, giving unity gain.

Step 3 / 3

Check headroom and speed

With a 0.50 V input, the ideal outputs are 1.50 V and 0.50 V. Real output also depends on input offset, resistor accuracy, loading, noise and signal frequency.

MCP6022-I/P on 5 V supply. VIN 0.50 V connects to pins 3 and 5. Pin 1 feeds pin 2 through 20 kΩ; 10 kΩ joins pin 2 to 0 V. Pin 7 joins pin 6 directly. 100 nF bypasses VDD8 to ground4. — All VIN labels share one signal. All ground symbols are connected to VSS pin 4.

Connect it, step by step

Follow the component values and pin connections

Connect power

Use +5 V at VDD pin 8 and ground at VSS pin 4, with 100 nF between them.

Wire the feedback

Add the 20 kΩ / 10 kΩ network to channel A and join pins 7 and 6 for channel B.

Read both outputs

At a nominal input of 0.50 V, expect about 1.50 V from A and 0.50 V from B under light DC loading.

Two CMOS-input amplifier channels inside a compact MCP6022 IC. A: positive 3, negative 2, output 1. B: positive 5, negative 6, output 7. Shared supplies 8 and 4. — Functional cutaway; internal compensation is included. External feedback sets the gain.

Explore the circuit

Select a stage to see its role and connections

Input stages

Gain and compensation

Each channel has an internal voltage-gain path and frequency compensation.

Output drivers

Each channel drives a compatible load close to its rails. The remaining headroom depends on load and current direction. The short-circuit current is a fault characteristic, not a normal drive-current promise.

Selected packagePDIP-8MCP6022-I/P

Physical connections8 pinsPackage-specific numbering

Reference collection8 tables50 parameters & pin functions