TC4420 Reference Tables
Search the TC4420 pin reference and manufacturer-referenced specification tables.
Pin reference
Signal names, electrical functions and connection guidance
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| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| VDD | Supply | Driver supplyConnection guidanceJoin pin 8 to +12 V in the example; decouple locally. | |
| INPUT | Input / control | Non-inverting logic inputConnection guidanceApply 0–5 V PWM with a common ground; use a 10 kΩ pulldown. | |
| NC | No connection | Unused contactConnection guidanceLeave unconnected. | |
| GND | Supply | Driver returnConnection guidanceJoin pin 5 and the MOSFET source with a short return. | |
| GND | Supply | Duplicated driver returnConnection guidanceConnect together with pin 4. | |
| OUTPUT | Output | Gate-drive outputConnection guidanceJoin pin 7; connect through 10 Ω to the MOSFET gate. | |
| OUTPUT | Output | Duplicated gate-drive outputConnection guidanceConnect together with pin 6. | |
| VDD | Supply | Duplicated supplyConnection guidanceConnect together with pin 1. |
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Supply and logic
TC4420 C grade
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Driver supply | 4.5–18 V | Recommended operating range |
| Ambient | 0–70°C | Selected CPA / COA |
| Guaranteed HIGH input | At least 2.4 V | DC characteristic |
| Guaranteed LOW input | At most 0.8 V | DC characteristic |
| Input current | −10 to +10 µA | 0 V ≤ VIN ≤ VDD |
| Input-to-output function | Non-inverting | TC4429 is the inverting alternative |
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Keep the input defined during startup and supply transitions.
Drive and timing
Manufacturer test conditions
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Peak output current | 6 A typical | VDD = 18 V; not continuous |
| Output resistance HIGH | 2.1 Ω typical; 2.8 Ω max | 18 V; 10 mA |
| Output resistance LOW | 1.5 Ω typical; 2.5 Ω max | 18 V; 10 mA |
| Rise / fall time | 25 ns typical; 35 ns max | 2500 pF load; Figure 4-1 |
| Propagation delay | 55 ns typical; 75 ns max | Figure 4-1 |
| Supply current, input HIGH | 0.45 mA typical; 1.5 mA max | VIN = 3 V, static |
| Supply current, input LOW | 55 µA typical; 150 µA max | VIN = 0 V, static |
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Actual gate current is limited by driver resistance, external resistor, wiring and gate voltage.
Low-side gate drive
12 V driver, 5 V logic
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply contacts | VDD1 and VDD8 together | 100 nF + 1 µF local bypass to GND4/5 |
| Output contacts | OUTPUT6 and OUTPUT7 together | 10 Ω series gate resistor |
| MOSFET source | GND | Use a suitable N-channel device and separate load-current routing |
| Gate pulldown | 100 kΩ | Gate to source |
| Logic pulldown | 10 kΩ | INPUT2 to GND |
| Example gate-charge budget | Qg = 20 nC, f = 20 kHz | Average charge current Qg × f = 0.4 mA |
| Gate-charge power | Qg × VDD × f = 4.8 mW | Illustrative, excludes driver static and crossover losses |
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Gate charge is a selected MOSFET parameter, not a TC4420 specification.
Package and stress
TC4420CPA · PDIP-8
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Pitch | 2.54 mm | Through-hole |
| Supply absolute maximum | 20 V | Stress ceiling |
| Power at TA ≤70°C | 730 mW PDIP; 470 mW SOIC | Derate and check actual mounting |
| Duplicate pins | All must be connected | Supply, ground and output pairs |
| Inductive load | Requires an appropriate flyback/clamp network | The shown teaching load is resistive |
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Do not route continuous load current through the driver output; it drives the gate.
External connections
Physical package contacts
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| Parameter | Value | Conditions / notes |
|---|---|---|
| 1 · VDD | Driver supply | Join pin 8 to +12 V in the example; decouple locally. |
| 2 · INPUT | Non-inverting logic input | Apply 0–5 V PWM with a common ground; use a 10 kΩ pulldown. |
| 3 · NC | Unused contact | Leave unconnected. |
| 4 · GND | Driver return | Join pin 5 and the MOSFET source with a short return. |
| 5 · GND | Duplicated driver return | Connect together with pin 4. |
| 6 · OUTPUT | Gate-drive output | Join pin 7; connect through 10 Ω to the MOSFET gate. |
| 7 · OUTPUT | Duplicated gate-drive output | Connect together with pin 6. |
| 8 · VDD | Duplicated supply | Connect together with pin 1. |
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Connect all supply and return contacts; leave only explicitly unused contacts open.
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